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ddr3_dimm_micron_sim.sh - Script generated by export_simulation (Vivado v2021.2 (64-bit)-id)
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr3
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr3_dimm
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr3_dimm_micron_sim
Vivado Simulator v2021.2
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
Running: /tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:204]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:135]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:156]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:157]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:158]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:159]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:160]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:161]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:163]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:165]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:250]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:275]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:276]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:281]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:283]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:319]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:325]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:326]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:374]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:375]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'TCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:426]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:427]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:452]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:453]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:458]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:460]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:497]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:498]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:499]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:501]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:504]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:506]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:536]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:575]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:576]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:580]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:582]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:583]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:631]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:632]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:700]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:701]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:747]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:163]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:164]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cke' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:165]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 's_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:166]
WARNING: [VRFC 10-3091] actual bit length 14 differs from formal bit length 16 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:171]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'odt' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:172]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:173]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:174]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:203]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:204]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:205]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:206]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:207]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:208]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:209]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:210]
WARNING: [VRFC 10-5021] port 'scl' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:161]
WARNING: [VRFC 10-5021] port 'i_controller_dm' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v:119]
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.ddr3_controller(CONTROLLER_CLK_P...
Compiling module unisims_ver.OSERDESE2(DATA_RATE_OQ="SDR",DAT...
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="SDR",DAT...
Compiling module unisims_ver.OBUFDS
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT...
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
Compiling module unisims_ver.IOBUF(IOSTANDARD="SSTL15",SLEW="...
Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="...
Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE...
Compiling module unisims_ver.OBUF(SLEW="FAST")
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT...
Compiling module unisims_ver.IOBUFDS(IOSTANDARD="DIFF_SSTL15"...
Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="...
Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE...
Compiling module unisims_ver.IDELAYCTRL_default
Compiling module xil_defaultlib.ddr3_phy(CONTROLLER_CLK_PERIOD=1...
Compiling module xil_defaultlib.ddr3_top(CONTROLLER_CLK_PERIOD=1...
Compiling module xil_defaultlib.ddr3_default
Compiling module xil_defaultlib.ddr3_dimm_default
Compiling module xil_defaultlib.ddr3_dimm_micron_sim
Compiling module xil_defaultlib.glbl
Built simulation snapshot ddr3_dimm_micron_sim
****** xsim v2021.2 (64-bit)
**** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
**** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl
# xsim {ddr3_dimm_micron_sim} -autoloadwcfg -tclbatch {cmd.tcl} -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim}
Time resolution is 1 ps
source cmd.tcl
## set curr_wave [current_wave_config]
## if { [string length $curr_wave] == 0 } {
## if { [llength [get_objects]] > 0} {
## add_wave /
## set_property needs_save false [current_wave_config]
## } else {
## send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
## }
## }
## run -all
Test ns_to_cycles() function:
ns_to_cycles(15) = 3 = 2 [exact]
ns_to_cycles(14.5) = 3 = 2 [round-off]
ns_to_cycles(11) = 3 = 2 [round-up]
Test nCK_to_cycles() function:
ns_to_cycles(16) = 4 = 4 [exact]
ns_to_cycles(15) = 4 = 4 [round-off]
ns_to_cycles(13) = 4 = 4 [round-up]
Test ns_to_nCK() function:
ns_to_cycles(15) = 12 = 6 [exact]
ns_to_cycles(14.875) = 12 = 6 [round-off]
ns_to_cycles(13.875) = 12 = 6 [round-up]
ns_to_nCK(tRCD) = 11 = 6 [WRONG]
tRTP = 7.5 = 10.000000
ns_to_nCK(tRTP) = 6= 4.000000 [WRONG]
Test nCK_to_ns() function:
ns_to_cycles(4) = 5 = 10 [exact]
ns_to_cycles(14.875) = 4 = 8 [round-off]
ns_to_cycles(13.875) = 7 = 13 [round-up]
Test nCK_to_ns() function:
ns_to_cycles(4) = 5 = 10 [exact]
ns_to_cycles(14.875) = 4 = 8 [round-off]
ns_to_cycles(13.875) = 7 = 13 [round-up]
Test $floor() function:
$floor(5/2) = 2.5 = 2
$floor(9/4) = 2.25 = 2
$floor(9/4) = 2 = 2
$floor(9/5) = 1.8 = 1
DELAY_COUNTER_WIDTH = 16
DELAY_SLOT_WIDTH = 19
serdes_ratio = 4
wb_addr_bits = 24
wb_data_bits = 512
wb_sel_bits = 64
READ_SLOT = 2
WRITE_SLOT = 3
ACTIVATE_SLOT = 0
PRECHARGE_SLOT = 1
DELAYS:
ns_to_nCK(tRCD): 6
ns_to_nCK(tRP): 6
ns_to_nCK(tRTP): 4
tCCD: 4
(CL_nCK + tCCD + 3'd2 - CWL_nCK): 7
(CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15
(CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13
$signed(4'b1100)>>>4: 1111
PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1
ACTIVATE_TO_WRITE_DELAY = 3 = 0
ACTIVATE_TO_READ_DELAY = 2 = 0
READ_TO_WRITE_DELAY = 2 = 1
READ_TO_READ_DELAY = 0 = 0
READ_TO_PRECHARGE_DELAY = 1 =1
WRITE_TO_WRITE_DELAY = 0 = 0
WRITE_TO_READ_DELAY = 4 = 3
WRITE_TO_PRECHARGE_DELAY = 5 = 4
STAGE2_DATA_DEPTH = 2 = 2
READ_ACK_PIPE_WIDTH = 6
ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
[x ps] MRS -> [ 7500 ps] MRS -> [195000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 308524.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 308524.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 308524.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 308524.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 308524.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 308524.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 308524.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 308524.0 ps WARNING: 200 us is required before RST_N goes inactive.
[510000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 819800.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 819800.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 819800.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 819800.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 819800.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 819800.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 819800.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 819800.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
[370000 ps] MRS ->
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1192300.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1192300.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1192300.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1192300.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1192300.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1192300.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1192300.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1192300.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
[10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [40000 ps] ZQC ->
[1290000 ps] PRE @ (0) -> [30000 ps] MRS -> [10000 ps] NOP -> [40000 ps] NOP -> [262500 ps] RD @ (0, 0) ->
[170000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [460000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [460000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [460000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [460000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [460000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [460000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [460000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) ->
[190000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [227500 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP ->
[110000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72197300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72199800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72202300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72204800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72207300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72209800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72212300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72214800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72217300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72219800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72347300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72349800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72352300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72354800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72357300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72359800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72362300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72364800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72367300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72369800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74447300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74449800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74452300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74454800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74457300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74459800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74462300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74464800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74467300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74469800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74597300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74599800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74602300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74604800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74607300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74609800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74612300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74614800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74617300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74619800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76697300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76699800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76702300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76704800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76707300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76709800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76712300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76714800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76717300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76719800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76847300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76849800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76852300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76854800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76857300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76859800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76862300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76864800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76867300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76869800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 78947300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 78949800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 78952300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 78954800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 78957300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 78959800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 78962300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 78964800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 78967300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 78969800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79097300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79099800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79102300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79104800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79107300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79109800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79112300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79114800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79117300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79119800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81197300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81199800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81202300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81204800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81207300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81209800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81212300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81214800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81217300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81219800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81347300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81349800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81352300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81354800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81357300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81359800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81362300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81364800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81367300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81369800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83447300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83449800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83452300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83454800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83457300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83459800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83462300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83464800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83467300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83469800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83597300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83599800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83602300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83604800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83607300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83609800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83612300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83614800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83617300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83619800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85697300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85699800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85702300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85704800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85707300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85709800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85712300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85714800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85717300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85719800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85847300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85849800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85852300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85854800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85857300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85859800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85862300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85864800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85867300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85869800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 85997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 85999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 87947300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 87949800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 87952300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 87954800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 87957300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 87959800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 87962300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 87964800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 87967300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 87969800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 88097300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 88099800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 88102300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 88104800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 88107300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 88109800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 88112300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 88114800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 88117300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 88119800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 88247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 88249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 88252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 88254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 88257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 88259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 88262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 88264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 88267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 88269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
[17870000 ps] MRS -> [10000 ps] NOP -> [40000 ps] PRE @ (0) -> [30000 ps] REF ->
[360000 ps] NOP -> [37500 ps] ACT @ (0, 0) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [37500 ps] RD @ (0, 0) ->
[372500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) ->
[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) ->
[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) ->
[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) ->
[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) ->
[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) ->
[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) ->
[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) ->
[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) ->
[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) ->
[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) ->
[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) ->
[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) ->
[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) ->
[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) ->
[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) ->
[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) ->
[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) ->
[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) ->
[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) ->
[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) ->
[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) ->
[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) ->
[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) ->
[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 0) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) ->
[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) ->
[10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) ->
[10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) ->
[10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) ->
[10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) ->
[10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) ->
[10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) ->
[10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) ->
[10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) ->
[10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) ->
[10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) ->
[10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) ->
[10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) ->
[10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) ->
[10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) ->
[10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) ->
[10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) ->
[10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) ->
[10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) ->
[10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) ->
[10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) ->
[10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) ->
[10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) ->
[10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) ->
[10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) ->
[10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 0) -> [ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) ->
[10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) ->
[10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) ->
[10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) ->
[10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) ->
[10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) ->
[10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) ->
[10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) ->
[10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) ->
[10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) ->
[10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) ->
[10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) ->
[10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) ->
[10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) ->
[10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) ->
[10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) ->
[10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) ->
[10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) ->
[10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) ->
[10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) ->
[10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) ->
[10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) ->
[10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) ->
[10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) ->
[10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) ->
[10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) ->
[ 2500 ps] ACT @ (3, 0) -> [ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) ->
[10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) ->
[10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) ->
[10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) ->
[10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) ->
[10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) ->
[10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) ->
[10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) ->
[10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) ->
[10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) ->
[10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) ->
[10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) ->
[10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) ->
[10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) ->
[10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) ->
[10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) ->
[10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) ->
[10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) ->
[10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) ->
[10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) ->
[10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) ->
[10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) ->
[10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) ->
[10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) ->
[10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) ->
[10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 0) ->
[ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) ->
[10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) ->
[10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) ->
[10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) ->
[10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) ->
[10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) ->
[10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) ->
[10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) ->
[10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) ->
[10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) ->
[10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) ->
[10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) ->
[10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) ->
[10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) ->
[10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) ->
[10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) ->
[10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) ->
[10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) ->
[10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) ->
[10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) ->
[10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) ->
[10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) ->
[10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) ->
[10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) ->
[10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) ->
[10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 0) -> [ 7500 ps] WR @ (4, 976) ->
[10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) ->
[10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) ->
[10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) ->
[10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) ->
[10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) ->
[10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) ->
[10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) ->
[10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) ->
[10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) ->
[10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) ->
[10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) ->
[10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) ->
[10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) ->
[10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) ->
[10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) ->
[10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) ->
[10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) ->
[10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) ->
[10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) ->
[10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [ 5000 ps] NOP ->
[ 5000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> [65000 ps] PRE @ (0) -> [30000 ps] REF ->
[360000 ps] NOP -> [17500 ps] ACT @ (5, 0) -> [17500 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) ->
[10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) ->
[10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) ->
[10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) ->
[10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) ->
[10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 0) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) ->
[10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) ->
[10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) ->
[10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) ->
[10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) ->
[10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> [10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) ->
[10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> [10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) ->
[10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) ->
[10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) ->
[10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) ->
[10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) ->
[10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) ->
[10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) ->
[10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) ->
[10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) ->
[10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) ->
[10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) ->
[10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) ->
[10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) ->
[10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) ->
[10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) ->
[10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) ->
[10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) ->
[10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) ->
[10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) ->
[10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) ->
[10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 0) -> [ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) ->
[10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) ->
[10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) ->
[10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) ->
[10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) ->
[10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) ->
[10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) ->
[10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) ->
[10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) ->
[10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) ->
[10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) ->
[10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) ->
[10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) ->
[10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) ->
[10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) ->
[10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) ->
[10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) ->
[10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) ->
[10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) ->
[10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) ->
[10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) ->
[10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) ->
[10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) ->
[10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) ->
[10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) ->
[10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) ->
[ 2500 ps] ACT @ (0, 1) -> [ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) ->
[10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) ->
[10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) ->
[10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) ->
[10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) ->
[10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) ->
[10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) ->
[10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) ->
[10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) ->
[10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) ->
[10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) ->
[10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) ->
[10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) ->
[10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) ->
[10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) ->
[10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) ->
[10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) ->
[10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) ->
[10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) ->
[10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) ->
[10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) ->
[10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) ->
[10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) ->
[10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) ->
[10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) ->
[10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 1) ->
[ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) ->
[10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 0) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) ->
[10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) ->
[10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) ->
[10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) ->
[10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) ->
[10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) ->
[10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) ->
[10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) ->
[10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) ->
[10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) ->
[10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) ->
[10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) ->
[10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) ->
[10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) ->
[10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) ->
[10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) ->
[10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) ->
[10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) ->
[10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) ->
[10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) ->
[10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) ->
[10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) ->
[10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) ->
[10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) ->
[10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) ->
[ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 992) ->
[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) ->
[10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) ->
[10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) ->
[10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) ->
[10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) ->
[10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) ->
[10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) ->
[10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) ->
[10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) ->
[10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) ->
[10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) ->
[10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) ->
[10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) ->
[10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) ->
[10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) ->
[10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) ->
[10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) ->
[10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) ->
[10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) ->
[10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) ->
[10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) ->
[10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) ->
[10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) ->
[10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) ->
[10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) ->
[ 5000 ps] ACT @ (2, 0) -> [ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) ->
[10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) ->
[10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) ->
[10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) ->
[10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) ->
[10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) ->
[10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) ->
[10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) ->
[10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) ->
[10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) ->
[10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) ->
[10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) ->
[10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) ->
[10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) ->
[10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) ->
[10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) ->
[10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) ->
[10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) ->
[10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) ->
[10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) ->
[10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) ->
[10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) ->
[10000 ps] RD @ (2, 816) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (2, 0) ->
[15000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) ->
[10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) ->
[10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) ->
[10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> [10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 0) ->
[ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) ->
[10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) ->
[10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) ->
[10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) ->
[10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) ->
[10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> [10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) ->
[10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> [10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) ->
[10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) ->
[10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) -> [10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) ->
[10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) ->
[10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) ->
[10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) ->
[10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) ->
[10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) ->
[10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) ->
[10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) ->
[10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) ->
[10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) ->
[10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) ->
[10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) ->
[10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) ->
[10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) ->
[10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) ->
[10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) ->
[10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) ->
[10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 0) -> [ 5000 ps] RD @ (3, 976) ->
[10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) ->
[10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) ->
[10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) ->
[10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) ->
[10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) ->
[10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) ->
[10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) ->
[10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) ->
[10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) ->
[10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) ->
[10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) ->
[10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) ->
[10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) ->
[10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) ->
[10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) ->
[10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) ->
[10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) ->
[10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) ->
[10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) ->
[10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) ->
[10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) ->
[10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) ->
[10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) ->
[10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) ->
[10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) ->
[10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 0) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) ->
[10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) ->
[10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) ->
[10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) ->
[10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) ->
[10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) ->
[10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) ->
[10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) ->
[10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) ->
[10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) ->
[10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) ->
[10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) ->
[10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) ->
[10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) ->
[10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) ->
[10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) ->
[10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) ->
[10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) ->
[10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) ->
[10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) ->
[10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) ->
[10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) ->
[10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) ->
[10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) ->
[10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) ->
[10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) ->
[10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 0) -> [ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) ->
[10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) ->
[10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) ->
[10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) ->
[10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) ->
[10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) ->
[10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) ->
[10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) ->
[10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) ->
[10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) ->
[10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) ->
[10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) ->
[10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) ->
[10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) ->
[10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) ->
[10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) ->
[10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) ->
[10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) ->
[10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) ->
[10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) ->
[10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) ->
[10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) ->
[10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) ->
[10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) ->
[10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) ->
[10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) ->
[ 5000 ps] ACT @ (7, 0) -> [ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) ->
[10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) ->
[10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) ->
[10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) ->
[10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) ->
[10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) ->
[10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) ->
[10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) ->
[10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) ->
[10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) ->
[10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) ->
[10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) ->
[10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) ->
[10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) ->
[10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) ->
[10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) ->
[10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) ->
[10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) ->
[10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) ->
[10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) ->
[10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) ->
[10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) ->
[10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) ->
[10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) ->
[10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) ->
[10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 1) ->
[ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) ->
[10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) ->
[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) ->
[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) ->
[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) ->
[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) ->
[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) ->
[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) ->
[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) ->
[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) ->
[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) ->
[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) ->
[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) ->
[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) ->
[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) ->
[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) ->
[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) ->
[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) ->
[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) ->
[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) ->
[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) ->
[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) ->
[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) ->
[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [ 7500 ps] NOP ->
[ 2500 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [67500 ps] PRE @ (0) -> [30000 ps] REF ->
[360000 ps] NOP -> [17500 ps] ACT @ (0, 1) -> [15000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) ->
[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 1) -> [ 5000 ps] RD @ (0, 976) ->
[10000 ps] RD @ (0, 984) ->
--------------------------------
DONE TEST 1: FIRST ROW
Number of Operations: 2304
Time Started: 89240 ns
Time Done: 113810 ns
Average Rate: 10 ns/request
--------------------------------
[10000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) ->
FAILED: Address = 1150, expected data = cbcfbe97cbceb097cbcda297cbcc9497cbcb8897cbca7a97cbc96c97cbc85e97cbc75097cbc64297cbc53497cbc42697cbc31897cbc20a97cbc0fe97cbbff097, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 113900000.0 ps
[107500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8192) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) ->
[10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) ->
[10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) ->
[10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) ->
[10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) ->
[10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) ->
[10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) ->
[10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) ->
[10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) ->
[10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) ->
[10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) ->
[10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) ->
[10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) ->
[10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) ->
[10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) ->
[10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) ->
[10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) ->
[10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) ->
[10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) ->
[10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) ->
[10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) ->
[10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) ->
[10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) ->
[10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) ->
[10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 5000 ps] PRE @ (1) ->
[ 5000 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [ 2500 ps] ACT @ (1, 8192) -> [ 7500 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) ->
[10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) ->
[10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) ->
[10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) ->
[10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) ->
[10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) ->
[10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) ->
[10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) ->
[10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) ->
[10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) ->
[10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) ->
[10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) ->
[10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) ->
[10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) ->
[10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) ->
[10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) ->
[10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) ->
[10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) ->
[10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) ->
[10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) ->
[10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) ->
[10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) ->
[10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) ->
[10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) ->
[10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) ->
[10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 8192) ->
[ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) ->
[10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) ->
[10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) ->
[10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) ->
[10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) ->
[10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) ->
[10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) ->
[10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) ->
[10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) ->
[10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) ->
[10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) ->
[10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) ->
[10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) ->
[10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) ->
[10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) ->
[10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) ->
[10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) ->
[10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) ->
[10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) ->
[10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) ->
[10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) ->
[10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) ->
[10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) ->
[10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) ->
[10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) ->
[10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 8192) -> [ 7500 ps] WR @ (2, 976) ->
[10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) ->
[10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) ->
[10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) ->
[10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) ->
[10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) ->
[10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) ->
[10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) ->
[10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) ->
[10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) ->
[10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) ->
[10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) ->
[10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) ->
[10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) ->
[10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) ->
[10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) ->
[10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) ->
[10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) ->
[10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) ->
[10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) ->
[10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) ->
[10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) ->
[10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) ->
[10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) ->
[10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) ->
[10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) ->
[10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 8192) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) ->
[10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) ->
[10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) ->
[10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) ->
[10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) ->
[10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) ->
[10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) ->
[10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) ->
[10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) ->
[10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) ->
[10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) ->
[10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) ->
[10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) ->
[10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) ->
[10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) ->
[10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) ->
[10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) ->
[10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) ->
[10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) ->
[10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) ->
[10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) ->
[10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) ->
[10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) ->
[10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) ->
[10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) ->
[10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) ->
[10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 8192) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) ->
[10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) ->
[10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) ->
[10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) ->
[10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) ->
[10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) ->
[10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) ->
[10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) ->
[10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) ->
[10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) ->
[10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) ->
[10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) ->
[10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) ->
[10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) ->
[10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) ->
[10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) ->
[10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) ->
[10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) ->
[10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) ->
[10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) ->
[10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) ->
[10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) ->
[10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) ->
[10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) ->
[10000 ps] WR @ (5, 896) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) ->
[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (5, 8192) -> [17500 ps] WR @ (5, 928) ->
[10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) ->
[ 2500 ps] ACT @ (6, 8192) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) ->
[10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) ->
[10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) ->
[10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) ->
[10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) ->
[10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) ->
[10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) ->
[10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) ->
[10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) ->
[10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) ->
[10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) ->
[10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) ->
[10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) ->
[10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) ->
[10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) ->
[10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) ->
[10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) ->
[10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) ->
[10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) ->
[10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) ->
[10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) ->
[10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) ->
[10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) ->
[10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) ->
[10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) ->
[10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 8192) ->
[ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) ->
[10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) ->
[10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) ->
[10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) ->
[10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) ->
[10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) ->
[10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) ->
[10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) ->
[10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) ->
[10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) ->
[10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) ->
[10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) ->
[10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) ->
[10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) ->
[10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) ->
[10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) ->
[10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) ->
[10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) ->
[10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) ->
[10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) ->
[10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) ->
[10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) ->
[10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) ->
[10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) ->
[10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) ->
[10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 8193) -> [ 7500 ps] WR @ (7, 976) ->
[10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) ->
[10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) ->
[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) ->
[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) ->
[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) ->
[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) ->
[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) ->
[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) ->
[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) ->
[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) ->
[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) ->
[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) ->
[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) ->
[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) ->
[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) ->
[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) ->
[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) ->
[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) ->
[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) ->
[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) ->
[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) ->
[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) ->
[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) ->
[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) ->
[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) ->
[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 8193) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) ->
[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 8192) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) ->
[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) ->
[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) ->
[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) ->
[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) ->
[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) ->
[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) ->
[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) ->
[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) ->
[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) ->
[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) ->
[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) ->
[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) ->
[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) ->
[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) ->
[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) ->
[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) ->
[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) ->
[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) ->
[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) ->
[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) ->
[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) ->
[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) ->
[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) ->
[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) ->
[10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 8192) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) ->
[10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) ->
[10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) ->
[10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) ->
[10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) ->
[10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) ->
[10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) ->
[10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) ->
[10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) ->
[10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) ->
[10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) ->
[10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) ->
[10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) ->
[10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) ->
[10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) ->
[10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) ->
[10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) ->
[10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) ->
[10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) ->
[10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) ->
[10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) ->
[10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) ->
[10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) ->
[10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) ->
[10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) ->
[10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 8192) -> [ 5000 ps] RD @ (1, 976) ->
[10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) ->
[10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) ->
[10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) ->
[10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) ->
[10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) ->
[10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) ->
[10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) ->
[10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) ->
[10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) ->
[10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) ->
[10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) ->
[10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) ->
[10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) ->
[10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) ->
[10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) ->
[10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) ->
[10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) ->
[10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) ->
[10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) ->
[10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) ->
[10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) ->
[10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) ->
[10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) ->
[10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) ->
[10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> [ 7500 ps] NOP ->
[ 2500 ps] RD @ (2, 952) -> [10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [67500 ps] PRE @ (0) -> [30000 ps] REF ->
[360000 ps] NOP -> [17500 ps] ACT @ (2, 8192) -> [10000 ps] ACT @ (3, 8192) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) ->
[10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) ->
[10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) ->
[10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) ->
[10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) ->
[10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) ->
[10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) ->
[10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) ->
[10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) ->
[10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) ->
[10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) ->
[10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) ->
[10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) ->
[10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) ->
[10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) ->
[10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) ->
[10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) ->
[10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) ->
[10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) ->
[10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) ->
[10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) ->
[10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) ->
[10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) ->
[10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) ->
[10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) ->
[10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) ->
[10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 8192) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) ->
[10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) ->
[10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) ->
[10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) ->
[10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) ->
[10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) ->
[10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) ->
[10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) ->
[10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) ->
[10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) ->
[10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) ->
[10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) ->
[10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) ->
[10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) ->
[10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) ->
[10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) ->
[10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) ->
[10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) ->
[10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) ->
[10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) ->
[10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) ->
[10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) ->
[10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) ->
[10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) ->
[10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) ->
[10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) ->
[ 5000 ps] ACT @ (5, 8192) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) ->
[10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) ->
[10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) ->
[10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) ->
[10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) ->
[10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) ->
[10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) ->
[10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) ->
[10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) ->
[10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) ->
[10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) ->
[10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) ->
[10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) ->
[10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) ->
[10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) ->
[10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) ->
[10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) ->
[10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) ->
[10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) ->
[10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) ->
[10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) ->
[10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) ->
[10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) ->
[10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) ->
[10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) ->
[10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 8192) ->
[ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) ->
[10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) ->
[10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) ->
[10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) ->
[10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) ->
[10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) ->
[10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) ->
[10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) ->
[10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) ->
[10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) ->
[10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) ->
[10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) ->
[10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) ->
[10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) ->
[10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) ->
[10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) ->
[10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) ->
[10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) ->
[10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) ->
[10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) ->
[10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) ->
[10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) ->
[10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) ->
[10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) ->
[10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) ->
[10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 8192) -> [ 5000 ps] RD @ (6, 976) ->
[10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) ->
[10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) ->
[10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) ->
[10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) ->
[10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) ->
[10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) ->
[10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) ->
[10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) ->
[10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) ->
[10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) ->
[10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) ->
[10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) ->
[10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) ->
[10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) ->
[10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) ->
[10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) ->
[10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) ->
[10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) ->
[10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) ->
[10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) ->
[10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) ->
[10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) ->
[10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) ->
[10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) ->
[10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) ->
[10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 8193) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) ->
[10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) ->
[10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) ->
[10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) ->
[10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) ->
[10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) ->
[10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) ->
[10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) ->
[10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) ->
[10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) ->
[10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) ->
[10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) ->
[10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) ->
[10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) ->
[10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) ->
[10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) ->
[10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) ->
[10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) ->
[10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) ->
[10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) ->
[10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) ->
[10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) ->
[10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) ->
[10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) ->
[10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) ->
[10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) ->
[10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 8193) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) ->
--------------------------------
DONE TEST 1: MIDDLE ROW
Number of Operations: 2304
Time Started: 113910 ns
Time Done: 138010 ns
Average Rate: 10 ns/request
--------------------------------
[10000 ps] RD @ (0, 992) ->
[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [47500 ps] NOP -> FAILED: Address = 8389758, expected data = 33cfbf6733ceb16733cda36733cc956733cb896733ca7b6733c96d6733c85f6733c7516733c6436733c5356733c4276733c3196733c20b6733c0ff6733bff167, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 138100000.0 ps
[70000 ps] PRE @ (0) ->
[30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (0, 16383) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) ->
[10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) ->
[10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) ->
[10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) ->
[10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) ->
[10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) ->
[10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) ->
[10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) ->
[10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) ->
[10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) ->
[10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) ->
[10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) ->
[10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) ->
[10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) ->
[10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) ->
[10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) ->
[10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) ->
[10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) ->
[10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) ->
[10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) ->
[10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) ->
[10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) ->
[10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) ->
[10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) ->
[10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) ->
[ 2500 ps] ACT @ (1, 16383) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) ->
[10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) ->
[10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) ->
[10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) ->
[10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) ->
[10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) ->
[10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) ->
[10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) ->
[10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) ->
[10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) ->
[10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) ->
[10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) ->
[10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) ->
[10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) ->
[10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) ->
[10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) ->
[10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) ->
[10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) ->
[10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) ->
[10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) ->
[10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) ->
[10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) ->
[10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) ->
[10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) ->
[10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) ->
[10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 16383) ->
[ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) ->
[10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) ->
[10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) ->
[10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) ->
[10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) ->
[10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) ->
[10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) ->
[10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) ->
[10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) ->
[10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) ->
[10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) ->
[10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) ->
[10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) ->
[10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) ->
[10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) ->
[10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) ->
[10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) ->
[10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) ->
[10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) ->
[10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) ->
[10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) ->
[10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) ->
[10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) ->
[10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) ->
[10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) ->
[10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 16383) -> [ 7500 ps] WR @ (2, 976) ->
[10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) ->
[10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) ->
[10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) ->
[10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) ->
[10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) ->
[10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) ->
[10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) ->
[10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) ->
[10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) ->
[10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) ->
[10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) ->
[10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) ->
[10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) ->
[10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) ->
[10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) ->
[10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) ->
[10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) ->
[10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) ->
[10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) ->
[10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) ->
[10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) ->
[10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) ->
[10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) ->
[10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) ->
[10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) ->
[10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 16383) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) ->
[10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) ->
[10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) ->
[10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) ->
[10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) ->
[10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) ->
[10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) ->
[10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) ->
[10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) ->
[10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) ->
[10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) ->
[10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) ->
[10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) ->
[10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) ->
[10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) ->
[10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) ->
[10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) ->
[10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) ->
[10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) ->
[10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) ->
[10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) ->
[10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) ->
[10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) ->
[10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) ->
[10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) ->
[10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) ->
[10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 16383) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) ->
[10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) ->
[10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) ->
[10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) ->
[10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) ->
[10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) ->
[10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) ->
[10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) ->
[10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) ->
[10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) ->
[10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) ->
[10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) ->
[10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) ->
[10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) ->
[10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) ->
[10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) ->
[10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) ->
[10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) ->
[10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) ->
[10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) ->
[10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) ->
[10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) ->
[10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) ->
[10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) ->
[10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) ->
[10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) ->
[ 2500 ps] ACT @ (6, 16383) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) ->
[10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) ->
[10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) ->
[10000 ps] WR @ (6, 64) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) ->
[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (6, 16383) -> [17500 ps] WR @ (6, 96) ->
[10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) ->
[10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) ->
[10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) ->
[10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) ->
[10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) ->
[10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) ->
[10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) ->
[10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) ->
[10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) ->
[10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) ->
[10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) ->
[10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) ->
[10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) ->
[10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) ->
[10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) ->
[10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) ->
[10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) ->
[10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) ->
[10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) ->
[10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) ->
[10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) ->
[10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 16383) ->
[ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) ->
[10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) ->
[10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) ->
[10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) ->
[10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) ->
[10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) ->
[10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) ->
[10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) ->
[10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) ->
[10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) ->
[10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) ->
[10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) ->
[10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) ->
[10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) ->
[10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) ->
[10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) ->
[10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) ->
[10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) ->
[10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) ->
[10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) ->
[10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) ->
[10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) ->
[10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) ->
[10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) ->
[10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) ->
[10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 0) -> [ 7500 ps] WR @ (7, 976) ->
[10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) ->
[10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) ->
[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) ->
[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) ->
[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) ->
[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) ->
[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) ->
[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) ->
[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) ->
[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) ->
[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) ->
[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) ->
[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) ->
[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) ->
[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) ->
[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) ->
[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) ->
[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) ->
[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) ->
[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) ->
[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) ->
[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) ->
[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) ->
[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) ->
[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) ->
[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 0) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) ->
[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 16383) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) ->
[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) ->
[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) ->
[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) ->
[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) ->
[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) ->
[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) ->
[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) ->
[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) ->
[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) ->
[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) ->
[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) ->
[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) ->
[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) ->
[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) ->
[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) ->
[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) ->
[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) ->
[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) ->
[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) ->
[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) ->
[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) ->
[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) ->
[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) ->
[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) ->
[10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 16383) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) ->
[10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) ->
[10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) ->
[10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) ->
[10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) ->
[10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) ->
[10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) ->
[10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) ->
[10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) ->
[10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) ->
[10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) ->
[10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) ->
[10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) ->
[10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) ->
[10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) ->
[10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) ->
[10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) ->
[10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) ->
[10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) ->
[10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) ->
[10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) ->
[10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) ->
[10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) ->
[10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) ->
[10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) ->
[10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 16383) -> [ 5000 ps] RD @ (1, 976) ->
[10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) ->
[10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) ->
[10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) ->
[10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) ->
[10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) ->
[10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) ->
[10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) ->
[10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) ->
[10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) ->
[10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) ->
[10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) ->
[10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) ->
[10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) ->
[10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) ->
[10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) ->
[10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) ->
[10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) ->
[10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) ->
[10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) ->
[10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) ->
[10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) ->
[10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) ->
[10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) ->
[10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) ->
[10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) ->
[10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 16383) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) ->
[10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) ->
[10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) ->
[10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) ->
[10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> [ 7500 ps] NOP ->
[ 2500 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [67500 ps] PRE @ (0) -> [30000 ps] REF ->
[360000 ps] NOP -> [17500 ps] ACT @ (3, 16383) -> [15000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) ->
[10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) ->
[10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) ->
[10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) ->
[10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) ->
[10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) ->
[10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) ->
[10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) ->
[10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) ->
[10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) ->
[10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) ->
[10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) ->
[10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) ->
[10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) ->
[10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) ->
[10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) ->
[10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) ->
[10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) ->
[10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) ->
[10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) ->
[10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) ->
[10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 16383) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) ->
[10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) ->
[10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) ->
[10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) ->
[10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) ->
[10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) ->
[10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) ->
[10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) ->
[10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) ->
[10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) ->
[10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) ->
[10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) ->
[10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) ->
[10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) ->
[10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) ->
[10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) ->
[10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) ->
[10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) ->
[10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) ->
[10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) ->
[10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) ->
[10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) ->
[10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) ->
[10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) ->
[10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) ->
[10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) ->
[ 5000 ps] ACT @ (5, 16383) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) ->
[10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) ->
[10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) ->
[10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) ->
[10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) ->
[10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) ->
[10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) ->
[10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) ->
[10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) ->
[10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) ->
[10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) ->
[10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) ->
[10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) ->
[10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) ->
[10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) ->
[10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) ->
[10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) ->
[10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) ->
[10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) ->
[10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) ->
[10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) ->
[10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) ->
[10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) ->
[10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) ->
[10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) ->
[10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 16383) ->
[ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) ->
[10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) ->
[10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) ->
[10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) ->
[10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) ->
[10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) ->
[10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) ->
[10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) ->
[10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) ->
[10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) ->
[10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) ->
[10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) ->
[10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) ->
[10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) ->
[10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) ->
[10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) ->
[10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) ->
[10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) ->
[10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) ->
[10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) ->
[10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) ->
[10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) ->
[10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) ->
[10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) ->
[10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) ->
[10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 16383) -> [ 5000 ps] RD @ (6, 976) ->
[10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) ->
[10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) ->
[10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) ->
[10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) ->
[10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) ->
[10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) ->
[10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) ->
[10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) ->
[10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) ->
[10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) ->
[10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) ->
[10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) ->
[10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) ->
[10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) ->
[10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) ->
[10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) ->
[10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) ->
[10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) ->
[10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) ->
[10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) ->
[10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) ->
[10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) ->
[10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) ->
[10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) ->
[10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) ->
[10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 0) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) ->
[10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) ->
[10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) ->
[10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) ->
[10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) ->
[10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) ->
[10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) ->
[10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) ->
[10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) ->
[10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) ->
[10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) ->
[10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) ->
[10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) ->
[10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) ->
[10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) ->
[10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) ->
[10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) ->
[10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) ->
[10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) ->
[10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) ->
[10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) ->
[10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) ->
[10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) ->
[10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) ->
[10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) ->
[10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) ->
[10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) ->
--------------------------------
DONE TEST 1: LAST ROW
Number of Operations: 2304
Time Started: 138110 ns
Time Done: 162620 ns
Average Rate: 10 ns/request
--------------------------------
[10000 ps] RD @ (0, 992) ->
[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> FAILED: Address = 16777342, expected data = 585c7fb0585b71b0585a63b0585955b0585849b058573bb058562db058551fb0585411b0585303b05851f5b05850e7b0584fd9b0584ecbb0584dbfb0584cb1b0, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 162710000.0 ps
[97500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 2852) -> [10000 ps] ACT @ (0, 1773) -> [ 7500 ps] WR @ (4, 960) -> [10000 ps] WR @ (0, 960) -> [35000 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15998) -> [10000 ps] ACT @ (0, 694) -> [17500 ps] WR @ (0, 960) -> [10000 ps] WR @ (4, 952) ->
[45000 ps] PRE @ (4) -> [10000 ps] NOP -> [ 7500 ps] ACT @ (4, 14919) -> [17500 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 13840) -> [17500 ps] WR @ (4, 952) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
[17500 ps] ACT @ (0, 12761) -> [17500 ps] WR @ (0, 952) -> [ 2500 ps] ACT @ (4, 10602) -> [42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11682) ->
[17500 ps] WR @ (0, 952) -> [10000 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9523) -> [17500 ps] WR @ (4, 952) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7365) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8444) -> [17500 ps] WR @ (4, 952) ->
[10000 ps] WR @ (0, 944) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5206) -> [10000 ps] ACT @ (0, 6286) ->
[17500 ps] WR @ (0, 944) -> [10000 ps] WR @ (4, 944) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4127) -> [17500 ps] WR @ (4, 944) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3048) -> [17500 ps] WR @ (4, 944) ->
[10000 ps] WR @ (0, 944) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16194) -> [10000 ps] ACT @ (0, 890) ->
[17500 ps] WR @ (0, 944) -> [10000 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15115) -> [17500 ps] WR @ (4, 936) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12957) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14036) -> [17500 ps] WR @ (4, 936) ->
[10000 ps] WR @ (0, 936) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10798) -> [10000 ps] ACT @ (0, 11878) ->
[17500 ps] WR @ (0, 936) -> [10000 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9719) -> [17500 ps] WR @ (4, 936) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8640) -> [17500 ps] WR @ (4, 936) ->
[10000 ps] WR @ (0, 928) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5402) -> [10000 ps] ACT @ (0, 6482) ->
[17500 ps] WR @ (0, 928) -> [10000 ps] WR @ (4, 928) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4323) -> [17500 ps] WR @ (4, 928) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2165) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3244) -> [17500 ps] WR @ (4, 928) ->
[10000 ps] WR @ (0, 928) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6) -> [10000 ps] ACT @ (0, 1086) ->
[17500 ps] WR @ (0, 928) -> [10000 ps] WR @ (4, 928) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14232) ->
[10000 ps] ACT @ (4, 15311) -> [17500 ps] WR @ (4, 920) -> [10000 ps] WR @ (0, 920) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) ->
[17500 ps] WR @ (0, 920) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) ->
[17500 ps] WR @ (0, 920) -> [10000 ps] WR @ (4, 920) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8836) ->
[10000 ps] ACT @ (4, 9915) -> [17500 ps] WR @ (4, 920) -> [10000 ps] WR @ (0, 920) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) ->
[17500 ps] WR @ (0, 912) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6678) ->
[17500 ps] WR @ (0, 912) -> [10000 ps] WR @ (4, 912) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3440) ->
[10000 ps] ACT @ (4, 4519) -> [17500 ps] WR @ (4, 912) -> [10000 ps] WR @ (0, 912) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) ->
[17500 ps] WR @ (0, 912) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) ->
[17500 ps] WR @ (0, 912) -> [10000 ps] WR @ (4, 912) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14428) ->
[10000 ps] ACT @ (4, 15507) -> [17500 ps] WR @ (4, 904) -> [10000 ps] WR @ (0, 904) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) ->
[17500 ps] WR @ (0, 904) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12270) ->
[17500 ps] WR @ (0, 904) -> [10000 ps] WR @ (4, 904) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9032) ->
[10000 ps] ACT @ (4, 10111) -> [17500 ps] WR @ (4, 904) -> [10000 ps] WR @ (0, 904) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) ->
[17500 ps] WR @ (0, 896) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) ->
[17500 ps] WR @ (0, 896) -> [10000 ps] WR @ (4, 896) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3636) ->
[10000 ps] ACT @ (4, 4715) -> [17500 ps] WR @ (4, 896) -> [10000 ps] WR @ (0, 896) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) ->
[17500 ps] WR @ (0, 896) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1478) ->
[17500 ps] WR @ (0, 896) -> [10000 ps] WR @ (4, 896) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14624) ->
[10000 ps] ACT @ (4, 15703) -> [17500 ps] WR @ (4, 888) -> [10000 ps] WR @ (0, 888) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 12465) -> [10000 ps] ACT @ (0, 13545) -> [17500 ps] WR @ (0, 888) -> [10000 ps] WR @ (4, 888) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 11386) -> [17500 ps] WR @ (4, 888) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9228) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 10307) -> [17500 ps] WR @ (4, 888) -> [10000 ps] WR @ (0, 888) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 7069) -> [10000 ps] ACT @ (0, 8149) -> [17500 ps] WR @ (0, 880) -> [10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 5990) -> [17500 ps] WR @ (4, 880) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3832) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 4911) -> [17500 ps] WR @ (4, 880) -> [10000 ps] WR @ (0, 880) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 1673) -> [10000 ps] ACT @ (0, 2753) -> [17500 ps] WR @ (0, 880) -> [10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 594) -> [17500 ps] WR @ (4, 880) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14820) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 15899) -> [17500 ps] WR @ (4, 872) -> [10000 ps] WR @ (0, 872) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 12661) -> [10000 ps] ACT @ (0, 13741) -> [17500 ps] WR @ (0, 872) -> [10000 ps] WR @ (4, 872) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 11582) -> [17500 ps] WR @ (4, 872) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9424) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 10503) -> [17500 ps] WR @ (4, 872) -> [10000 ps] WR @ (0, 872) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 7265) -> [10000 ps] ACT @ (0, 8345) -> [17500 ps] WR @ (0, 872) -> [10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 6186) -> [17500 ps] WR @ (4, 864) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4028) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 5107) -> [17500 ps] WR @ (4, 864) -> [10000 ps] WR @ (0, 864) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 1869) -> [10000 ps] ACT @ (0, 2949) -> [17500 ps] WR @ (0, 864) -> [10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 790) -> [17500 ps] WR @ (4, 864) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15016) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 16095) -> [17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 12857) -> [10000 ps] ACT @ (0, 13937) -> [17500 ps] WR @ (0, 856) -> [10000 ps] WR @ (4, 856) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) -> [17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9620) -> [17500 ps] WR @ (0, 856) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7461) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) -> [17500 ps] WR @ (0, 856) -> [10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5303) -> [10000 ps] ACT @ (4, 6382) -> [17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 848) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4224) -> [17500 ps] WR @ (0, 848) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2065) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) -> [17500 ps] WR @ (0, 848) -> [10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16291) -> [10000 ps] ACT @ (4, 986) -> [17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 840) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) -> [17500 ps] WR @ (0, 840) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13053) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) -> [17500 ps] WR @ (0, 840) -> [10000 ps] WR @ (4, 840) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10895) -> [10000 ps] ACT @ (4, 11974) -> [17500 ps] WR @ (4, 840) -> [10000 ps] WR @ (0, 840) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) -> [17500 ps] WR @ (0, 840) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7657) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) -> [17500 ps] WR @ (0, 840) -> [10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5499) -> [10000 ps] ACT @ (4, 6578) -> [17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) -> [17500 ps] WR @ (0, 832) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2261) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) -> [17500 ps] WR @ (0, 832) -> [10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 103) -> [10000 ps] ACT @ (4, 1182) -> [17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) -> [17500 ps] WR @ (0, 824) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13249) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) -> [17500 ps] WR @ (0, 824) -> [10000 ps] WR @ (4, 824) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11091) -> [10000 ps] ACT @ (4, 12170) -> [17500 ps] WR @ (4, 824) -> [10000 ps] WR @ (0, 824) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8932) -> [10000 ps] ACT @ (0, 10012) -> [17500 ps] WR @ (0, 824) ->
[10000 ps] WR @ (4, 824) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) -> [17500 ps] WR @ (4, 816) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 5695) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6774) -> [17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3536) -> [10000 ps] ACT @ (0, 4616) -> [17500 ps] WR @ (0, 816) ->
[10000 ps] WR @ (4, 816) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2457) -> [17500 ps] WR @ (4, 816) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 299) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1378) -> [17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14524) -> [10000 ps] ACT @ (0, 15604) -> [17500 ps] WR @ (0, 808) ->
[10000 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13445) -> [17500 ps] WR @ (4, 808) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 11287) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12366) -> [17500 ps] WR @ (4, 808) -> [10000 ps] WR @ (0, 808) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9128) -> [10000 ps] ACT @ (0, 10208) -> [17500 ps] WR @ (0, 808) ->
[10000 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8049) -> [17500 ps] WR @ (4, 800) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 5891) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6970) -> [17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3732) -> [10000 ps] ACT @ (0, 4812) -> [17500 ps] WR @ (0, 800) ->
[10000 ps] WR @ (4, 800) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2653) -> [17500 ps] WR @ (4, 800) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 495) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1574) -> [17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14720) -> [10000 ps] ACT @ (0, 15800) -> [17500 ps] WR @ (0, 792) ->
[10000 ps] WR @ (4, 792) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13641) -> [17500 ps] WR @ (4, 792) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 12562) -> [17500 ps] WR @ (4, 792) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
[17500 ps] ACT @ (0, 11483) -> [17500 ps] WR @ (0, 792) -> [ 2500 ps] ACT @ (4, 9324) -> [42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10404) ->
[17500 ps] WR @ (0, 792) -> [10000 ps] WR @ (4, 792) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7166) ->
[10000 ps] ACT @ (4, 8245) -> [17500 ps] WR @ (4, 792) -> [10000 ps] WR @ (0, 784) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6087) ->
[17500 ps] WR @ (0, 784) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3928) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5008) ->
[17500 ps] WR @ (0, 784) -> [10000 ps] WR @ (4, 784) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1770) ->
[10000 ps] ACT @ (4, 2849) -> [17500 ps] WR @ (4, 784) -> [10000 ps] WR @ (0, 784) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 691) ->
[17500 ps] WR @ (0, 784) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15996) ->
[17500 ps] WR @ (0, 776) -> [10000 ps] WR @ (4, 776) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12758) ->
[10000 ps] ACT @ (4, 13837) -> [17500 ps] WR @ (4, 776) -> [10000 ps] WR @ (0, 776) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11679) ->
[17500 ps] WR @ (0, 776) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10600) ->
[17500 ps] WR @ (0, 776) -> [10000 ps] WR @ (4, 776) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7362) ->
[10000 ps] ACT @ (4, 8441) -> [17500 ps] WR @ (4, 776) -> [10000 ps] WR @ (0, 768) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6283) ->
[17500 ps] WR @ (0, 768) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5204) ->
[17500 ps] WR @ (0, 768) -> [10000 ps] WR @ (4, 768) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1966) ->
[10000 ps] ACT @ (4, 3045) -> [17500 ps] WR @ (4, 768) -> [10000 ps] WR @ (0, 768) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 887) ->
[17500 ps] WR @ (0, 768) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16192) ->
[17500 ps] WR @ (0, 760) -> [10000 ps] WR @ (4, 760) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12954) ->
[10000 ps] ACT @ (4, 14033) -> [17500 ps] WR @ (4, 760) -> [10000 ps] WR @ (0, 760) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11875) ->
[17500 ps] WR @ (0, 760) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10796) ->
[17500 ps] WR @ (0, 760) -> [10000 ps] WR @ (4, 760) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7558) ->
[10000 ps] ACT @ (4, 8637) -> [17500 ps] WR @ (4, 760) -> [10000 ps] WR @ (0, 752) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 5399) -> [10000 ps] ACT @ (0, 6479) -> [17500 ps] WR @ (0, 752) -> [10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 4320) -> [17500 ps] WR @ (4, 752) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2162) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 3241) -> [17500 ps] WR @ (4, 752) -> [10000 ps] WR @ (0, 752) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 3) -> [10000 ps] ACT @ (0, 1083) -> [17500 ps] WR @ (0, 752) -> [10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 15308) -> [17500 ps] WR @ (4, 744) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13150) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 14229) -> [17500 ps] WR @ (4, 744) -> [10000 ps] WR @ (0, 744) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 10991) -> [10000 ps] ACT @ (0, 12071) -> [17500 ps] WR @ (0, 744) -> [10000 ps] WR @ (4, 744) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 9912) -> [17500 ps] WR @ (4, 744) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7754) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 8833) -> [17500 ps] WR @ (4, 744) -> [10000 ps] WR @ (0, 736) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 5595) -> [10000 ps] ACT @ (0, 6675) -> [17500 ps] WR @ (0, 736) -> [10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 4516) -> [17500 ps] WR @ (4, 736) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2358) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 3437) -> [17500 ps] WR @ (4, 736) -> [10000 ps] WR @ (0, 736) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 199) -> [10000 ps] ACT @ (0, 1279) -> [17500 ps] WR @ (0, 736) -> [10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 15504) -> [17500 ps] WR @ (4, 728) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13346) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 14425) -> [17500 ps] WR @ (4, 728) -> [10000 ps] WR @ (0, 728) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 11187) -> [10000 ps] ACT @ (0, 12267) -> [17500 ps] WR @ (0, 728) -> [10000 ps] WR @ (4, 728) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 10108) -> [17500 ps] WR @ (4, 728) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7950) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 9029) -> [17500 ps] WR @ (4, 728) -> [10000 ps] WR @ (0, 720) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 5791) -> [10000 ps] ACT @ (0, 6871) -> [17500 ps] WR @ (0, 720) -> [10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) -> [17500 ps] WR @ (4, 720) -> [10000 ps] WR @ (0, 720) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) -> [17500 ps] WR @ (0, 720) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 395) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) -> [17500 ps] WR @ (0, 720) -> [10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14621) -> [10000 ps] ACT @ (4, 15700) -> [17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) -> [17500 ps] WR @ (0, 712) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11383) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12463) -> [17500 ps] WR @ (0, 712) -> [10000 ps] WR @ (4, 712) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9225) -> [10000 ps] ACT @ (4, 10304) -> [17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) -> [17500 ps] WR @ (0, 704) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5987) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) -> [17500 ps] WR @ (0, 704) -> [10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3829) -> [10000 ps] ACT @ (4, 4908) -> [17500 ps] WR @ (4, 704) -> [10000 ps] WR @ (0, 704) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) -> [17500 ps] WR @ (0, 704) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 591) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) -> [17500 ps] WR @ (0, 704) -> [10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14817) -> [10000 ps] ACT @ (4, 15896) -> [17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) -> [17500 ps] WR @ (0, 696) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11579) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12659) -> [17500 ps] WR @ (0, 696) -> [10000 ps] WR @ (4, 696) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9421) -> [10000 ps] ACT @ (4, 10500) -> [17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) -> [17500 ps] WR @ (0, 696) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6183) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> [17500 ps] WR @ (0, 688) -> [10000 ps] WR @ (4, 688) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4025) -> [10000 ps] ACT @ (4, 5104) -> [17500 ps] WR @ (4, 688) -> [10000 ps] WR @ (0, 688) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) -> [10000 ps] ACT @ (0, 2946) -> [17500 ps] WR @ (0, 688) ->
[10000 ps] WR @ (4, 688) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) -> [17500 ps] WR @ (4, 688) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 15013) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) -> [17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12854) -> [10000 ps] ACT @ (0, 13934) -> [17500 ps] WR @ (0, 680) ->
[10000 ps] WR @ (4, 680) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) -> [17500 ps] WR @ (4, 680) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 9617) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) -> [17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7458) -> [10000 ps] ACT @ (0, 8538) -> [17500 ps] WR @ (0, 680) ->
[10000 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) -> [17500 ps] WR @ (4, 672) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 4221) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5300) -> [17500 ps] WR @ (4, 672) -> [10000 ps] WR @ (0, 672) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2062) -> [10000 ps] ACT @ (0, 3142) -> [17500 ps] WR @ (0, 672) ->
[10000 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) -> [17500 ps] WR @ (4, 672) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 15209) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16288) -> [17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13050) -> [10000 ps] ACT @ (0, 14130) -> [17500 ps] WR @ (0, 664) ->
[10000 ps] WR @ (4, 664) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) -> [17500 ps] WR @ (4, 664) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 9813) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) -> [17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7654) -> [10000 ps] ACT @ (0, 8734) -> [17500 ps] WR @ (0, 664) ->
[10000 ps] WR @ (4, 656) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) -> [17500 ps] WR @ (4, 656) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 4417) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) -> [17500 ps] WR @ (4, 656) -> [10000 ps] WR @ (0, 656) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2258) -> [10000 ps] ACT @ (0, 3338) -> [17500 ps] WR @ (0, 656) ->
[10000 ps] WR @ (4, 656) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 100) -> [10000 ps] ACT @ (4, 1179) ->
[17500 ps] WR @ (4, 656) -> [10000 ps] WR @ (0, 656) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15405) -> [17500 ps] WR @ (0, 648) ->
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14326) -> [17500 ps] WR @ (0, 648) ->
[10000 ps] WR @ (4, 648) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11088) -> [10000 ps] ACT @ (4, 12167) ->
[17500 ps] WR @ (4, 648) -> [10000 ps] WR @ (0, 648) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10009) -> [17500 ps] WR @ (0, 648) ->
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7850) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8930) -> [17500 ps] WR @ (0, 648) ->
[10000 ps] WR @ (4, 640) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5692) -> [10000 ps] ACT @ (4, 6771) ->
[17500 ps] WR @ (4, 640) -> [10000 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4613) -> [17500 ps] WR @ (0, 640) ->
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3534) -> [17500 ps] WR @ (0, 640) ->
[10000 ps] WR @ (4, 640) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 296) -> [10000 ps] ACT @ (4, 1375) ->
[17500 ps] WR @ (4, 640) -> [10000 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15601) -> [17500 ps] WR @ (0, 632) ->
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13442) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14522) -> [17500 ps] WR @ (0, 632) ->
[10000 ps] WR @ (4, 632) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11284) -> [10000 ps] ACT @ (4, 12363) ->
[17500 ps] WR @ (4, 632) -> [10000 ps] WR @ (0, 632) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
[17500 ps] ACT @ (0, 10205) -> [17500 ps] WR @ (0, 632) -> [ 2500 ps] ACT @ (4, 8046) -> [42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9126) ->
[17500 ps] WR @ (0, 632) -> [10000 ps] WR @ (4, 624) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5888) ->
[10000 ps] ACT @ (4, 6967) -> [17500 ps] WR @ (4, 624) -> [10000 ps] WR @ (0, 624) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4809) ->
[17500 ps] WR @ (0, 624) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2650) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) ->
[17500 ps] WR @ (0, 624) -> [10000 ps] WR @ (4, 624) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 492) ->
[10000 ps] ACT @ (4, 1571) -> [17500 ps] WR @ (4, 624) -> [10000 ps] WR @ (0, 624) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 14717) -> [10000 ps] ACT @ (0, 15797) -> [17500 ps] WR @ (0, 616) -> [10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 13638) -> [17500 ps] WR @ (4, 616) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11480) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 12559) -> [17500 ps] WR @ (4, 616) -> [10000 ps] WR @ (0, 616) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 9321) -> [10000 ps] ACT @ (0, 10401) -> [17500 ps] WR @ (0, 616) -> [10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 8242) -> [17500 ps] WR @ (4, 616) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6084) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 7163) -> [17500 ps] WR @ (4, 608) -> [10000 ps] WR @ (0, 608) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 3925) -> [10000 ps] ACT @ (0, 5005) -> [17500 ps] WR @ (0, 608) -> [10000 ps] WR @ (4, 608) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 2846) -> [17500 ps] WR @ (4, 608) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 688) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 1767) -> [17500 ps] WR @ (4, 608) -> [10000 ps] WR @ (0, 608) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 14913) -> [10000 ps] ACT @ (0, 15993) -> [17500 ps] WR @ (0, 600) -> [10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 13834) -> [17500 ps] WR @ (4, 600) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11676) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 12755) -> [17500 ps] WR @ (4, 600) -> [10000 ps] WR @ (0, 600) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 9517) -> [10000 ps] ACT @ (0, 10597) -> [17500 ps] WR @ (0, 600) -> [10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 8438) -> [17500 ps] WR @ (4, 600) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6280) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 7359) -> [17500 ps] WR @ (4, 592) -> [10000 ps] WR @ (0, 592) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 4121) -> [10000 ps] ACT @ (0, 5201) -> [17500 ps] WR @ (0, 592) -> [10000 ps] WR @ (4, 592) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 3042) -> [17500 ps] WR @ (4, 592) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 884) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 1963) -> [17500 ps] WR @ (4, 592) -> [10000 ps] WR @ (0, 592) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 15109) -> [10000 ps] ACT @ (0, 16189) -> [17500 ps] WR @ (0, 584) -> [10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) -> [10000 ps] ACT @ (4, 14030) -> [17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 584) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) -> [17500 ps] WR @ (0, 584) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9713) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) -> [17500 ps] WR @ (0, 584) -> [10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7555) -> [10000 ps] ACT @ (4, 8634) -> [17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 576) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) -> [17500 ps] WR @ (0, 576) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4317) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) -> [17500 ps] WR @ (0, 576) -> [10000 ps] WR @ (4, 576) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2159) -> [10000 ps] ACT @ (4, 3238) -> [17500 ps] WR @ (4, 576) -> [10000 ps] WR @ (0, 576) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) -> [17500 ps] WR @ (0, 576) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15305) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) -> [17500 ps] WR @ (0, 576) -> [10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13147) -> [10000 ps] ACT @ (4, 14226) -> [17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 568) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) -> [17500 ps] WR @ (0, 568) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9909) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) -> [17500 ps] WR @ (0, 568) -> [10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7751) -> [10000 ps] ACT @ (4, 8830) -> [17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 560) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) -> [17500 ps] WR @ (0, 560) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4513) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) -> [17500 ps] WR @ (0, 560) -> [10000 ps] WR @ (4, 560) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2355) -> [10000 ps] ACT @ (4, 3434) -> [17500 ps] WR @ (4, 560) -> [10000 ps] WR @ (0, 560) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) -> [17500 ps] WR @ (0, 560) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15501) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) -> [17500 ps] WR @ (0, 560) -> [10000 ps] WR @ (4, 552) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13343) -> [10000 ps] ACT @ (4, 14422) -> [17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 552) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11184) -> [10000 ps] ACT @ (0, 12264) -> [17500 ps] WR @ (0, 552) ->
[10000 ps] WR @ (4, 552) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10105) -> [17500 ps] WR @ (4, 552) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 7947) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9026) -> [17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 544) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5788) -> [10000 ps] ACT @ (0, 6868) -> [17500 ps] WR @ (0, 544) ->
[10000 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4709) -> [17500 ps] WR @ (4, 544) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 2551) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3630) -> [17500 ps] WR @ (4, 544) -> [10000 ps] WR @ (0, 544) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 392) -> [10000 ps] ACT @ (0, 1472) -> [17500 ps] WR @ (0, 544) ->
[10000 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15697) -> [17500 ps] WR @ (4, 536) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 13539) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14618) -> [17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 536) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11380) -> [10000 ps] ACT @ (0, 12460) -> [17500 ps] WR @ (0, 536) ->
[10000 ps] WR @ (4, 536) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10301) -> [17500 ps] WR @ (4, 536) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 8143) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9222) -> [17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 528) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5984) -> [10000 ps] ACT @ (0, 7064) -> [17500 ps] WR @ (0, 528) ->
[10000 ps] WR @ (4, 528) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4905) -> [17500 ps] WR @ (4, 528) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 2747) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3826) -> [17500 ps] WR @ (4, 528) -> [10000 ps] WR @ (0, 528) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 588) -> [10000 ps] ACT @ (0, 1668) -> [17500 ps] WR @ (0, 528) ->
[10000 ps] WR @ (4, 528) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15893) -> [17500 ps] WR @ (4, 520) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 13735) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14814) -> [17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11576) -> [10000 ps] ACT @ (0, 12656) -> [17500 ps] WR @ (0, 520) ->
[10000 ps] WR @ (4, 520) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9418) -> [10000 ps] ACT @ (4, 10497) ->
[17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8339) -> [17500 ps] WR @ (0, 520) ->
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7260) -> [17500 ps] WR @ (0, 512) ->
[10000 ps] WR @ (4, 512) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4022) -> [10000 ps] ACT @ (4, 5101) ->
[17500 ps] WR @ (4, 512) -> [10000 ps] WR @ (0, 512) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2943) -> [17500 ps] WR @ (0, 512) ->
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 784) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1864) -> [17500 ps] WR @ (0, 512) ->
[10000 ps] WR @ (4, 512) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15010) -> [10000 ps] ACT @ (4, 16089) ->
[17500 ps] WR @ (4, 504) -> [10000 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13931) -> [17500 ps] WR @ (0, 504) ->
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12852) -> [17500 ps] WR @ (0, 504) ->
[10000 ps] WR @ (4, 504) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9614) -> [10000 ps] ACT @ (4, 10693) ->
[17500 ps] WR @ (4, 504) -> [10000 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8535) -> [17500 ps] WR @ (0, 504) ->
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6376) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7456) -> [17500 ps] WR @ (0, 496) ->
[10000 ps] WR @ (4, 496) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4218) -> [10000 ps] ACT @ (4, 5297) ->
[17500 ps] WR @ (4, 496) -> [10000 ps] WR @ (0, 496) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3139) -> [17500 ps] WR @ (0, 496) ->
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2060) -> [17500 ps] WR @ (0, 496) ->
[10000 ps] WR @ (4, 496) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15206) -> [10000 ps] ACT @ (4, 16285) ->
[17500 ps] WR @ (4, 488) -> [10000 ps] WR @ (0, 488) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14127) -> [17500 ps] WR @ (0, 488) ->
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11968) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13048) -> [17500 ps] WR @ (0, 488) ->
[10000 ps] WR @ (4, 488) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9810) -> [10000 ps] ACT @ (4, 10889) ->
[17500 ps] WR @ (4, 488) -> [10000 ps] WR @ (0, 488) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7651) ->
[10000 ps] ACT @ (0, 8731) -> [17500 ps] WR @ (0, 488) -> [10000 ps] WR @ (4, 480) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6572) ->
[17500 ps] WR @ (4, 480) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4414) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5493) ->
[17500 ps] WR @ (4, 480) -> [10000 ps] WR @ (0, 480) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2255) ->
[10000 ps] ACT @ (0, 3335) -> [17500 ps] WR @ (0, 480) -> [10000 ps] WR @ (4, 480) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1176) ->
[17500 ps] WR @ (4, 480) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15402) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 97) ->
[17500 ps] WR @ (4, 480) -> [10000 ps] WR @ (0, 472) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13243) ->
[10000 ps] ACT @ (0, 14323) -> [17500 ps] WR @ (0, 472) -> [10000 ps] WR @ (4, 472) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12164) ->
[17500 ps] WR @ (4, 472) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10006) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11085) ->
[17500 ps] WR @ (4, 472) -> [10000 ps] WR @ (0, 472) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
[17500 ps] ACT @ (0, 8927) -> [10000 ps] ACT @ (4, 7847) -> [ 7500 ps] WR @ (0, 472) -> [10000 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 6768) -> [17500 ps] WR @ (4, 464) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4610) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 5689) -> [17500 ps] WR @ (4, 464) -> [10000 ps] WR @ (0, 464) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 2451) -> [10000 ps] ACT @ (0, 3531) -> [17500 ps] WR @ (0, 464) -> [10000 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 1372) -> [17500 ps] WR @ (4, 464) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15598) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 293) -> [17500 ps] WR @ (4, 464) -> [10000 ps] WR @ (0, 456) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 13439) -> [10000 ps] ACT @ (0, 14519) -> [17500 ps] WR @ (0, 456) -> [10000 ps] WR @ (4, 456) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 12360) -> [17500 ps] WR @ (4, 456) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10202) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 11281) -> [17500 ps] WR @ (4, 456) -> [10000 ps] WR @ (0, 456) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 8043) -> [10000 ps] ACT @ (0, 9123) -> [17500 ps] WR @ (0, 456) -> [10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5885) -> [10000 ps] ACT @ (4, 6964) -> [17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) -> [17500 ps] WR @ (0, 448) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2647) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3727) -> [17500 ps] WR @ (0, 448) -> [10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 489) -> [10000 ps] ACT @ (4, 1568) -> [17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15794) -> [17500 ps] WR @ (0, 440) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14715) -> [17500 ps] WR @ (0, 440) -> [10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11477) -> [10000 ps] ACT @ (4, 12556) -> [17500 ps] WR @ (4, 440) -> [10000 ps] WR @ (0, 440) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) -> [17500 ps] WR @ (0, 440) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8239) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9319) -> [17500 ps] WR @ (0, 440) -> [10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6081) -> [10000 ps] ACT @ (4, 7160) -> [17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5002) -> [17500 ps] WR @ (0, 432) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3923) -> [17500 ps] WR @ (0, 432) -> [10000 ps] WR @ (4, 432) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 685) -> [10000 ps] ACT @ (4, 1764) -> [17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) -> [17500 ps] WR @ (0, 424) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13831) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14911) -> [17500 ps] WR @ (0, 424) -> [10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11673) -> [10000 ps] ACT @ (4, 12752) -> [17500 ps] WR @ (4, 424) -> [10000 ps] WR @ (0, 424) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10594) -> [17500 ps] WR @ (0, 424) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9515) -> [17500 ps] WR @ (0, 424) -> [10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6277) -> [10000 ps] ACT @ (4, 7356) -> [17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4118) -> [10000 ps] ACT @ (0, 5198) -> [17500 ps] WR @ (0, 416) ->
[10000 ps] WR @ (4, 416) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3039) -> [17500 ps] WR @ (4, 416) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 881) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1960) -> [17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15106) -> [10000 ps] ACT @ (0, 16186) -> [17500 ps] WR @ (0, 408) ->
[10000 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14027) -> [17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 11869) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12948) -> [17500 ps] WR @ (4, 408) -> [10000 ps] WR @ (0, 408) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9710) -> [10000 ps] ACT @ (0, 10790) -> [17500 ps] WR @ (0, 408) ->
[10000 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8631) -> [17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 6473) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7552) -> [17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4314) -> [10000 ps] ACT @ (0, 5394) -> [17500 ps] WR @ (0, 400) ->
[10000 ps] WR @ (4, 400) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3235) -> [17500 ps] WR @ (4, 400) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 1077) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2156) -> [17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15302) -> [10000 ps] ACT @ (0, 16382) -> [17500 ps] WR @ (0, 392) ->
[10000 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14223) -> [17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 12065) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13144) -> [17500 ps] WR @ (4, 392) -> [10000 ps] WR @ (0, 392) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9906) -> [10000 ps] ACT @ (0, 10986) -> [17500 ps] WR @ (0, 392) ->
[10000 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8827) -> [17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 6669) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7748) -> [17500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4510) -> [10000 ps] ACT @ (0, 5590) -> [17500 ps] WR @ (0, 384) ->
[10000 ps] WR @ (4, 384) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2352) -> [10000 ps] ACT @ (4, 3431) ->
[17500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1273) -> [17500 ps] WR @ (0, 384) ->
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 194) -> [17500 ps] WR @ (0, 384) ->
[10000 ps] WR @ (4, 376) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13340) -> [10000 ps] ACT @ (4, 14419) ->
[17500 ps] WR @ (4, 376) -> [10000 ps] WR @ (0, 376) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12261) -> [17500 ps] WR @ (0, 376) ->
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10102) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11182) -> [17500 ps] WR @ (0, 376) ->
[10000 ps] WR @ (4, 376) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7944) -> [10000 ps] ACT @ (4, 9023) ->
[17500 ps] WR @ (4, 376) -> [10000 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6865) -> [17500 ps] WR @ (0, 368) ->
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5786) -> [17500 ps] WR @ (0, 368) ->
[10000 ps] WR @ (4, 368) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2548) -> [10000 ps] ACT @ (4, 3627) ->
[17500 ps] WR @ (4, 368) -> [10000 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1469) -> [17500 ps] WR @ (0, 368) ->
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15694) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 390) -> [17500 ps] WR @ (0, 368) ->
[10000 ps] WR @ (4, 360) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13536) -> [10000 ps] ACT @ (4, 14615) ->
[17500 ps] WR @ (4, 360) -> [10000 ps] WR @ (0, 360) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12457) -> [17500 ps] WR @ (0, 360) ->
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11378) -> [17500 ps] WR @ (0, 360) ->
[10000 ps] WR @ (4, 360) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8140) -> [10000 ps] ACT @ (4, 9219) ->
[17500 ps] WR @ (4, 360) -> [10000 ps] WR @ (0, 352) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7061) -> [17500 ps] WR @ (0, 352) ->
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4902) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5982) -> [17500 ps] WR @ (0, 352) ->
[10000 ps] WR @ (4, 352) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2744) -> [10000 ps] ACT @ (4, 3823) ->
[17500 ps] WR @ (4, 352) -> [10000 ps] WR @ (0, 352) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 585) ->
[10000 ps] ACT @ (0, 1665) -> [17500 ps] WR @ (0, 352) -> [10000 ps] WR @ (4, 352) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15890) ->
[17500 ps] WR @ (4, 344) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13732) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14811) ->
[17500 ps] WR @ (4, 344) -> [10000 ps] WR @ (0, 344) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11573) ->
[10000 ps] ACT @ (0, 12653) -> [17500 ps] WR @ (0, 344) -> [10000 ps] WR @ (4, 344) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10494) ->
[17500 ps] WR @ (4, 344) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8336) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9415) ->
[17500 ps] WR @ (4, 344) -> [10000 ps] WR @ (0, 344) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6177) ->
[10000 ps] ACT @ (0, 7257) -> [17500 ps] WR @ (0, 336) -> [10000 ps] WR @ (4, 336) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5098) ->
[17500 ps] WR @ (4, 336) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2940) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4019) ->
[17500 ps] WR @ (4, 336) -> [10000 ps] WR @ (0, 336) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 781) ->
[10000 ps] ACT @ (0, 1861) -> [17500 ps] WR @ (0, 336) -> [10000 ps] WR @ (4, 336) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16086) ->
[17500 ps] WR @ (4, 328) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13928) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15007) ->
[17500 ps] WR @ (4, 328) -> [10000 ps] WR @ (0, 328) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11769) ->
[10000 ps] ACT @ (0, 12849) -> [17500 ps] WR @ (0, 328) -> [10000 ps] WR @ (4, 328) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10690) ->
[17500 ps] WR @ (4, 328) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8532) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9611) ->
[17500 ps] WR @ (4, 328) -> [10000 ps] WR @ (0, 328) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6373) ->
[10000 ps] ACT @ (0, 7453) -> [17500 ps] WR @ (0, 320) -> [10000 ps] WR @ (4, 320) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5294) ->
[17500 ps] WR @ (4, 320) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3136) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4215) ->
[17500 ps] WR @ (4, 320) -> [10000 ps] WR @ (0, 320) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 977) ->
[10000 ps] ACT @ (0, 2057) -> [17500 ps] WR @ (0, 320) -> [10000 ps] WR @ (4, 320) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 15203) -> [10000 ps] ACT @ (4, 16282) -> [17500 ps] WR @ (4, 312) -> [10000 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 14124) -> [17500 ps] WR @ (0, 312) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11965) -> [22500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 13045) -> [17500 ps] WR @ (0, 312) -> [10000 ps] WR @ (4, 312) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 9807) -> [10000 ps] ACT @ (4, 10886) -> [17500 ps] WR @ (4, 312) -> [10000 ps] WR @ (0, 312) -> [35000 ps] NOP ->
[10000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> [17500 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) ->
[17500 ps] WR @ (0, 304) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 6569) ->
[17500 ps] WR @ (4, 304) -> [ 2500 ps] ACT @ (0, 4411) -> [42500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5490) -> [17500 ps] WR @ (4, 304) ->
[10000 ps] WR @ (0, 304) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) -> [17500 ps] WR @ (0, 304) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 1173) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [17500 ps] WR @ (0, 304) -> [10000 ps] WR @ (4, 304) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15399) -> [10000 ps] ACT @ (4, 94) -> [17500 ps] WR @ (4, 304) ->
[10000 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) -> [17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 12161) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13241) -> [17500 ps] WR @ (0, 296) -> [10000 ps] WR @ (4, 296) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10003) -> [10000 ps] ACT @ (4, 11082) -> [17500 ps] WR @ (4, 296) ->
[10000 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) -> [17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 6765) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7845) -> [17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4607) -> [10000 ps] ACT @ (4, 5686) -> [17500 ps] WR @ (4, 288) ->
[10000 ps] WR @ (0, 288) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) -> [17500 ps] WR @ (0, 288) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 1369) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2449) -> [17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15595) -> [10000 ps] ACT @ (4, 290) -> [17500 ps] WR @ (4, 288) ->
[10000 ps] WR @ (0, 280) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13436) -> [10000 ps] ACT @ (0, 14516) ->
[17500 ps] WR @ (0, 280) -> [10000 ps] WR @ (4, 280) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12357) -> [17500 ps] WR @ (4, 280) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10199) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11278) -> [17500 ps] WR @ (4, 280) ->
[10000 ps] WR @ (0, 280) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8040) -> [10000 ps] ACT @ (0, 9120) ->
[17500 ps] WR @ (0, 280) -> [10000 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6961) -> [17500 ps] WR @ (4, 272) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4803) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5882) -> [17500 ps] WR @ (4, 272) ->
[10000 ps] WR @ (0, 272) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2644) -> [10000 ps] ACT @ (0, 3724) ->
[17500 ps] WR @ (0, 272) -> [10000 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1565) -> [17500 ps] WR @ (4, 272) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15791) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 486) -> [17500 ps] WR @ (4, 272) ->
[10000 ps] WR @ (0, 264) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13632) -> [10000 ps] ACT @ (0, 14712) ->
[17500 ps] WR @ (0, 264) -> [10000 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12553) -> [17500 ps] WR @ (4, 264) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10395) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11474) -> [17500 ps] WR @ (4, 264) ->
[10000 ps] WR @ (0, 264) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8236) -> [10000 ps] ACT @ (0, 9316) ->
[17500 ps] WR @ (0, 264) -> [10000 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7157) -> [17500 ps] WR @ (4, 256) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4999) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6078) -> [17500 ps] WR @ (4, 256) ->
[10000 ps] WR @ (0, 256) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2840) -> [10000 ps] ACT @ (0, 3920) ->
[17500 ps] WR @ (0, 256) -> [10000 ps] WR @ (4, 256) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1761) -> [17500 ps] WR @ (4, 256) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15987) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 682) -> [17500 ps] WR @ (4, 256) ->
[10000 ps] WR @ (0, 248) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13828) -> [10000 ps] ACT @ (0, 14908) ->
[17500 ps] WR @ (0, 248) -> [10000 ps] WR @ (4, 248) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) ->
[10000 ps] ACT @ (4, 12749) -> [17500 ps] WR @ (4, 248) -> [10000 ps] WR @ (0, 248) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) ->
[17500 ps] WR @ (0, 248) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8432) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9512) ->
[17500 ps] WR @ (0, 248) -> [10000 ps] WR @ (4, 248) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6274) ->
[10000 ps] ACT @ (4, 7353) -> [17500 ps] WR @ (4, 240) -> [10000 ps] WR @ (0, 240) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) ->
[17500 ps] WR @ (0, 240) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) ->
[17500 ps] WR @ (0, 240) -> [10000 ps] WR @ (4, 240) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 878) ->
[10000 ps] ACT @ (4, 1957) -> [17500 ps] WR @ (4, 240) -> [10000 ps] WR @ (0, 240) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) ->
[17500 ps] WR @ (0, 232) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) ->
[17500 ps] WR @ (0, 232) -> [10000 ps] WR @ (4, 232) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11866) ->
[10000 ps] ACT @ (4, 12945) -> [17500 ps] WR @ (4, 232) -> [10000 ps] WR @ (0, 232) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) ->
[17500 ps] WR @ (0, 232) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) ->
[17500 ps] WR @ (0, 232) -> [10000 ps] WR @ (4, 232) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6470) ->
[10000 ps] ACT @ (4, 7549) -> [17500 ps] WR @ (4, 224) -> [10000 ps] WR @ (0, 224) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) ->
[17500 ps] WR @ (0, 224) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) ->
[17500 ps] WR @ (0, 224) -> [10000 ps] WR @ (4, 224) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1074) ->
[10000 ps] ACT @ (4, 2153) -> [17500 ps] WR @ (4, 224) -> [10000 ps] WR @ (0, 224) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) ->
[17500 ps] WR @ (0, 216) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) ->
[17500 ps] WR @ (0, 216) -> [10000 ps] WR @ (4, 216) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12062) ->
[10000 ps] ACT @ (4, 13141) -> [17500 ps] WR @ (4, 216) -> [10000 ps] WR @ (0, 216) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 9903) -> [10000 ps] ACT @ (0, 10983) -> [17500 ps] WR @ (0, 216) -> [10000 ps] WR @ (4, 216) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 8824) -> [17500 ps] WR @ (4, 216) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6666) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 7745) -> [17500 ps] WR @ (4, 208) -> [10000 ps] WR @ (0, 208) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 4507) -> [10000 ps] ACT @ (0, 5587) -> [17500 ps] WR @ (0, 208) -> [10000 ps] WR @ (4, 208) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 3428) -> [17500 ps] WR @ (4, 208) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1270) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 2349) -> [17500 ps] WR @ (4, 208) -> [10000 ps] WR @ (0, 208) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 15495) -> [10000 ps] ACT @ (0, 191) -> [17500 ps] WR @ (0, 208) -> [10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 14416) -> [17500 ps] WR @ (4, 200) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12258) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 13337) -> [17500 ps] WR @ (4, 200) -> [10000 ps] WR @ (0, 200) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 10099) -> [10000 ps] ACT @ (0, 11179) -> [17500 ps] WR @ (0, 200) -> [10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 9020) -> [17500 ps] WR @ (4, 200) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6862) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 7941) -> [17500 ps] WR @ (4, 192) -> [10000 ps] WR @ (0, 192) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 4703) -> [10000 ps] ACT @ (0, 5783) -> [17500 ps] WR @ (0, 192) -> [10000 ps] WR @ (4, 192) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 3624) -> [17500 ps] WR @ (4, 192) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1466) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 2545) -> [17500 ps] WR @ (4, 192) -> [10000 ps] WR @ (0, 192) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 15691) -> [10000 ps] ACT @ (0, 387) -> [17500 ps] WR @ (0, 192) -> [10000 ps] WR @ (4, 184) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 14612) -> [17500 ps] WR @ (4, 184) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12454) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 13533) -> [17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 184) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 10295) -> [10000 ps] ACT @ (0, 11375) -> [17500 ps] WR @ (0, 184) -> [10000 ps] WR @ (4, 184) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8137) -> [10000 ps] ACT @ (4, 9216) -> [17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 176) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7058) -> [17500 ps] WR @ (0, 176) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4899) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) -> [17500 ps] WR @ (0, 176) -> [10000 ps] WR @ (4, 176) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2741) -> [10000 ps] ACT @ (4, 3820) -> [17500 ps] WR @ (4, 176) -> [10000 ps] WR @ (0, 176) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1662) -> [17500 ps] WR @ (0, 176) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15887) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 583) -> [17500 ps] WR @ (0, 176) -> [10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13729) -> [10000 ps] ACT @ (4, 14808) -> [17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) -> [17500 ps] WR @ (0, 168) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10491) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) -> [17500 ps] WR @ (0, 168) -> [10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8333) -> [10000 ps] ACT @ (4, 9412) -> [17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7254) -> [17500 ps] WR @ (0, 160) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5095) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6175) -> [17500 ps] WR @ (0, 160) -> [10000 ps] WR @ (4, 160) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2937) -> [10000 ps] ACT @ (4, 4016) -> [17500 ps] WR @ (4, 160) -> [10000 ps] WR @ (0, 160) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) -> [17500 ps] WR @ (0, 160) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16083) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) -> [17500 ps] WR @ (0, 160) -> [10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13925) -> [10000 ps] ACT @ (4, 15004) -> [17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12846) -> [17500 ps] WR @ (0, 152) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10687) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11767) -> [17500 ps] WR @ (0, 152) -> [10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8529) -> [10000 ps] ACT @ (4, 9608) -> [17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6370) -> [10000 ps] ACT @ (0, 7450) -> [17500 ps] WR @ (0, 144) ->
[10000 ps] WR @ (4, 144) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 5291) ->
[17500 ps] WR @ (4, 144) -> [ 2500 ps] ACT @ (0, 3133) -> [42500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4212) -> [17500 ps] WR @ (4, 144) ->
[10000 ps] WR @ (0, 144) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 974) -> [10000 ps] ACT @ (0, 2054) ->
[17500 ps] WR @ (0, 144) -> [10000 ps] WR @ (4, 144) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16279) -> [17500 ps] WR @ (4, 136) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14121) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15200) -> [17500 ps] WR @ (4, 136) ->
[10000 ps] WR @ (0, 136) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11962) -> [10000 ps] ACT @ (0, 13042) ->
[17500 ps] WR @ (0, 136) -> [10000 ps] WR @ (4, 136) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10883) -> [17500 ps] WR @ (4, 136) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9804) -> [17500 ps] WR @ (4, 136) ->
[10000 ps] WR @ (0, 136) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6566) -> [10000 ps] ACT @ (0, 7646) ->
[17500 ps] WR @ (0, 128) -> [10000 ps] WR @ (4, 128) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5487) -> [17500 ps] WR @ (4, 128) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4408) -> [17500 ps] WR @ (4, 128) ->
[10000 ps] WR @ (0, 128) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1170) -> [10000 ps] ACT @ (0, 2250) ->
[17500 ps] WR @ (0, 128) -> [10000 ps] WR @ (4, 128) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 91) -> [17500 ps] WR @ (4, 128) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15396) -> [17500 ps] WR @ (4, 120) ->
[10000 ps] WR @ (0, 120) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12158) -> [10000 ps] ACT @ (0, 13238) ->
[17500 ps] WR @ (0, 120) -> [10000 ps] WR @ (4, 120) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11079) -> [17500 ps] WR @ (4, 120) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10000) -> [17500 ps] WR @ (4, 120) ->
[10000 ps] WR @ (0, 120) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6762) -> [10000 ps] ACT @ (0, 7842) ->
[17500 ps] WR @ (0, 112) -> [10000 ps] WR @ (4, 112) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) ->
[10000 ps] ACT @ (4, 5683) -> [17500 ps] WR @ (4, 112) -> [10000 ps] WR @ (0, 112) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) ->
[17500 ps] WR @ (0, 112) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2446) ->
[17500 ps] WR @ (0, 112) -> [10000 ps] WR @ (4, 112) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15592) ->
[10000 ps] ACT @ (4, 287) -> [17500 ps] WR @ (4, 112) -> [10000 ps] WR @ (0, 104) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) ->
[17500 ps] WR @ (0, 104) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12354) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) ->
[17500 ps] WR @ (0, 104) -> [10000 ps] WR @ (4, 104) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10196) ->
[10000 ps] ACT @ (4, 11275) -> [17500 ps] WR @ (4, 104) -> [10000 ps] WR @ (0, 104) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) ->
[17500 ps] WR @ (0, 104) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) ->
[17500 ps] WR @ (0, 96) -> [10000 ps] WR @ (4, 96) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4800) ->
[10000 ps] ACT @ (4, 5879) -> [17500 ps] WR @ (4, 96) -> [10000 ps] WR @ (0, 96) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) ->
[17500 ps] WR @ (0, 96) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1562) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) ->
[17500 ps] WR @ (0, 96) -> [10000 ps] WR @ (4, 96) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15788) ->
[10000 ps] ACT @ (4, 483) -> [17500 ps] WR @ (4, 96) -> [10000 ps] WR @ (0, 88) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) ->
[17500 ps] WR @ (0, 88) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) ->
[17500 ps] WR @ (0, 88) -> [10000 ps] WR @ (4, 88) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10392) ->
[10000 ps] ACT @ (4, 11471) -> [17500 ps] WR @ (4, 88) -> [10000 ps] WR @ (0, 88) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) ->
[17500 ps] WR @ (0, 88) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7154) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) ->
[17500 ps] WR @ (0, 88) -> [10000 ps] WR @ (4, 80) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4996) ->
[10000 ps] ACT @ (4, 6075) -> [17500 ps] WR @ (4, 80) -> [10000 ps] WR @ (0, 80) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 2837) -> [10000 ps] ACT @ (0, 3917) -> [17500 ps] WR @ (0, 80) -> [10000 ps] WR @ (4, 80) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 1758) -> [17500 ps] WR @ (4, 80) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15984) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 679) -> [17500 ps] WR @ (4, 80) -> [10000 ps] WR @ (0, 72) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 13825) -> [10000 ps] ACT @ (0, 14905) -> [17500 ps] WR @ (0, 72) -> [10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 12746) -> [17500 ps] WR @ (4, 72) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10588) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 11667) -> [17500 ps] WR @ (4, 72) -> [10000 ps] WR @ (0, 72) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 8429) -> [10000 ps] ACT @ (0, 9509) -> [17500 ps] WR @ (0, 72) -> [10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 7350) -> [17500 ps] WR @ (4, 64) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5192) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 6271) -> [17500 ps] WR @ (4, 64) -> [10000 ps] WR @ (0, 64) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 3033) -> [10000 ps] ACT @ (0, 4113) -> [17500 ps] WR @ (0, 64) -> [10000 ps] WR @ (4, 64) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 1954) -> [17500 ps] WR @ (4, 64) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16180) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 875) -> [17500 ps] WR @ (4, 64) -> [10000 ps] WR @ (0, 56) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 14021) -> [10000 ps] ACT @ (0, 15101) -> [17500 ps] WR @ (0, 56) -> [10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 12942) -> [17500 ps] WR @ (4, 56) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10784) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 11863) -> [17500 ps] WR @ (4, 56) -> [10000 ps] WR @ (0, 56) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 8625) -> [10000 ps] ACT @ (0, 9705) -> [17500 ps] WR @ (0, 56) -> [10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 7546) -> [17500 ps] WR @ (4, 48) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5388) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 6467) -> [17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 3229) -> [10000 ps] ACT @ (0, 4309) -> [17500 ps] WR @ (0, 48) -> [10000 ps] WR @ (4, 48) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1071) -> [10000 ps] ACT @ (4, 2150) -> [17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) -> [17500 ps] WR @ (0, 40) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) -> [17500 ps] WR @ (0, 40) -> [10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12059) -> [10000 ps] ACT @ (4, 13138) -> [17500 ps] WR @ (4, 40) -> [10000 ps] WR @ (0, 40) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10980) -> [17500 ps] WR @ (0, 40) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9901) -> [17500 ps] WR @ (0, 40) -> [10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6663) -> [10000 ps] ACT @ (4, 7742) -> [17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) -> [17500 ps] WR @ (0, 32) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) -> [17500 ps] WR @ (0, 32) -> [10000 ps] WR @ (4, 32) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1267) -> [10000 ps] ACT @ (4, 2346) -> [17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 188) -> [17500 ps] WR @ (0, 32) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15493) -> [17500 ps] WR @ (0, 24) -> [10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12255) -> [10000 ps] ACT @ (4, 13334) -> [17500 ps] WR @ (4, 24) -> [10000 ps] WR @ (0, 24) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) -> [17500 ps] WR @ (0, 24) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) -> [17500 ps] WR @ (0, 24) -> [10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6859) -> [10000 ps] ACT @ (4, 7938) -> [17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5780) -> [17500 ps] WR @ (0, 16) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4701) -> [17500 ps] WR @ (0, 16) -> [10000 ps] WR @ (4, 16) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1463) -> [10000 ps] ACT @ (4, 2542) -> [17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15688) -> [10000 ps] ACT @ (0, 384) -> [17500 ps] WR @ (0, 16) ->
[10000 ps] WR @ (4, 8) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) -> [17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 12451) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13530) -> [17500 ps] WR @ (4, 8) -> [10000 ps] WR @ (0, 8) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10292) -> [10000 ps] ACT @ (0, 11372) -> [17500 ps] WR @ (0, 8) ->
[10000 ps] WR @ (4, 8) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9213) -> [17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 7055) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) -> [17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4896) -> [10000 ps] ACT @ (0, 5976) -> [17500 ps] WR @ (0, 0) ->
[10000 ps] WR @ (4, 0) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) -> [17500 ps] WR @ (4, 0) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 1659) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2738) -> [17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 580) -> [17500 ps] WR @ (0, 0) -> [ 2500 ps] ACT @ (7, 15884) -> [17500 ps] WR @ (7, 1016) ->
[25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13727) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14805) -> [17500 ps] WR @ (7, 1016) ->
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13726) -> [17500 ps] WR @ (7, 1016) ->
[ 2500 ps] ACT @ (3, 12647) -> [ 2500 ps] PRE @ (4) -> [15000 ps] WR @ (3, 1016) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10489) ->
[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> [17500 ps] WR @ (3, 1016) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (7, 10488) -> [10000 ps] ACT @ (0, 9410) -> [ 7500 ps] WR @ (7, 1016) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (7) ->
[ 7500 ps] ACT @ (0, 8331) -> [10000 ps] ACT @ (7, 9409) -> [17500 ps] WR @ (7, 1016) -> [ 2500 ps] ACT @ (4, 7251) -> [42500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 8330) -> [17500 ps] WR @ (7, 1016) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7251) ->
[10000 ps] ACT @ (4, 6172) -> [ 7500 ps] WR @ (3, 1008) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6172) -> [17500 ps] WR @ (3, 1008) ->
[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 5093) -> [10000 ps] ACT @ (7, 5092) ->
[17500 ps] WR @ (7, 1008) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2935) -> [12500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4013) ->
[17500 ps] WR @ (7, 1008) -> [ 2500 ps] ACT @ (4, 1855) -> [42500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2934) -> [17500 ps] WR @ (7, 1008) ->
[ 2500 ps] ACT @ (3, 1855) -> [ 2500 ps] PRE @ (4) -> [15000 ps] WR @ (3, 1008) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16081) ->
[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 776) -> [17500 ps] WR @ (3, 1008) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (7, 16080) -> [10000 ps] ACT @ (0, 15002) -> [ 7500 ps] WR @ (7, 1000) -> [ 2500 ps] ACT @ (4, 13922) -> [42500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 15001) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13922) ->
[10000 ps] ACT @ (4, 12843) -> [ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 11764) ->
[10000 ps] ACT @ (3, 12843) -> [17500 ps] WR @ (3, 1000) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10685) -> [22500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 11764) -> [17500 ps] WR @ (3, 1000) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10684) ->
[10000 ps] ACT @ (0, 9606) -> [ 7500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8526) -> [22500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 9605) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 8526) ->
[10000 ps] ACT @ (4, 7447) -> [ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 6368) ->
[10000 ps] ACT @ (3, 7447) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5289) -> [22500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 6368) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5288) ->
[10000 ps] ACT @ (0, 4210) -> [ 7500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3130) -> [22500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 4209) -> [17500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 3130) ->
[10000 ps] ACT @ (4, 2051) -> [ 7500 ps] WR @ (3, 992) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 972) ->
[10000 ps] ACT @ (3, 2051) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16277) -> [22500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 972) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 16276) ->
[10000 ps] ACT @ (0, 15198) -> [ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14118) -> [22500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 15197) -> [17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 14118) ->
[10000 ps] ACT @ (4, 13039) -> [ 7500 ps] WR @ (3, 984) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 11960) ->
[10000 ps] ACT @ (3, 13039) -> [17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10881) -> [22500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 11960) -> [17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10880) ->
[10000 ps] ACT @ (0, 9802) -> [ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8722) -> [22500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 9801) -> [17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8722) -> [17500 ps] WR @ (3, 984) ->
[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> [17500 ps] WR @ (3, 976) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5484) ->
[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> [17500 ps] WR @ (3, 976) -> [10000 ps] WR @ (7, 976) -> [35000 ps] PRE @ (3) ->
[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3326) -> [10000 ps] ACT @ (7, 4405) -> [17500 ps] WR @ (7, 976) -> [10000 ps] WR @ (3, 976) ->
[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> [17500 ps] WR @ (3, 976) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 88) ->
[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> [17500 ps] WR @ (3, 976) -> [10000 ps] WR @ (7, 976) -> [35000 ps] PRE @ (3) ->
[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14314) -> [10000 ps] ACT @ (7, 15393) -> [17500 ps] WR @ (7, 968) -> [10000 ps] WR @ (3, 968) ->
[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12155) -> [10000 ps] ACT @ (3, 13235) -> [17500 ps] WR @ (3, 968) ->
[10000 ps] WR @ (7, 968) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11076) -> [17500 ps] WR @ (7, 968) -> [ 5000 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 8918) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9997) -> [17500 ps] WR @ (7, 968) -> [10000 ps] WR @ (3, 968) ->
[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6759) -> [10000 ps] ACT @ (3, 7839) -> [17500 ps] WR @ (3, 960) ->
[10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5680) -> [17500 ps] WR @ (7, 960) -> [ 5000 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 3522) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4601) -> [17500 ps] WR @ (7, 960) -> [10000 ps] WR @ (3, 960) ->
[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1363) -> [10000 ps] ACT @ (3, 2443) -> [17500 ps] WR @ (3, 960) ->
[10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 284) -> [17500 ps] WR @ (7, 960) -> [ 5000 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 14510) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15589) -> [17500 ps] WR @ (7, 952) -> [10000 ps] WR @ (3, 952) ->
[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12351) -> [10000 ps] ACT @ (3, 13431) -> [17500 ps] WR @ (3, 952) ->
[10000 ps] WR @ (7, 952) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11272) -> [17500 ps] WR @ (7, 952) -> [ 5000 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 9114) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10193) -> [17500 ps] WR @ (7, 952) -> [10000 ps] WR @ (3, 952) ->
[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6955) -> [10000 ps] ACT @ (3, 8035) -> [17500 ps] WR @ (3, 944) ->
[10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5876) -> [17500 ps] WR @ (7, 944) -> [ 5000 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 3718) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4797) -> [17500 ps] WR @ (7, 944) -> [10000 ps] WR @ (3, 944) ->
[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1559) -> [10000 ps] ACT @ (3, 2639) -> [17500 ps] WR @ (3, 944) ->
[10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 480) -> [17500 ps] WR @ (7, 944) -> [ 5000 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 14706) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15785) -> [17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) ->
[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12547) -> [10000 ps] ACT @ (3, 13627) -> [17500 ps] WR @ (3, 936) ->
[10000 ps] WR @ (7, 936) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10389) -> [10000 ps] ACT @ (7, 11468) ->
[17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9310) -> [17500 ps] WR @ (3, 936) ->
[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8231) -> [17500 ps] WR @ (3, 936) ->
[10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4993) -> [10000 ps] ACT @ (7, 6072) ->
[17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 928) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3914) -> [17500 ps] WR @ (3, 928) ->
[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2835) -> [17500 ps] WR @ (3, 928) ->
[10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15981) -> [10000 ps] ACT @ (7, 676) ->
[17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14902) -> [17500 ps] WR @ (3, 920) ->
[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13823) -> [17500 ps] WR @ (3, 920) ->
[10000 ps] WR @ (7, 920) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10585) -> [10000 ps] ACT @ (7, 11664) ->
[17500 ps] WR @ (7, 920) -> [10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9506) -> [17500 ps] WR @ (3, 920) ->
[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8427) -> [17500 ps] WR @ (3, 920) ->
[10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 5189) -> [10000 ps] ACT @ (7, 6268) ->
[17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 912) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4110) -> [17500 ps] WR @ (3, 912) ->
[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3031) -> [17500 ps] WR @ (3, 912) ->
[10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 16177) -> [10000 ps] ACT @ (7, 872) ->
[17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 904) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15098) -> [17500 ps] WR @ (3, 904) ->
[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14019) -> [17500 ps] WR @ (3, 904) ->
[10000 ps] WR @ (7, 904) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10781) -> [10000 ps] ACT @ (7, 11860) ->
[17500 ps] WR @ (7, 904) -> [10000 ps] WR @ (3, 904) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8622) ->
[10000 ps] ACT @ (3, 9702) -> [17500 ps] WR @ (3, 904) -> [10000 ps] WR @ (7, 904) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7543) ->
[17500 ps] WR @ (7, 896) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6464) ->
[17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 896) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 3226) ->
[10000 ps] ACT @ (3, 4306) -> [17500 ps] WR @ (3, 896) -> [10000 ps] WR @ (7, 896) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2147) ->
[17500 ps] WR @ (7, 896) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16373) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1068) ->
[17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 14214) ->
[10000 ps] ACT @ (3, 15294) -> [17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13135) ->
[17500 ps] WR @ (7, 888) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12056) ->
[17500 ps] WR @ (7, 888) -> [10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8818) ->
[10000 ps] ACT @ (3, 9898) -> [17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7739) ->
[17500 ps] WR @ (7, 880) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5581) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6660) ->
[17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 3422) ->
[10000 ps] ACT @ (3, 4502) -> [17500 ps] WR @ (3, 880) -> [10000 ps] WR @ (7, 880) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2343) ->
[17500 ps] WR @ (7, 880) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1264) ->
[17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 14410) ->
[10000 ps] ACT @ (3, 15490) -> [17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13331) ->
[17500 ps] WR @ (7, 872) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11173) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12252) ->
[17500 ps] WR @ (7, 872) -> [10000 ps] WR @ (3, 872) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 9014) ->
[10000 ps] ACT @ (3, 10094) -> [17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
[ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) -> [17500 ps] WR @ (7, 864) -> [10000 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 5777) -> [17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3618) -> [22500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 4698) -> [17500 ps] WR @ (3, 864) -> [10000 ps] WR @ (7, 864) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
[ 7500 ps] ACT @ (3, 1460) -> [10000 ps] ACT @ (7, 2539) -> [17500 ps] WR @ (7, 864) -> [10000 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 381) -> [17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14606) -> [22500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 15686) -> [17500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
[ 7500 ps] ACT @ (3, 12448) -> [10000 ps] ACT @ (7, 13527) -> [12500 ps] NOP -> [ 5000 ps] WR @ (7, 856) -> [10000 ps] WR @ (3, 856) ->
[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11369) -> [17500 ps] WR @ (3, 856) -> [65000 ps] PRE @ (0) -> [30000 ps] REF ->
[360000 ps] NOP -> [17500 ps] ACT @ (3, 10290) -> [10000 ps] ACT @ (7, 9210) -> [ 7500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) ->
[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7052) -> [10000 ps] ACT @ (7, 8131) -> [17500 ps] WR @ (7, 848) ->
[10000 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5973) -> [17500 ps] WR @ (3, 848) -> [ 5000 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 3814) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4894) -> [17500 ps] WR @ (3, 848) -> [10000 ps] WR @ (7, 848) ->
[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 1656) -> [10000 ps] ACT @ (7, 2735) -> [17500 ps] WR @ (7, 848) ->
[10000 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 577) -> [17500 ps] WR @ (3, 848) -> [ 5000 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 14802) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15882) -> [17500 ps] WR @ (3, 840) -> [10000 ps] WR @ (7, 840) ->
[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 12644) -> [10000 ps] ACT @ (7, 13723) -> [17500 ps] WR @ (7, 840) ->
[10000 ps] WR @ (3, 840) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11565) -> [17500 ps] WR @ (3, 840) -> [ 5000 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 9406) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10486) -> [17500 ps] WR @ (3, 840) -> [10000 ps] WR @ (7, 840) ->
[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7248) -> [10000 ps] ACT @ (7, 8327) -> [17500 ps] WR @ (7, 840) ->
[10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5089) -> [10000 ps] ACT @ (3, 6169) ->
[17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 832) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) -> [17500 ps] WR @ (7, 832) ->
[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1852) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) -> [17500 ps] WR @ (7, 832) ->
[10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 16077) -> [10000 ps] ACT @ (3, 773) ->
[17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) -> [17500 ps] WR @ (7, 824) ->
[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12840) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) -> [17500 ps] WR @ (7, 824) ->
[10000 ps] WR @ (3, 824) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10681) -> [10000 ps] ACT @ (3, 11761) ->
[17500 ps] WR @ (3, 824) -> [10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) -> [17500 ps] WR @ (7, 824) ->
[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7444) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) -> [17500 ps] WR @ (7, 824) ->
[10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5285) -> [10000 ps] ACT @ (3, 6365) ->
[17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 816) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) -> [17500 ps] WR @ (7, 816) ->
[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2048) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) -> [17500 ps] WR @ (7, 816) ->
[10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 16273) -> [10000 ps] ACT @ (3, 969) ->
[17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) -> [17500 ps] WR @ (7, 808) ->
[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13036) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) -> [17500 ps] WR @ (7, 808) ->
[10000 ps] WR @ (3, 808) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10877) -> [10000 ps] ACT @ (3, 11957) ->
[17500 ps] WR @ (3, 808) -> [10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) -> [17500 ps] WR @ (7, 808) ->
[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7640) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) -> [17500 ps] WR @ (7, 808) ->
[10000 ps] WR @ (3, 800) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5481) -> [10000 ps] ACT @ (3, 6561) ->
[17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3323) ->
[10000 ps] ACT @ (7, 4402) -> [17500 ps] WR @ (7, 800) -> [10000 ps] WR @ (3, 800) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2244) ->
[17500 ps] WR @ (3, 800) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 85) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1165) ->
[17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14311) ->
[10000 ps] ACT @ (7, 15390) -> [17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13232) ->
[17500 ps] WR @ (3, 792) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11073) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12153) ->
[17500 ps] WR @ (3, 792) -> [10000 ps] WR @ (7, 792) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 8915) ->
[10000 ps] ACT @ (7, 9994) -> [17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7836) ->
[17500 ps] WR @ (3, 784) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5677) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6757) ->
[17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3519) ->
[10000 ps] ACT @ (7, 4598) -> [17500 ps] WR @ (7, 784) -> [10000 ps] WR @ (3, 784) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2440) ->
[17500 ps] WR @ (3, 784) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 281) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) ->
[17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14507) ->
[10000 ps] ACT @ (7, 15586) -> [17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) ->
[17500 ps] WR @ (3, 776) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11269) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12349) ->
[17500 ps] WR @ (3, 776) -> [10000 ps] WR @ (7, 776) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 9111) ->
[10000 ps] ACT @ (7, 10190) -> [17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8032) ->
[17500 ps] WR @ (3, 768) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6953) ->
[17500 ps] WR @ (3, 768) -> [ 2500 ps] ACT @ (4, 2852) -> [ 7500 ps] WR @ (7, 768) -> [ 2500 ps] ACT @ (0, 1773) -> [35000 ps] RD @ (4, 960) ->
[10000 ps] RD @ (0, 960) -> [ 7500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15998) -> [10000 ps] ACT @ (0, 694) ->
[15000 ps] RD @ (0, 960) -> [10000 ps] RD @ (4, 952) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14919) -> [15000 ps] RD @ (4, 952) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12761) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13840) -> [15000 ps] RD @ (4, 952) ->
[10000 ps] RD @ (0, 952) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11682) -> [10000 ps] ACT @ (4, 10602) ->
[ 5000 ps] RD @ (0, 952) -> [10000 ps] RD @ (4, 952) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9523) -> [15000 ps] RD @ (4, 952) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7365) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8444) -> [15000 ps] RD @ (4, 952) ->
[10000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6286) -> [10000 ps] ACT @ (4, 5206) ->
[ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 944) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4127) -> [15000 ps] RD @ (4, 944) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3048) -> [15000 ps] RD @ (4, 944) ->
[10000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 890) -> [10000 ps] ACT @ (4, 16194) ->
[ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15115) -> [15000 ps] RD @ (4, 936) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12957) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14036) -> [15000 ps] RD @ (4, 936) ->
[10000 ps] RD @ (0, 936) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11878) -> [10000 ps] ACT @ (4, 10798) ->
[ 5000 ps] RD @ (0, 936) -> [10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9719) -> [15000 ps] RD @ (4, 936) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8640) -> [15000 ps] RD @ (4, 936) ->
[10000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6482) -> [10000 ps] ACT @ (4, 5402) ->
[ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4323) -> [15000 ps] RD @ (4, 928) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2165) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3244) -> [15000 ps] RD @ (4, 928) ->
[10000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1086) -> [10000 ps] ACT @ (4, 6) ->
[ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14232) ->
[10000 ps] ACT @ (4, 15311) -> [15000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) ->
[15000 ps] RD @ (0, 920) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) ->
[15000 ps] RD @ (0, 920) -> [10000 ps] RD @ (4, 920) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9915) ->
[10000 ps] ACT @ (0, 8836) -> [ 5000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) ->
[15000 ps] RD @ (0, 912) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6678) ->
[15000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4519) ->
[10000 ps] ACT @ (0, 3440) -> [ 5000 ps] RD @ (4, 912) -> [10000 ps] RD @ (0, 912) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) ->
[15000 ps] RD @ (0, 912) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) ->
[15000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15507) ->
[10000 ps] ACT @ (0, 14428) -> [ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) ->
[15000 ps] RD @ (0, 904) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12270) ->
[15000 ps] RD @ (0, 904) -> [10000 ps] RD @ (4, 904) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10111) ->
[10000 ps] ACT @ (0, 9032) -> [ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) ->
[15000 ps] RD @ (0, 896) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) ->
[15000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4715) ->
[10000 ps] ACT @ (0, 3636) -> [ 5000 ps] RD @ (4, 896) -> [10000 ps] RD @ (0, 896) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) ->
[15000 ps] RD @ (0, 896) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1478) ->
[15000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15703) ->
[10000 ps] ACT @ (0, 14624) -> [ 5000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 12465) -> [10000 ps] ACT @ (0, 13545) -> [15000 ps] RD @ (0, 888) -> [10000 ps] RD @ (4, 888) -> [17500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 11386) -> [15000 ps] RD @ (4, 888) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9228) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 10307) -> [15000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 8149) -> [10000 ps] ACT @ (4, 7069) -> [ 5000 ps] RD @ (0, 880) -> [10000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 5990) -> [15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3832) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 4911) -> [15000 ps] RD @ (4, 880) -> [10000 ps] RD @ (0, 880) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 2753) -> [10000 ps] ACT @ (4, 1673) -> [ 5000 ps] RD @ (0, 880) -> [10000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 594) -> [15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14820) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 15899) -> [15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 13741) -> [10000 ps] ACT @ (4, 12661) -> [ 5000 ps] RD @ (0, 872) -> [10000 ps] RD @ (4, 872) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 11582) -> [15000 ps] RD @ (4, 872) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9424) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 10503) -> [15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 8345) -> [10000 ps] ACT @ (4, 7265) -> [ 5000 ps] RD @ (0, 872) -> [10000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 6186) -> [15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4028) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 5107) -> [15000 ps] RD @ (4, 864) -> [10000 ps] RD @ (0, 864) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 2949) -> [10000 ps] ACT @ (4, 1869) -> [ 5000 ps] RD @ (0, 864) -> [10000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 790) -> [15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15016) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 16095) -> [15000 ps] RD @ (4, 856) -> [10000 ps] RD @ (0, 856) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 13937) -> [10000 ps] ACT @ (4, 12857) -> [ 5000 ps] RD @ (0, 856) -> [10000 ps] RD @ (4, 856) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) -> [ 2500 ps] NOP -> [12500 ps] RD @ (4, 856) ->
[10000 ps] RD @ (0, 856) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 9620) ->
[15000 ps] RD @ (0, 856) -> [ 5000 ps] ACT @ (4, 7461) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) -> [15000 ps] RD @ (0, 856) ->
[10000 ps] RD @ (4, 848) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6382) -> [10000 ps] ACT @ (0, 5303) ->
[ 5000 ps] RD @ (4, 848) -> [10000 ps] RD @ (0, 848) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4224) -> [15000 ps] RD @ (0, 848) ->
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2065) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) -> [15000 ps] RD @ (0, 848) ->
[10000 ps] RD @ (4, 848) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 986) -> [10000 ps] ACT @ (0, 16291) ->
[ 5000 ps] RD @ (4, 848) -> [10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) -> [15000 ps] RD @ (0, 840) ->
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13053) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) -> [15000 ps] RD @ (0, 840) ->
[10000 ps] RD @ (4, 840) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11974) -> [10000 ps] ACT @ (0, 10895) ->
[ 5000 ps] RD @ (4, 840) -> [10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) -> [15000 ps] RD @ (0, 840) ->
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7657) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) -> [15000 ps] RD @ (0, 840) ->
[10000 ps] RD @ (4, 832) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6578) -> [10000 ps] ACT @ (0, 5499) ->
[ 5000 ps] RD @ (4, 832) -> [10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) -> [15000 ps] RD @ (0, 832) ->
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2261) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) -> [15000 ps] RD @ (0, 832) ->
[10000 ps] RD @ (4, 832) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1182) -> [10000 ps] ACT @ (0, 103) ->
[ 5000 ps] RD @ (4, 832) -> [10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) -> [15000 ps] RD @ (0, 824) ->
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13249) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) -> [15000 ps] RD @ (0, 824) ->
[10000 ps] RD @ (4, 824) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12170) -> [10000 ps] ACT @ (0, 11091) ->
[ 5000 ps] RD @ (4, 824) -> [10000 ps] RD @ (0, 824) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8932) ->
[10000 ps] ACT @ (0, 10012) -> [15000 ps] RD @ (0, 824) -> [10000 ps] RD @ (4, 824) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) ->
[15000 ps] RD @ (4, 816) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5695) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6774) ->
[15000 ps] RD @ (4, 816) -> [10000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4616) ->
[10000 ps] ACT @ (4, 3536) -> [ 5000 ps] RD @ (0, 816) -> [10000 ps] RD @ (4, 816) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2457) ->
[15000 ps] RD @ (4, 816) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 299) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1378) ->
[15000 ps] RD @ (4, 816) -> [10000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15604) ->
[10000 ps] ACT @ (4, 14524) -> [ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13445) ->
[15000 ps] RD @ (4, 808) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12366) ->
[15000 ps] RD @ (4, 808) -> [10000 ps] RD @ (0, 808) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10208) ->
[10000 ps] ACT @ (4, 9128) -> [ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8049) ->
[15000 ps] RD @ (4, 800) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5891) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6970) ->
[15000 ps] RD @ (4, 800) -> [10000 ps] RD @ (0, 800) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4812) ->
[10000 ps] ACT @ (4, 3732) -> [ 5000 ps] RD @ (0, 800) -> [10000 ps] RD @ (4, 800) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2653) ->
[15000 ps] RD @ (4, 800) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1574) ->
[15000 ps] RD @ (4, 800) -> [10000 ps] RD @ (0, 800) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15800) ->
[10000 ps] ACT @ (4, 14720) -> [ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13641) ->
[15000 ps] RD @ (4, 792) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11483) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12562) ->
[15000 ps] RD @ (4, 792) -> [10000 ps] RD @ (0, 792) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10404) ->
[10000 ps] ACT @ (4, 9324) -> [ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 7166) -> [10000 ps] ACT @ (4, 8245) -> [15000 ps] RD @ (4, 792) -> [10000 ps] RD @ (0, 784) -> [17500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 6087) -> [15000 ps] RD @ (0, 784) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3928) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 5008) -> [15000 ps] RD @ (0, 784) -> [10000 ps] RD @ (4, 784) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 2849) -> [10000 ps] ACT @ (0, 1770) -> [ 5000 ps] RD @ (4, 784) -> [10000 ps] RD @ (0, 784) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 691) -> [15000 ps] RD @ (0, 784) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 15996) -> [15000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 13837) -> [10000 ps] ACT @ (0, 12758) -> [ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 776) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 11679) -> [15000 ps] RD @ (0, 776) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 10600) -> [15000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 8441) -> [10000 ps] ACT @ (0, 7362) -> [ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 6283) -> [15000 ps] RD @ (0, 768) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 5204) -> [15000 ps] RD @ (0, 768) -> [10000 ps] RD @ (4, 768) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 3045) -> [10000 ps] ACT @ (0, 1966) -> [ 5000 ps] RD @ (4, 768) -> [10000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 887) -> [15000 ps] RD @ (0, 768) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 16192) -> [15000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 14033) -> [10000 ps] ACT @ (0, 12954) -> [ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 760) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 11875) -> [15000 ps] RD @ (0, 760) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 10796) -> [15000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 8637) -> [10000 ps] ACT @ (0, 7558) -> [ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 752) -> [17500 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5399) -> [10000 ps] ACT @ (0, 6479) -> [15000 ps] RD @ (0, 752) -> [10000 ps] RD @ (4, 752) ->
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4320) -> [15000 ps] RD @ (4, 752) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2162) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3241) -> [15000 ps] RD @ (4, 752) -> [10000 ps] RD @ (0, 752) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1083) -> [10000 ps] ACT @ (4, 3) -> [ 5000 ps] RD @ (0, 752) -> [10000 ps] RD @ (4, 752) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15308) -> [15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13150) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14229) -> [15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 744) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12071) -> [10000 ps] ACT @ (4, 10991) -> [ 5000 ps] RD @ (0, 744) -> [10000 ps] RD @ (4, 744) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9912) -> [15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7754) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8833) -> [15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 736) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6675) -> [10000 ps] ACT @ (4, 5595) -> [ 5000 ps] RD @ (0, 736) -> [10000 ps] RD @ (4, 736) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4516) -> [15000 ps] RD @ (4, 736) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2358) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3437) -> [15000 ps] RD @ (4, 736) -> [10000 ps] RD @ (0, 736) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1279) -> [10000 ps] ACT @ (4, 199) -> [ 5000 ps] RD @ (0, 736) -> [10000 ps] RD @ (4, 736) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15504) -> [15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13346) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14425) -> [15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 728) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12267) -> [10000 ps] ACT @ (4, 11187) -> [ 5000 ps] RD @ (0, 728) -> [10000 ps] RD @ (4, 728) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10108) -> [15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7950) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9029) -> [15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 720) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6871) -> [10000 ps] ACT @ (4, 5791) -> [ 5000 ps] RD @ (0, 720) -> [10000 ps] RD @ (4, 720) ->
[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) -> [15000 ps] RD @ (4, 720) ->
[10000 ps] RD @ (0, 720) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) -> [15000 ps] RD @ (0, 720) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 395) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) -> [15000 ps] RD @ (0, 720) -> [10000 ps] RD @ (4, 720) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15700) -> [10000 ps] ACT @ (0, 14621) -> [ 5000 ps] RD @ (4, 712) ->
[10000 ps] RD @ (0, 712) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) -> [15000 ps] RD @ (0, 712) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 11383) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12463) -> [15000 ps] RD @ (0, 712) -> [10000 ps] RD @ (4, 712) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10304) -> [10000 ps] ACT @ (0, 9225) -> [ 5000 ps] RD @ (4, 712) ->
[10000 ps] RD @ (0, 712) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) -> [15000 ps] RD @ (0, 704) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 5987) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) -> [15000 ps] RD @ (0, 704) -> [10000 ps] RD @ (4, 704) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4908) -> [10000 ps] ACT @ (0, 3829) -> [ 5000 ps] RD @ (4, 704) ->
[10000 ps] RD @ (0, 704) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) -> [15000 ps] RD @ (0, 704) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 591) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) -> [15000 ps] RD @ (0, 704) -> [10000 ps] RD @ (4, 704) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15896) -> [10000 ps] ACT @ (0, 14817) -> [ 5000 ps] RD @ (4, 696) ->
[10000 ps] RD @ (0, 696) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) -> [15000 ps] RD @ (0, 696) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 11579) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12659) -> [15000 ps] RD @ (0, 696) -> [10000 ps] RD @ (4, 696) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10500) -> [10000 ps] ACT @ (0, 9421) -> [ 5000 ps] RD @ (4, 696) ->
[10000 ps] RD @ (0, 696) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) -> [15000 ps] RD @ (0, 696) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 6183) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> [15000 ps] RD @ (0, 688) -> [10000 ps] RD @ (4, 688) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5104) -> [10000 ps] ACT @ (0, 4025) -> [ 5000 ps] RD @ (4, 688) ->
[10000 ps] RD @ (0, 688) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) -> [10000 ps] ACT @ (0, 2946) ->
[15000 ps] RD @ (0, 688) -> [10000 ps] RD @ (4, 688) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) -> [15000 ps] RD @ (4, 688) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15013) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) -> [15000 ps] RD @ (4, 680) ->
[10000 ps] RD @ (0, 680) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13934) -> [10000 ps] ACT @ (4, 12854) ->
[ 5000 ps] RD @ (0, 680) -> [10000 ps] RD @ (4, 680) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) -> [15000 ps] RD @ (4, 680) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9617) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) -> [15000 ps] RD @ (4, 680) ->
[10000 ps] RD @ (0, 680) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8538) -> [10000 ps] ACT @ (4, 7458) ->
[ 5000 ps] RD @ (0, 680) -> [10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) -> [15000 ps] RD @ (4, 672) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4221) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5300) -> [15000 ps] RD @ (4, 672) ->
[10000 ps] RD @ (0, 672) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3142) -> [10000 ps] ACT @ (4, 2062) ->
[ 5000 ps] RD @ (0, 672) -> [10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) -> [15000 ps] RD @ (4, 672) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15209) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16288) -> [15000 ps] RD @ (4, 664) ->
[10000 ps] RD @ (0, 664) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14130) -> [10000 ps] ACT @ (4, 13050) ->
[ 5000 ps] RD @ (0, 664) -> [10000 ps] RD @ (4, 664) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) -> [15000 ps] RD @ (4, 664) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9813) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) -> [15000 ps] RD @ (4, 664) ->
[10000 ps] RD @ (0, 664) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8734) -> [10000 ps] ACT @ (4, 7654) ->
[ 5000 ps] RD @ (0, 664) -> [10000 ps] RD @ (4, 656) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) -> [15000 ps] RD @ (4, 656) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4417) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) -> [15000 ps] RD @ (4, 656) ->
[10000 ps] RD @ (0, 656) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3338) -> [10000 ps] ACT @ (4, 2258) ->
[ 5000 ps] RD @ (0, 656) -> [10000 ps] RD @ (4, 656) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 100) ->
[10000 ps] ACT @ (4, 1179) -> [15000 ps] RD @ (4, 656) -> [10000 ps] RD @ (0, 656) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15405) ->
[15000 ps] RD @ (0, 648) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14326) ->
[15000 ps] RD @ (0, 648) -> [10000 ps] RD @ (4, 648) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12167) ->
[10000 ps] ACT @ (0, 11088) -> [ 5000 ps] RD @ (4, 648) -> [10000 ps] RD @ (0, 648) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10009) ->
[15000 ps] RD @ (0, 648) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7850) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8930) ->
[15000 ps] RD @ (0, 648) -> [10000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6771) ->
[10000 ps] ACT @ (0, 5692) -> [ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4613) ->
[15000 ps] RD @ (0, 640) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3534) ->
[15000 ps] RD @ (0, 640) -> [10000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1375) ->
[10000 ps] ACT @ (0, 296) -> [ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15601) ->
[15000 ps] RD @ (0, 632) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13442) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14522) ->
[15000 ps] RD @ (0, 632) -> [10000 ps] RD @ (4, 632) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
[17500 ps] ACT @ (4, 12363) -> [10000 ps] ACT @ (0, 11284) -> [ 5000 ps] RD @ (4, 632) -> [10000 ps] RD @ (0, 632) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 10205) -> [15000 ps] RD @ (0, 632) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8046) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 9126) -> [15000 ps] RD @ (0, 632) -> [10000 ps] RD @ (4, 624) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 6967) -> [10000 ps] ACT @ (0, 5888) -> [ 5000 ps] RD @ (4, 624) -> [10000 ps] RD @ (0, 624) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 4809) -> [15000 ps] RD @ (0, 624) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2650) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 3730) -> [15000 ps] RD @ (0, 624) -> [10000 ps] RD @ (4, 624) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 1571) -> [10000 ps] ACT @ (0, 492) -> [ 5000 ps] RD @ (4, 624) -> [10000 ps] RD @ (0, 624) -> [17500 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14717) -> [10000 ps] ACT @ (0, 15797) -> [15000 ps] RD @ (0, 616) -> [10000 ps] RD @ (4, 616) ->
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) -> [15000 ps] RD @ (4, 616) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11480) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12559) -> [15000 ps] RD @ (4, 616) -> [10000 ps] RD @ (0, 616) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10401) -> [10000 ps] ACT @ (4, 9321) -> [ 5000 ps] RD @ (0, 616) -> [10000 ps] RD @ (4, 616) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8242) -> [15000 ps] RD @ (4, 616) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6084) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7163) -> [15000 ps] RD @ (4, 608) -> [10000 ps] RD @ (0, 608) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5005) -> [10000 ps] ACT @ (4, 3925) -> [ 5000 ps] RD @ (0, 608) -> [10000 ps] RD @ (4, 608) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) -> [15000 ps] RD @ (4, 608) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 688) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1767) -> [15000 ps] RD @ (4, 608) -> [10000 ps] RD @ (0, 608) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15993) -> [10000 ps] ACT @ (4, 14913) -> [ 5000 ps] RD @ (0, 600) -> [10000 ps] RD @ (4, 600) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13834) -> [15000 ps] RD @ (4, 600) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11676) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12755) -> [15000 ps] RD @ (4, 600) -> [10000 ps] RD @ (0, 600) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10597) -> [10000 ps] ACT @ (4, 9517) -> [ 5000 ps] RD @ (0, 600) -> [10000 ps] RD @ (4, 600) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) -> [15000 ps] RD @ (4, 600) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6280) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7359) -> [15000 ps] RD @ (4, 592) -> [10000 ps] RD @ (0, 592) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5201) -> [10000 ps] ACT @ (4, 4121) -> [ 5000 ps] RD @ (0, 592) -> [10000 ps] RD @ (4, 592) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3042) -> [15000 ps] RD @ (4, 592) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 884) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1963) -> [15000 ps] RD @ (4, 592) -> [10000 ps] RD @ (0, 592) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16189) -> [10000 ps] ACT @ (4, 15109) -> [ 5000 ps] RD @ (0, 584) -> [10000 ps] RD @ (4, 584) ->
[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) -> [10000 ps] ACT @ (4, 14030) -> [15000 ps] RD @ (4, 584) ->
[10000 ps] RD @ (0, 584) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) -> [15000 ps] RD @ (0, 584) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 9713) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) -> [15000 ps] RD @ (0, 584) -> [10000 ps] RD @ (4, 584) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8634) -> [10000 ps] ACT @ (0, 7555) -> [ 5000 ps] RD @ (4, 584) ->
[10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) -> [15000 ps] RD @ (0, 576) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 4317) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) -> [15000 ps] RD @ (0, 576) -> [10000 ps] RD @ (4, 576) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3238) -> [10000 ps] ACT @ (0, 2159) -> [ 5000 ps] RD @ (4, 576) ->
[10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) -> [15000 ps] RD @ (0, 576) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 15305) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) -> [15000 ps] RD @ (0, 576) -> [10000 ps] RD @ (4, 568) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14226) -> [10000 ps] ACT @ (0, 13147) -> [ 5000 ps] RD @ (4, 568) ->
[10000 ps] RD @ (0, 568) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) -> [15000 ps] RD @ (0, 568) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 9909) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) -> [15000 ps] RD @ (0, 568) -> [10000 ps] RD @ (4, 568) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8830) -> [10000 ps] ACT @ (0, 7751) -> [ 5000 ps] RD @ (4, 568) ->
[10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) -> [15000 ps] RD @ (0, 560) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 4513) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) -> [15000 ps] RD @ (0, 560) -> [10000 ps] RD @ (4, 560) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3434) -> [10000 ps] ACT @ (0, 2355) -> [ 5000 ps] RD @ (4, 560) ->
[10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) -> [15000 ps] RD @ (0, 560) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 15501) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) -> [15000 ps] RD @ (0, 560) -> [10000 ps] RD @ (4, 552) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14422) -> [10000 ps] ACT @ (0, 13343) -> [ 5000 ps] RD @ (4, 552) ->
[10000 ps] RD @ (0, 552) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11184) -> [10000 ps] ACT @ (0, 12264) ->
[15000 ps] RD @ (0, 552) -> [10000 ps] RD @ (4, 552) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10105) -> [15000 ps] RD @ (4, 552) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7947) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9026) -> [15000 ps] RD @ (4, 552) ->
[10000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6868) -> [10000 ps] ACT @ (4, 5788) ->
[ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4709) -> [15000 ps] RD @ (4, 544) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2551) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3630) -> [15000 ps] RD @ (4, 544) ->
[10000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1472) -> [10000 ps] ACT @ (4, 392) ->
[ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15697) -> [15000 ps] RD @ (4, 536) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13539) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14618) -> [15000 ps] RD @ (4, 536) ->
[10000 ps] RD @ (0, 536) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12460) -> [10000 ps] ACT @ (4, 11380) ->
[ 5000 ps] RD @ (0, 536) -> [10000 ps] RD @ (4, 536) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10301) -> [15000 ps] RD @ (4, 536) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8143) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9222) -> [15000 ps] RD @ (4, 536) ->
[10000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7064) -> [10000 ps] ACT @ (4, 5984) ->
[ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4905) -> [15000 ps] RD @ (4, 528) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2747) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3826) -> [15000 ps] RD @ (4, 528) ->
[10000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1668) -> [10000 ps] ACT @ (4, 588) ->
[ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15893) -> [15000 ps] RD @ (4, 520) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13735) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14814) -> [15000 ps] RD @ (4, 520) ->
[10000 ps] RD @ (0, 520) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12656) -> [10000 ps] ACT @ (4, 11576) ->
[ 5000 ps] RD @ (0, 520) -> [10000 ps] RD @ (4, 520) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9418) ->
[10000 ps] ACT @ (4, 10497) -> [15000 ps] RD @ (4, 520) -> [10000 ps] RD @ (0, 520) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8339) ->
[15000 ps] RD @ (0, 520) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7260) ->
[15000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5101) ->
[10000 ps] ACT @ (0, 4022) -> [ 5000 ps] RD @ (4, 512) -> [10000 ps] RD @ (0, 512) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2943) ->
[15000 ps] RD @ (0, 512) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 784) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1864) ->
[15000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16089) ->
[10000 ps] ACT @ (0, 15010) -> [ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13931) ->
[15000 ps] RD @ (0, 504) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12852) ->
[15000 ps] RD @ (0, 504) -> [10000 ps] RD @ (4, 504) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10693) ->
[10000 ps] ACT @ (0, 9614) -> [ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8535) ->
[15000 ps] RD @ (0, 504) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6376) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7456) ->
[15000 ps] RD @ (0, 496) -> [10000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5297) ->
[10000 ps] ACT @ (0, 4218) -> [ 5000 ps] RD @ (4, 496) -> [10000 ps] RD @ (0, 496) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3139) ->
[15000 ps] RD @ (0, 496) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2060) ->
[15000 ps] RD @ (0, 496) -> [10000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16285) ->
[10000 ps] ACT @ (0, 15206) -> [ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14127) ->
[15000 ps] RD @ (0, 488) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11968) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13048) ->
[15000 ps] RD @ (0, 488) -> [10000 ps] RD @ (4, 488) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10889) ->
[10000 ps] ACT @ (0, 9810) -> [ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 7651) -> [10000 ps] ACT @ (0, 8731) -> [15000 ps] RD @ (0, 488) -> [10000 ps] RD @ (4, 480) -> [17500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 6572) -> [15000 ps] RD @ (4, 480) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4414) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 5493) -> [15000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 480) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 3335) -> [10000 ps] ACT @ (4, 2255) -> [ 5000 ps] RD @ (0, 480) -> [10000 ps] RD @ (4, 480) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 1176) -> [15000 ps] RD @ (4, 480) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15402) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 97) -> [15000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 472) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 14323) -> [10000 ps] ACT @ (4, 13243) -> [ 5000 ps] RD @ (0, 472) -> [10000 ps] RD @ (4, 472) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 12164) -> [15000 ps] RD @ (4, 472) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10006) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 11085) -> [15000 ps] RD @ (4, 472) -> [10000 ps] RD @ (0, 472) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 8927) -> [10000 ps] ACT @ (4, 7847) -> [ 5000 ps] RD @ (0, 472) -> [10000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 6768) -> [15000 ps] RD @ (4, 464) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4610) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 5689) -> [15000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 464) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 3531) -> [10000 ps] ACT @ (4, 2451) -> [ 5000 ps] RD @ (0, 464) -> [10000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 1372) -> [15000 ps] RD @ (4, 464) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15598) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 293) -> [15000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 456) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 14519) -> [10000 ps] ACT @ (4, 13439) -> [ 5000 ps] RD @ (0, 456) -> [10000 ps] RD @ (4, 456) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 12360) -> [15000 ps] RD @ (4, 456) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10202) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 11281) -> [15000 ps] RD @ (4, 456) -> [10000 ps] RD @ (0, 456) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 9123) -> [10000 ps] ACT @ (4, 8043) -> [ 5000 ps] RD @ (0, 456) -> [10000 ps] RD @ (4, 448) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5885) -> [10000 ps] ACT @ (4, 6964) -> [15000 ps] RD @ (4, 448) -> [10000 ps] RD @ (0, 448) ->
[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) -> [15000 ps] RD @ (0, 448) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2647) ->
[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3727) -> [15000 ps] RD @ (0, 448) -> [10000 ps] RD @ (4, 448) -> [17500 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1568) -> [10000 ps] ACT @ (0, 489) -> [ 5000 ps] RD @ (4, 448) -> [10000 ps] RD @ (0, 448) ->
[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15794) -> [15000 ps] RD @ (0, 440) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) ->
[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14715) -> [15000 ps] RD @ (0, 440) -> [10000 ps] RD @ (4, 440) -> [17500 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12556) -> [10000 ps] ACT @ (0, 11477) -> [ 5000 ps] RD @ (4, 440) -> [10000 ps] RD @ (0, 440) ->
[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) -> [15000 ps] RD @ (0, 440) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8239) ->
[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9319) -> [15000 ps] RD @ (0, 440) -> [10000 ps] RD @ (4, 440) -> [17500 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7160) -> [10000 ps] ACT @ (0, 6081) -> [ 5000 ps] RD @ (4, 432) -> [10000 ps] RD @ (0, 432) ->
[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5002) -> [15000 ps] RD @ (0, 432) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) ->
[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3923) -> [15000 ps] RD @ (0, 432) -> [10000 ps] RD @ (4, 432) -> [17500 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1764) -> [10000 ps] ACT @ (0, 685) -> [ 5000 ps] RD @ (4, 432) -> [10000 ps] RD @ (0, 432) ->
[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) -> [15000 ps] RD @ (0, 424) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13831) ->
[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14911) -> [15000 ps] RD @ (0, 424) -> [10000 ps] RD @ (4, 424) -> [17500 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12752) -> [10000 ps] ACT @ (0, 11673) -> [ 5000 ps] RD @ (4, 424) -> [10000 ps] RD @ (0, 424) ->
[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10594) -> [15000 ps] RD @ (0, 424) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) ->
[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9515) -> [15000 ps] RD @ (0, 424) -> [10000 ps] RD @ (4, 424) -> [17500 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7356) -> [10000 ps] ACT @ (0, 6277) -> [ 5000 ps] RD @ (4, 416) -> [10000 ps] RD @ (0, 416) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4118) -> [10000 ps] ACT @ (0, 5198) -> [15000 ps] RD @ (0, 416) ->
[10000 ps] RD @ (4, 416) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3039) -> [15000 ps] RD @ (4, 416) -> [ 7500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 881) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1960) -> [15000 ps] RD @ (4, 416) -> [ 7500 ps] NOP ->
[ 2500 ps] RD @ (0, 416) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16186) -> [10000 ps] ACT @ (4, 15106) ->
[ 5000 ps] RD @ (0, 408) -> [10000 ps] RD @ (4, 408) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
[17500 ps] ACT @ (4, 14027) -> [15000 ps] RD @ (4, 408) -> [ 5000 ps] ACT @ (0, 11869) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12948) ->
[15000 ps] RD @ (4, 408) -> [10000 ps] RD @ (0, 408) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10790) ->
[10000 ps] ACT @ (4, 9710) -> [ 5000 ps] RD @ (0, 408) -> [10000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8631) ->
[15000 ps] RD @ (4, 408) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6473) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7552) ->
[15000 ps] RD @ (4, 400) -> [10000 ps] RD @ (0, 400) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5394) ->
[10000 ps] ACT @ (4, 4314) -> [ 5000 ps] RD @ (0, 400) -> [10000 ps] RD @ (4, 400) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3235) ->
[15000 ps] RD @ (4, 400) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1077) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2156) ->
[15000 ps] RD @ (4, 400) -> [10000 ps] RD @ (0, 400) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16382) ->
[10000 ps] ACT @ (4, 15302) -> [ 5000 ps] RD @ (0, 392) -> [10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14223) ->
[15000 ps] RD @ (4, 392) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12065) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13144) ->
[15000 ps] RD @ (4, 392) -> [10000 ps] RD @ (0, 392) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10986) ->
[10000 ps] ACT @ (4, 9906) -> [ 5000 ps] RD @ (0, 392) -> [10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8827) ->
[15000 ps] RD @ (4, 392) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6669) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7748) ->
[15000 ps] RD @ (4, 384) -> [10000 ps] RD @ (0, 384) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5590) ->
[10000 ps] ACT @ (4, 4510) -> [ 5000 ps] RD @ (0, 384) -> [10000 ps] RD @ (4, 384) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 2352) -> [10000 ps] ACT @ (4, 3431) -> [15000 ps] RD @ (4, 384) -> [10000 ps] RD @ (0, 384) -> [17500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 1273) -> [15000 ps] RD @ (0, 384) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 194) -> [15000 ps] RD @ (0, 384) -> [10000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 14419) -> [10000 ps] ACT @ (0, 13340) -> [ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 376) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 12261) -> [15000 ps] RD @ (0, 376) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10102) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 11182) -> [15000 ps] RD @ (0, 376) -> [10000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 9023) -> [10000 ps] ACT @ (0, 7944) -> [ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 368) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 6865) -> [15000 ps] RD @ (0, 368) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 5786) -> [15000 ps] RD @ (0, 368) -> [10000 ps] RD @ (4, 368) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 3627) -> [10000 ps] ACT @ (0, 2548) -> [ 5000 ps] RD @ (4, 368) -> [10000 ps] RD @ (0, 368) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 1469) -> [15000 ps] RD @ (0, 368) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15694) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 390) -> [15000 ps] RD @ (0, 368) -> [10000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 14615) -> [10000 ps] ACT @ (0, 13536) -> [ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 360) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 12457) -> [15000 ps] RD @ (0, 360) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 11378) -> [15000 ps] RD @ (0, 360) -> [10000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 9219) -> [10000 ps] ACT @ (0, 8140) -> [ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 352) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 7061) -> [15000 ps] RD @ (0, 352) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4902) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 5982) -> [15000 ps] RD @ (0, 352) -> [10000 ps] RD @ (4, 352) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 3823) -> [10000 ps] ACT @ (0, 2744) -> [ 5000 ps] RD @ (4, 352) -> [10000 ps] RD @ (0, 352) -> [17500 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 585) -> [10000 ps] ACT @ (0, 1665) -> [15000 ps] RD @ (0, 352) -> [10000 ps] RD @ (4, 352) ->
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15890) -> [15000 ps] RD @ (4, 344) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13732) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14811) -> [15000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12653) -> [10000 ps] ACT @ (4, 11573) -> [ 5000 ps] RD @ (0, 344) -> [10000 ps] RD @ (4, 344) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10494) -> [15000 ps] RD @ (4, 344) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8336) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9415) -> [15000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7257) -> [10000 ps] ACT @ (4, 6177) -> [ 5000 ps] RD @ (0, 336) -> [10000 ps] RD @ (4, 336) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5098) -> [15000 ps] RD @ (4, 336) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2940) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4019) -> [15000 ps] RD @ (4, 336) -> [10000 ps] RD @ (0, 336) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1861) -> [10000 ps] ACT @ (4, 781) -> [ 5000 ps] RD @ (0, 336) -> [10000 ps] RD @ (4, 336) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16086) -> [15000 ps] RD @ (4, 328) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13928) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15007) -> [15000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12849) -> [10000 ps] ACT @ (4, 11769) -> [ 5000 ps] RD @ (0, 328) -> [10000 ps] RD @ (4, 328) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10690) -> [15000 ps] RD @ (4, 328) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8532) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9611) -> [15000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7453) -> [10000 ps] ACT @ (4, 6373) -> [ 5000 ps] RD @ (0, 320) -> [10000 ps] RD @ (4, 320) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5294) -> [15000 ps] RD @ (4, 320) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3136) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4215) -> [15000 ps] RD @ (4, 320) -> [10000 ps] RD @ (0, 320) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2057) -> [10000 ps] ACT @ (4, 977) -> [ 5000 ps] RD @ (0, 320) -> [10000 ps] RD @ (4, 320) ->
[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15203) -> [10000 ps] ACT @ (4, 16282) -> [15000 ps] RD @ (4, 312) ->
[10000 ps] RD @ (0, 312) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) -> [15000 ps] RD @ (0, 312) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 11965) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13045) -> [15000 ps] RD @ (0, 312) -> [10000 ps] RD @ (4, 312) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10886) -> [10000 ps] ACT @ (0, 9807) -> [ 5000 ps] RD @ (4, 312) ->
[10000 ps] RD @ (0, 312) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> [15000 ps] RD @ (0, 312) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 6569) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) -> [15000 ps] RD @ (0, 304) -> [10000 ps] RD @ (4, 304) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5490) -> [10000 ps] ACT @ (0, 4411) -> [ 5000 ps] RD @ (4, 304) ->
[10000 ps] RD @ (0, 304) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) -> [15000 ps] RD @ (0, 304) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 1173) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [15000 ps] RD @ (0, 304) -> [10000 ps] RD @ (4, 304) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 94) -> [10000 ps] ACT @ (0, 15399) -> [ 5000 ps] RD @ (4, 304) ->
[10000 ps] RD @ (0, 296) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) -> [15000 ps] RD @ (0, 296) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 12161) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13241) -> [15000 ps] RD @ (0, 296) -> [10000 ps] RD @ (4, 296) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11082) -> [10000 ps] ACT @ (0, 10003) -> [ 5000 ps] RD @ (4, 296) ->
[10000 ps] RD @ (0, 296) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) -> [15000 ps] RD @ (0, 296) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 6765) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7845) -> [15000 ps] RD @ (0, 288) -> [10000 ps] RD @ (4, 288) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5686) -> [10000 ps] ACT @ (0, 4607) -> [ 5000 ps] RD @ (4, 288) ->
[10000 ps] RD @ (0, 288) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) -> [15000 ps] RD @ (0, 288) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 1369) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2449) -> [15000 ps] RD @ (0, 288) -> [10000 ps] RD @ (4, 288) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 290) -> [10000 ps] ACT @ (0, 15595) -> [ 5000 ps] RD @ (4, 288) ->
[10000 ps] RD @ (0, 280) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13436) -> [10000 ps] ACT @ (0, 14516) ->
[15000 ps] RD @ (0, 280) -> [10000 ps] RD @ (4, 280) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12357) -> [15000 ps] RD @ (4, 280) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10199) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11278) -> [15000 ps] RD @ (4, 280) ->
[10000 ps] RD @ (0, 280) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9120) -> [10000 ps] ACT @ (4, 8040) ->
[ 5000 ps] RD @ (0, 280) -> [10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6961) -> [15000 ps] RD @ (4, 272) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4803) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5882) -> [15000 ps] RD @ (4, 272) ->
[10000 ps] RD @ (0, 272) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3724) -> [10000 ps] ACT @ (4, 2644) ->
[ 5000 ps] RD @ (0, 272) -> [10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1565) -> [15000 ps] RD @ (4, 272) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15791) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 486) -> [15000 ps] RD @ (4, 272) ->
[10000 ps] RD @ (0, 264) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14712) -> [10000 ps] ACT @ (4, 13632) ->
[ 5000 ps] RD @ (0, 264) -> [10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12553) -> [15000 ps] RD @ (4, 264) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10395) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11474) -> [15000 ps] RD @ (4, 264) ->
[10000 ps] RD @ (0, 264) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9316) -> [10000 ps] ACT @ (4, 8236) ->
[ 5000 ps] RD @ (0, 264) -> [10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7157) -> [15000 ps] RD @ (4, 256) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4999) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6078) -> [15000 ps] RD @ (4, 256) ->
[10000 ps] RD @ (0, 256) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3920) -> [10000 ps] ACT @ (4, 2840) ->
[ 5000 ps] RD @ (0, 256) -> [10000 ps] RD @ (4, 256) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1761) -> [15000 ps] RD @ (4, 256) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15987) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 682) -> [15000 ps] RD @ (4, 256) ->
[10000 ps] RD @ (0, 248) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14908) -> [10000 ps] ACT @ (4, 13828) ->
[ 5000 ps] RD @ (0, 248) -> [10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) ->
[10000 ps] ACT @ (4, 12749) -> [15000 ps] RD @ (4, 248) -> [10000 ps] RD @ (0, 248) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) ->
[15000 ps] RD @ (0, 248) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8432) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9512) ->
[15000 ps] RD @ (0, 248) -> [10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7353) ->
[10000 ps] ACT @ (0, 6274) -> [ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) ->
[15000 ps] RD @ (0, 240) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) ->
[15000 ps] RD @ (0, 240) -> [10000 ps] RD @ (4, 240) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1957) ->
[10000 ps] ACT @ (0, 878) -> [ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) ->
[15000 ps] RD @ (0, 232) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) ->
[15000 ps] RD @ (0, 232) -> [10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12945) ->
[10000 ps] ACT @ (0, 11866) -> [ 5000 ps] RD @ (4, 232) -> [10000 ps] RD @ (0, 232) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) ->
[15000 ps] RD @ (0, 232) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) ->
[15000 ps] RD @ (0, 232) -> [10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7549) ->
[10000 ps] ACT @ (0, 6470) -> [ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) ->
[15000 ps] RD @ (0, 224) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) ->
[15000 ps] RD @ (0, 224) -> [10000 ps] RD @ (4, 224) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2153) ->
[10000 ps] ACT @ (0, 1074) -> [ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) ->
[15000 ps] RD @ (0, 216) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) ->
[15000 ps] RD @ (0, 216) -> [10000 ps] RD @ (4, 216) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13141) ->
[10000 ps] ACT @ (0, 12062) -> [ 5000 ps] RD @ (4, 216) -> [10000 ps] RD @ (0, 216) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 9903) -> [10000 ps] ACT @ (0, 10983) -> [15000 ps] RD @ (0, 216) -> [10000 ps] RD @ (4, 216) -> [17500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 8824) -> [15000 ps] RD @ (4, 216) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6666) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 7745) -> [15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 5587) -> [10000 ps] ACT @ (4, 4507) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 208) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 3428) -> [15000 ps] RD @ (4, 208) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1270) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 2349) -> [15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 191) -> [10000 ps] ACT @ (4, 15495) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 14416) -> [15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12258) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 13337) -> [15000 ps] RD @ (4, 200) -> [10000 ps] RD @ (0, 200) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 11179) -> [10000 ps] ACT @ (4, 10099) -> [ 5000 ps] RD @ (0, 200) -> [10000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 9020) -> [15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6862) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 7941) -> [15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 5783) -> [10000 ps] ACT @ (4, 4703) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 192) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 3624) -> [15000 ps] RD @ (4, 192) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1466) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 2545) -> [15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [67500 ps] PRE @ (0) -> [30000 ps] REF ->
[360000 ps] NOP -> [17500 ps] ACT @ (0, 387) -> [10000 ps] ACT @ (4, 15691) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 184) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14612) -> [15000 ps] RD @ (4, 184) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12454) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13533) -> [15000 ps] RD @ (4, 184) -> [10000 ps] RD @ (0, 184) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11375) -> [10000 ps] ACT @ (4, 10295) -> [ 5000 ps] RD @ (0, 184) -> [10000 ps] RD @ (4, 184) ->
[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8137) -> [10000 ps] ACT @ (4, 9216) -> [15000 ps] RD @ (4, 184) ->
[10000 ps] RD @ (0, 176) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7058) -> [15000 ps] RD @ (0, 176) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 4899) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) -> [15000 ps] RD @ (0, 176) -> [10000 ps] RD @ (4, 176) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3820) -> [10000 ps] ACT @ (0, 2741) -> [ 5000 ps] RD @ (4, 176) ->
[10000 ps] RD @ (0, 176) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1662) -> [15000 ps] RD @ (0, 176) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 15887) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 583) -> [15000 ps] RD @ (0, 176) -> [10000 ps] RD @ (4, 168) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14808) -> [10000 ps] ACT @ (0, 13729) -> [ 5000 ps] RD @ (4, 168) ->
[10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) -> [15000 ps] RD @ (0, 168) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 10491) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) -> [15000 ps] RD @ (0, 168) -> [10000 ps] RD @ (4, 168) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9412) -> [10000 ps] ACT @ (0, 8333) -> [ 5000 ps] RD @ (4, 168) ->
[10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7254) -> [15000 ps] RD @ (0, 160) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 5095) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6175) -> [15000 ps] RD @ (0, 160) -> [10000 ps] RD @ (4, 160) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4016) -> [10000 ps] ACT @ (0, 2937) -> [ 5000 ps] RD @ (4, 160) ->
[10000 ps] RD @ (0, 160) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) -> [15000 ps] RD @ (0, 160) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 16083) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) -> [15000 ps] RD @ (0, 160) -> [10000 ps] RD @ (4, 152) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15004) -> [10000 ps] ACT @ (0, 13925) -> [ 5000 ps] RD @ (4, 152) ->
[10000 ps] RD @ (0, 152) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12846) -> [15000 ps] RD @ (0, 152) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 10687) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11767) -> [15000 ps] RD @ (0, 152) -> [10000 ps] RD @ (4, 152) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9608) -> [10000 ps] ACT @ (0, 8529) -> [ 5000 ps] RD @ (4, 152) ->
[10000 ps] RD @ (0, 152) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6370) -> [10000 ps] ACT @ (0, 7450) ->
[15000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5291) -> [15000 ps] RD @ (4, 144) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4212) -> [15000 ps] RD @ (4, 144) ->
[10000 ps] RD @ (0, 144) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2054) -> [10000 ps] ACT @ (4, 974) ->
[ 5000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16279) -> [15000 ps] RD @ (4, 136) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14121) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15200) -> [15000 ps] RD @ (4, 136) ->
[10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13042) -> [10000 ps] ACT @ (4, 11962) ->
[ 5000 ps] RD @ (0, 136) -> [10000 ps] RD @ (4, 136) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10883) -> [15000 ps] RD @ (4, 136) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9804) -> [15000 ps] RD @ (4, 136) ->
[10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7646) -> [10000 ps] ACT @ (4, 6566) ->
[ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5487) -> [15000 ps] RD @ (4, 128) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4408) -> [15000 ps] RD @ (4, 128) ->
[10000 ps] RD @ (0, 128) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2250) -> [10000 ps] ACT @ (4, 1170) ->
[ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 91) -> [15000 ps] RD @ (4, 128) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15396) -> [15000 ps] RD @ (4, 120) ->
[10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13238) -> [10000 ps] ACT @ (4, 12158) ->
[ 5000 ps] RD @ (0, 120) -> [10000 ps] RD @ (4, 120) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11079) -> [15000 ps] RD @ (4, 120) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10000) -> [15000 ps] RD @ (4, 120) ->
[10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7842) -> [10000 ps] ACT @ (4, 6762) ->
[ 5000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) ->
[10000 ps] ACT @ (4, 5683) -> [15000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 112) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) ->
[15000 ps] RD @ (0, 112) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2446) ->
[15000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 287) ->
[10000 ps] ACT @ (0, 15592) -> [ 5000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) ->
[15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12354) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) ->
[15000 ps] RD @ (0, 104) -> [10000 ps] RD @ (4, 104) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11275) ->
[10000 ps] ACT @ (0, 10196) -> [ 5000 ps] RD @ (4, 104) -> [10000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) ->
[15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) ->
[15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5879) ->
[10000 ps] ACT @ (0, 4800) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 96) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) ->
[15000 ps] RD @ (0, 96) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1562) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) ->
[15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 483) ->
[10000 ps] ACT @ (0, 15788) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) ->
[15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) ->
[15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 88) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11471) ->
[10000 ps] ACT @ (0, 10392) -> [ 5000 ps] RD @ (4, 88) -> [10000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) ->
[15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7154) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) ->
[15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6075) ->
[10000 ps] ACT @ (0, 4996) -> [ 5000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 80) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 2837) -> [10000 ps] ACT @ (0, 3917) -> [15000 ps] RD @ (0, 80) -> [10000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 1758) -> [15000 ps] RD @ (4, 80) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15984) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 679) -> [15000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 72) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 14905) -> [10000 ps] ACT @ (4, 13825) -> [ 5000 ps] RD @ (0, 72) -> [10000 ps] RD @ (4, 72) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 12746) -> [15000 ps] RD @ (4, 72) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10588) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 11667) -> [15000 ps] RD @ (4, 72) -> [10000 ps] RD @ (0, 72) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 9509) -> [10000 ps] ACT @ (4, 8429) -> [ 5000 ps] RD @ (0, 72) -> [10000 ps] RD @ (4, 72) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 7350) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5192) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 6271) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 64) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 4113) -> [10000 ps] ACT @ (4, 3033) -> [ 5000 ps] RD @ (0, 64) -> [10000 ps] RD @ (4, 64) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 1954) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16180) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 875) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 56) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 15101) -> [10000 ps] ACT @ (4, 14021) -> [ 5000 ps] RD @ (0, 56) -> [10000 ps] RD @ (4, 56) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 12942) -> [15000 ps] RD @ (4, 56) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10784) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 11863) -> [15000 ps] RD @ (4, 56) -> [10000 ps] RD @ (0, 56) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 9705) -> [10000 ps] ACT @ (4, 8625) -> [ 5000 ps] RD @ (0, 56) -> [10000 ps] RD @ (4, 56) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 7546) -> [15000 ps] RD @ (4, 48) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5388) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 6467) -> [15000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 4309) -> [10000 ps] ACT @ (4, 3229) -> [ 5000 ps] RD @ (0, 48) -> [10000 ps] RD @ (4, 48) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1071) -> [10000 ps] ACT @ (4, 2150) -> [15000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) ->
[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) -> [15000 ps] RD @ (0, 40) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) ->
[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) -> [15000 ps] RD @ (0, 40) -> [10000 ps] RD @ (4, 40) -> [17500 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13138) -> [10000 ps] ACT @ (0, 12059) -> [ 5000 ps] RD @ (4, 40) -> [10000 ps] RD @ (0, 40) ->
[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10980) -> [15000 ps] RD @ (0, 40) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) ->
[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9901) -> [15000 ps] RD @ (0, 40) -> [10000 ps] RD @ (4, 40) -> [17500 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7742) -> [10000 ps] ACT @ (0, 6663) -> [ 5000 ps] RD @ (4, 32) -> [10000 ps] RD @ (0, 32) ->
[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) -> [15000 ps] RD @ (0, 32) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) ->
[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) -> [15000 ps] RD @ (0, 32) -> [10000 ps] RD @ (4, 32) -> [17500 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2346) -> [10000 ps] ACT @ (0, 1267) -> [ 5000 ps] RD @ (4, 32) -> [10000 ps] RD @ (0, 32) ->
[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 188) -> [15000 ps] RD @ (0, 32) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) ->
[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15493) -> [15000 ps] RD @ (0, 24) -> [10000 ps] RD @ (4, 24) -> [17500 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13334) -> [10000 ps] ACT @ (0, 12255) -> [ 5000 ps] RD @ (4, 24) -> [10000 ps] RD @ (0, 24) ->
[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) -> [15000 ps] RD @ (0, 24) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) ->
[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) -> [15000 ps] RD @ (0, 24) -> [10000 ps] RD @ (4, 24) -> [17500 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7938) -> [10000 ps] ACT @ (0, 6859) -> [ 5000 ps] RD @ (4, 16) -> [10000 ps] RD @ (0, 16) ->
[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5780) -> [15000 ps] RD @ (0, 16) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) ->
[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4701) -> [15000 ps] RD @ (0, 16) -> [10000 ps] RD @ (4, 16) -> [17500 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2542) -> [10000 ps] ACT @ (0, 1463) -> [ 5000 ps] RD @ (4, 16) -> [10000 ps] RD @ (0, 16) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15688) -> [10000 ps] ACT @ (0, 384) -> [15000 ps] RD @ (0, 16) ->
[10000 ps] RD @ (4, 8) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) -> [15000 ps] RD @ (4, 8) -> [ 7500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 12451) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13530) -> [15000 ps] RD @ (4, 8) -> [10000 ps] RD @ (0, 8) ->
[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11372) -> [10000 ps] ACT @ (4, 10292) -> [ 5000 ps] RD @ (0, 8) ->
[10000 ps] RD @ (4, 8) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9213) -> [15000 ps] RD @ (4, 8) -> [ 7500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 7055) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) -> [15000 ps] RD @ (4, 0) -> [10000 ps] RD @ (0, 0) ->
[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5976) -> [10000 ps] ACT @ (4, 4896) -> [ 5000 ps] RD @ (0, 0) ->
[10000 ps] RD @ (4, 0) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) -> [15000 ps] RD @ (4, 0) -> [ 7500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 1659) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2738) -> [15000 ps] RD @ (4, 0) -> [10000 ps] RD @ (0, 0) ->
[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 580) -> [15000 ps] RD @ (0, 0) -> [ 5000 ps] ACT @ (7, 15884) -> [15000 ps] RD @ (7, 1016) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13727) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14805) -> [15000 ps] RD @ (7, 1016) ->
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13726) -> [15000 ps] RD @ (7, 1016) ->
[ 5000 ps] ACT @ (3, 12647) -> [ 2500 ps] PRE @ (4) -> [12500 ps] RD @ (3, 1016) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10489) ->
[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> [15000 ps] RD @ (3, 1016) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (7, 10488) -> [10000 ps] ACT @ (0, 9410) -> [ 5000 ps] RD @ (7, 1016) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (7, 9409) -> [10000 ps] ACT @ (0, 8331) -> [ 5000 ps] RD @ (7, 1016) -> [ 5000 ps] ACT @ (4, 7251) -> [22500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 8330) -> [15000 ps] RD @ (7, 1016) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7251) ->
[10000 ps] ACT @ (4, 6172) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5093) -> [ 2500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 6172) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5092) ->
[10000 ps] ACT @ (0, 4014) -> [ 5000 ps] RD @ (7, 1008) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 4013) ->
[10000 ps] ACT @ (0, 2935) -> [ 5000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1855) -> [ 2500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 2934) -> [15000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 1855) ->
[10000 ps] ACT @ (4, 776) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16081) -> [ 2500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 776) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 16080) ->
[10000 ps] ACT @ (0, 15002) -> [ 5000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13922) -> [ 2500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 15001) -> [15000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13922) ->
[10000 ps] ACT @ (4, 12843) -> [ 5000 ps] RD @ (3, 1000) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 12843) ->
[10000 ps] ACT @ (4, 11764) -> [ 5000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (0) -> [10000 ps] NOP -> [ 7500 ps] ACT @ (0, 10685) ->
[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11764) -> [15000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10684) ->
[15000 ps] RD @ (7, 1000) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 9606) ->
[10000 ps] ACT @ (7, 9605) -> [10000 ps] ACT @ (4, 8526) -> [ 5000 ps] RD @ (7, 1000) -> [ 5000 ps] ACT @ (3, 8526) -> [15000 ps] RD @ (3, 1000) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 6368) -> [10000 ps] ACT @ (3, 7447) -> [15000 ps] RD @ (3, 992) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5289) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6368) -> [15000 ps] RD @ (3, 992) ->
[ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5288) -> [10000 ps] ACT @ (0, 4210) -> [ 5000 ps] RD @ (7, 992) ->
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3130) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4209) -> [15000 ps] RD @ (7, 992) ->
[ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 3130) -> [10000 ps] ACT @ (4, 2051) -> [ 5000 ps] RD @ (3, 992) ->
[27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 2051) -> [10000 ps] ACT @ (4, 972) -> [ 5000 ps] RD @ (3, 992) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16277) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 972) -> [15000 ps] RD @ (3, 992) ->
[ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 16276) -> [10000 ps] ACT @ (0, 15198) -> [ 5000 ps] RD @ (7, 984) ->
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14118) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15197) -> [15000 ps] RD @ (7, 984) ->
[ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 14118) -> [10000 ps] ACT @ (4, 13039) -> [ 5000 ps] RD @ (3, 984) ->
[27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13039) -> [10000 ps] ACT @ (4, 11960) -> [ 5000 ps] RD @ (3, 984) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10881) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11960) -> [15000 ps] RD @ (3, 984) ->
[ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10880) -> [10000 ps] ACT @ (0, 9802) -> [ 5000 ps] RD @ (7, 984) ->
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8722) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9801) -> [15000 ps] RD @ (7, 984) ->
[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8722) -> [15000 ps] RD @ (3, 984) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) ->
[15000 ps] RD @ (3, 976) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5484) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) ->
[15000 ps] RD @ (3, 976) -> [10000 ps] RD @ (7, 976) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4405) ->
[10000 ps] ACT @ (3, 3326) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (3, 976) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) ->
[15000 ps] RD @ (3, 976) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 88) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) ->
[15000 ps] RD @ (3, 976) -> [10000 ps] RD @ (7, 976) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15393) ->
[10000 ps] ACT @ (3, 14314) -> [ 5000 ps] RD @ (7, 968) -> [10000 ps] RD @ (3, 968) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
[ 7500 ps] ACT @ (7, 12155) -> [10000 ps] ACT @ (3, 13235) -> [15000 ps] RD @ (3, 968) -> [10000 ps] RD @ (7, 968) -> [17500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 11076) -> [15000 ps] RD @ (7, 968) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8918) -> [ 2500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 9997) -> [15000 ps] RD @ (7, 968) -> [10000 ps] RD @ (3, 968) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
[ 7500 ps] ACT @ (3, 7839) -> [10000 ps] ACT @ (7, 6759) -> [ 5000 ps] RD @ (3, 960) -> [10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 5680) -> [15000 ps] RD @ (7, 960) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3522) -> [ 2500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 4601) -> [15000 ps] RD @ (7, 960) -> [10000 ps] RD @ (3, 960) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
[ 7500 ps] ACT @ (3, 2443) -> [10000 ps] ACT @ (7, 1363) -> [ 5000 ps] RD @ (3, 960) -> [10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 284) -> [15000 ps] RD @ (7, 960) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14510) -> [ 2500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 15589) -> [15000 ps] RD @ (7, 952) -> [10000 ps] RD @ (3, 952) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
[ 7500 ps] ACT @ (3, 13431) -> [10000 ps] ACT @ (7, 12351) -> [ 5000 ps] RD @ (3, 952) -> [10000 ps] RD @ (7, 952) -> [27500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 11272) -> [15000 ps] RD @ (7, 952) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9114) -> [ 2500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 10193) -> [15000 ps] RD @ (7, 952) -> [10000 ps] RD @ (3, 952) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
[ 7500 ps] ACT @ (3, 8035) -> [10000 ps] ACT @ (7, 6955) -> [ 5000 ps] RD @ (3, 944) -> [10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 5876) -> [15000 ps] RD @ (7, 944) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3718) -> [ 2500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 4797) -> [15000 ps] RD @ (7, 944) -> [10000 ps] RD @ (3, 944) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
[ 7500 ps] ACT @ (3, 2639) -> [10000 ps] ACT @ (7, 1559) -> [ 5000 ps] RD @ (3, 944) -> [10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 480) -> [15000 ps] RD @ (7, 944) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14706) -> [ 2500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 15785) -> [15000 ps] RD @ (7, 936) -> [10000 ps] RD @ (3, 936) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
[ 7500 ps] ACT @ (3, 13627) -> [10000 ps] ACT @ (7, 12547) -> [ 5000 ps] RD @ (3, 936) -> [10000 ps] RD @ (7, 936) -> [17500 ps] PRE @ (3) ->
[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10389) -> [10000 ps] ACT @ (7, 11468) -> [15000 ps] RD @ (7, 936) -> [10000 ps] RD @ (3, 936) ->
[17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9310) -> [15000 ps] RD @ (3, 936) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) ->
[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8231) -> [15000 ps] RD @ (3, 936) -> [10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) ->
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6072) -> [10000 ps] ACT @ (3, 4993) -> [ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 928) ->
[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3914) -> [15000 ps] RD @ (3, 928) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) ->
[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2835) -> [15000 ps] RD @ (3, 928) -> [10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) ->
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 676) -> [10000 ps] ACT @ (3, 15981) -> [ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 920) ->
[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14902) -> [15000 ps] RD @ (3, 920) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) ->
[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13823) -> [15000 ps] RD @ (3, 920) -> [10000 ps] RD @ (7, 920) -> [17500 ps] PRE @ (7) ->
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 11664) -> [10000 ps] ACT @ (3, 10585) -> [ 5000 ps] RD @ (7, 920) -> [10000 ps] RD @ (3, 920) ->
[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9506) -> [15000 ps] RD @ (3, 920) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) ->
[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8427) -> [15000 ps] RD @ (3, 920) -> [10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) ->
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6268) -> [10000 ps] ACT @ (3, 5189) -> [ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 912) ->
[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4110) -> [15000 ps] RD @ (3, 912) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) ->
[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3031) -> [15000 ps] RD @ (3, 912) -> [10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) ->
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 872) -> [10000 ps] ACT @ (3, 16177) -> [ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 904) ->
[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15098) -> [15000 ps] RD @ (3, 904) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) ->
[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14019) -> [15000 ps] RD @ (3, 904) -> [10000 ps] RD @ (7, 904) -> [17500 ps] PRE @ (7) ->
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 11860) -> [10000 ps] ACT @ (3, 10781) -> [ 5000 ps] RD @ (7, 904) -> [10000 ps] RD @ (3, 904) ->
[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8622) -> [10000 ps] ACT @ (3, 9702) -> [15000 ps] RD @ (3, 904) ->
[10000 ps] RD @ (7, 904) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7543) -> [15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 5385) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6464) -> [15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 896) ->
[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4306) -> [10000 ps] ACT @ (7, 3226) -> [ 5000 ps] RD @ (3, 896) ->
[10000 ps] RD @ (7, 896) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2147) -> [15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 16373) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1068) -> [15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 888) ->
[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15294) -> [10000 ps] ACT @ (7, 14214) -> [ 5000 ps] RD @ (3, 888) ->
[10000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13135) -> [15000 ps] RD @ (7, 888) -> [ 7500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 10977) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12056) -> [15000 ps] RD @ (7, 888) -> [10000 ps] RD @ (3, 888) ->
[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 9898) -> [10000 ps] ACT @ (7, 8818) -> [ 5000 ps] RD @ (3, 888) ->
[10000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7739) -> [15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 5581) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6660) -> [15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) ->
[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4502) -> [10000 ps] ACT @ (7, 3422) -> [ 5000 ps] RD @ (3, 880) ->
[10000 ps] RD @ (7, 880) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2343) -> [15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 185) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1264) -> [15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) ->
[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15490) -> [10000 ps] ACT @ (7, 14410) -> [ 5000 ps] RD @ (3, 872) ->
[10000 ps] RD @ (7, 872) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13331) -> [15000 ps] RD @ (7, 872) -> [ 7500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 11173) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12252) -> [15000 ps] RD @ (7, 872) -> [10000 ps] RD @ (3, 872) ->
[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10094) -> [10000 ps] ACT @ (7, 9014) -> [ 5000 ps] RD @ (3, 872) ->
[10000 ps] RD @ (7, 872) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) ->
[15000 ps] RD @ (7, 864) -> [10000 ps] RD @ (3, 864) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5777) -> [15000 ps] RD @ (3, 864) ->
[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3618) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4698) -> [15000 ps] RD @ (3, 864) ->
[10000 ps] RD @ (7, 864) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 2539) -> [10000 ps] ACT @ (3, 1460) ->
[ 5000 ps] RD @ (7, 864) -> [10000 ps] RD @ (3, 864) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 381) -> [15000 ps] RD @ (3, 864) ->
[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14606) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15686) -> [15000 ps] RD @ (3, 856) ->
[10000 ps] RD @ (7, 856) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 13527) -> [10000 ps] ACT @ (3, 12448) ->
[ 5000 ps] RD @ (7, 856) -> [10000 ps] RD @ (3, 856) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11369) -> [15000 ps] RD @ (3, 856) ->
[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9210) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10290) -> [15000 ps] RD @ (3, 856) ->
[10000 ps] RD @ (7, 856) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8131) -> [10000 ps] ACT @ (3, 7052) ->
[ 5000 ps] RD @ (7, 848) -> [10000 ps] RD @ (3, 848) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5973) -> [15000 ps] RD @ (3, 848) ->
[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3814) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4894) -> [15000 ps] RD @ (3, 848) ->
[10000 ps] RD @ (7, 848) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 2735) -> [10000 ps] ACT @ (3, 1656) ->
[ 5000 ps] RD @ (7, 848) -> [10000 ps] RD @ (3, 848) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 577) -> [15000 ps] RD @ (3, 848) ->
[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14802) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15882) -> [15000 ps] RD @ (3, 840) ->
[10000 ps] RD @ (7, 840) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 13723) -> [10000 ps] ACT @ (3, 12644) ->
[ 5000 ps] RD @ (7, 840) -> [10000 ps] RD @ (3, 840) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11565) -> [15000 ps] RD @ (3, 840) ->
[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9406) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10486) -> [15000 ps] RD @ (3, 840) ->
[10000 ps] RD @ (7, 840) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8327) -> [10000 ps] ACT @ (3, 7248) ->
[ 5000 ps] RD @ (7, 840) -> [10000 ps] RD @ (3, 832) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5089) ->
[10000 ps] ACT @ (3, 6169) -> [15000 ps] RD @ (3, 832) -> [10000 ps] RD @ (7, 832) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) ->
[15000 ps] RD @ (7, 832) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1852) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) ->
[15000 ps] RD @ (7, 832) -> [10000 ps] RD @ (3, 832) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 773) ->
[10000 ps] ACT @ (7, 16077) -> [ 5000 ps] RD @ (3, 832) -> [10000 ps] RD @ (7, 824) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) ->
[15000 ps] RD @ (7, 824) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12840) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) ->
[15000 ps] RD @ (7, 824) -> [10000 ps] RD @ (3, 824) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11761) ->
[10000 ps] ACT @ (7, 10681) -> [ 5000 ps] RD @ (3, 824) -> [10000 ps] RD @ (7, 824) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) ->
[15000 ps] RD @ (7, 824) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7444) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) ->
[15000 ps] RD @ (7, 824) -> [10000 ps] RD @ (3, 816) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6365) ->
[10000 ps] ACT @ (7, 5285) -> [ 5000 ps] RD @ (3, 816) -> [10000 ps] RD @ (7, 816) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) ->
[15000 ps] RD @ (7, 816) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2048) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) ->
[15000 ps] RD @ (7, 816) -> [10000 ps] RD @ (3, 816) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 969) ->
[10000 ps] ACT @ (7, 16273) -> [ 5000 ps] RD @ (3, 816) -> [10000 ps] RD @ (7, 808) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) ->
[15000 ps] RD @ (7, 808) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13036) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) ->
[15000 ps] RD @ (7, 808) -> [10000 ps] RD @ (3, 808) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11957) ->
[10000 ps] ACT @ (7, 10877) -> [ 5000 ps] RD @ (3, 808) -> [10000 ps] RD @ (7, 808) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) ->
[15000 ps] RD @ (7, 808) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7640) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) ->
[15000 ps] RD @ (7, 808) -> [10000 ps] RD @ (3, 800) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6561) ->
[10000 ps] ACT @ (7, 5481) -> [ 5000 ps] RD @ (3, 800) -> [10000 ps] RD @ (7, 800) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
[ 7500 ps] ACT @ (3, 3323) -> [10000 ps] ACT @ (7, 4402) -> [15000 ps] RD @ (7, 800) -> [10000 ps] RD @ (3, 800) -> [17500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 2244) -> [15000 ps] RD @ (3, 800) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 85) -> [ 2500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 1165) -> [15000 ps] RD @ (3, 800) -> [10000 ps] RD @ (7, 800) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
[ 7500 ps] ACT @ (7, 15390) -> [10000 ps] ACT @ (3, 14311) -> [ 5000 ps] RD @ (7, 792) -> [10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 13232) -> [15000 ps] RD @ (3, 792) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11073) -> [ 2500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 12153) -> [15000 ps] RD @ (3, 792) -> [10000 ps] RD @ (7, 792) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
[ 7500 ps] ACT @ (7, 9994) -> [10000 ps] ACT @ (3, 8915) -> [ 5000 ps] RD @ (7, 792) -> [10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 7836) -> [15000 ps] RD @ (3, 784) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5677) -> [ 2500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 6757) -> [15000 ps] RD @ (3, 784) -> [10000 ps] RD @ (7, 784) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
[ 7500 ps] ACT @ (7, 4598) -> [10000 ps] ACT @ (3, 3519) -> [ 5000 ps] RD @ (7, 784) -> [10000 ps] RD @ (3, 784) -> [67500 ps] PRE @ (0) ->
[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (3, 2440) -> [15000 ps] RD @ (3, 784) -> [ 5000 ps] ACT @ (7, 281) ->
[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) -> [15000 ps] RD @ (3, 784) -> [10000 ps] RD @ (7, 784) -> [17500 ps] PRE @ (7) ->
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15586) -> [10000 ps] ACT @ (3, 14507) -> [ 5000 ps] RD @ (7, 776) -> [10000 ps] RD @ (3, 776) ->
[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) -> [15000 ps] RD @ (3, 776) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11269) ->
[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12349) -> [15000 ps] RD @ (3, 776) -> [10000 ps] RD @ (7, 776) -> [17500 ps] PRE @ (7) ->
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10190) -> [10000 ps] ACT @ (3, 9111) -> [ 5000 ps] RD @ (7, 776) -> [10000 ps] RD @ (3, 776) ->
[27500 ps] PRE @ (3) ->
--------------------------------
DONE TEST 2: RANDOM
Number of Operations: 2304
Time Started: 162720 ns
Time Done: 272280 ns
Average Rate: 47 ns/request
--------------------------------
[17500 ps] ACT @ (3, 8032) -> [15000 ps] RD @ (3, 768) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) ->
[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6953) -> [15000 ps] RD @ (3, 768) -> [10000 ps] RD @ (7, 768) -> FAILED: Address = 18962384, expected data = 8fa2201f8fa1121f8fa0041f8f9ef61f8f9dea1f8f9cdc1f8f9bce1f8f9ac01f8f99b21f8f98a41f8f97961f8f96881f8f957a1f8f946c1f8f93601f8f92521f, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 272420000.0 ps
------- SUMMARY -------
Number of Writes = 4608
Number of Reads = 4608
Number of Success = 4604
Number of Fails = 4
Number of Injected Errors = 4
$stop called at time : 273380 ns : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 456
run: Time (s): cpu = 00:00:16 ; elapsed = 00:52:07 . Memory (MB): peak = 2833.148 ; gain = 8.004 ; free physical = 1814 ; free virtual = 24675
## quit
INFO: xsimkernel Simulation Memory Usage: 305696 KB (Peak: 371232 KB), Simulation CPU Usage: 3030440 ms
INFO: [Common 17-206] Exiting xsim at Wed Jul 5 19:44:03 2023...
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