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ddr3_dimm_micron_sim.sh - Script generated by export_simulation (Vivado v2021.2 (64-bit)-id)
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr3
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr3_dimm
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ddr3_dimm_micron_sim
Vivado Simulator v2021.2
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
Running: /tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:204]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:135]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:156]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:157]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:158]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:159]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:160]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:161]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:163]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:165]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:250]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:275]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:276]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:281]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:283]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:319]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:325]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:326]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:374]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:375]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'TCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:426]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:427]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:452]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:453]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:458]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:460]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:497]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:498]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:499]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:501]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:504]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:506]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:536]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:575]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:576]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:580]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:582]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:583]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:631]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:632]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:700]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:701]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:747]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:163]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:164]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cke' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:165]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 's_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:166]
WARNING: [VRFC 10-3091] actual bit length 14 differs from formal bit length 16 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:171]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'odt' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:172]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:173]
WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:174]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:203]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:204]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:205]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:206]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:207]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:208]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:209]
WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:210]
WARNING: [VRFC 10-5021] port 'scl' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:161]
WARNING: [VRFC 10-5021] port 'i_controller_dm' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v:119]
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.ddr3_controller(CONTROLLER_CLK_P...
Compiling module unisims_ver.OSERDESE2(DATA_RATE_OQ="SDR",DAT...
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="SDR",DAT...
Compiling module unisims_ver.OBUFDS
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT...
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
Compiling module unisims_ver.IOBUF(IOSTANDARD="SSTL15",SLEW="...
Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="...
Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE...
Compiling module unisims_ver.OBUF(SLEW="FAST")
Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT...
Compiling module unisims_ver.IOBUFDS(IOSTANDARD="DIFF_SSTL15"...
Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="...
Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE...
Compiling module unisims_ver.IDELAYCTRL_default
Compiling module xil_defaultlib.ddr3_phy(CONTROLLER_CLK_PERIOD=1...
Compiling module xil_defaultlib.ddr3_top(CONTROLLER_CLK_PERIOD=1...
Compiling module xil_defaultlib.ddr3_default
Compiling module xil_defaultlib.ddr3_dimm_default
Compiling module xil_defaultlib.ddr3_dimm_micron_sim
Compiling module xil_defaultlib.glbl
Built simulation snapshot ddr3_dimm_micron_sim
****** xsim v2021.2 (64-bit)
**** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
**** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl
# xsim {ddr3_dimm_micron_sim} -autoloadwcfg -tclbatch {cmd.tcl} -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim}
Time resolution is 1 ps
source cmd.tcl
## set curr_wave [current_wave_config]
## if { [string length $curr_wave] == 0 } {
## if { [llength [get_objects]] > 0} {
## add_wave /
## set_property needs_save false [current_wave_config]
## } else {
## send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
## }
## }
## run -all
Test ns_to_cycles() function:
ns_to_cycles(15) = 3 = 2 [exact]
ns_to_cycles(14.5) = 3 = 2 [round-off]
ns_to_cycles(11) = 3 = 2 [round-up]
Test nCK_to_cycles() function:
ns_to_cycles(16) = 4 = 4 [exact]
ns_to_cycles(15) = 4 = 4 [round-off]
ns_to_cycles(13) = 4 = 4 [round-up]
Test ns_to_nCK() function:
ns_to_cycles(15) = 12 = 6 [exact]
ns_to_cycles(14.875) = 12 = 6 [round-off]
ns_to_cycles(13.875) = 12 = 6 [round-up]
ns_to_nCK(tRCD) = 11 = 6 [WRONG]
tRTP = 7.5 = 10.000000
ns_to_nCK(tRTP) = 6= 4.000000 [WRONG]
Test nCK_to_ns() function:
ns_to_cycles(4) = 5 = 10 [exact]
ns_to_cycles(14.875) = 4 = 8 [round-off]
ns_to_cycles(13.875) = 7 = 13 [round-up]
Test nCK_to_ns() function:
ns_to_cycles(4) = 5 = 10 [exact]
ns_to_cycles(14.875) = 4 = 8 [round-off]
ns_to_cycles(13.875) = 7 = 13 [round-up]
Test $floor() function:
$floor(5/2) = 2.5 = 2
$floor(9/4) = 2.25 = 2
$floor(9/4) = 2 = 2
$floor(9/5) = 1.8 = 1
DELAY_COUNTER_WIDTH = 16
DELAY_SLOT_WIDTH = 19
serdes_ratio = 4
wb_addr_bits = 24
wb_data_bits = 512
wb_sel_bits = 64
READ_SLOT = 2
WRITE_SLOT = 3
ACTIVATE_SLOT = 0
PRECHARGE_SLOT = 1
DELAYS:
ns_to_nCK(tRCD): 6
ns_to_nCK(tRP): 6
ns_to_nCK(tRTP): 4
tCCD: 4
(CL_nCK + tCCD + 3'd2 - CWL_nCK): 7
(CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15
(CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13
$signed(4'b1100)>>>4: 1111
PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1
ACTIVATE_TO_WRITE_DELAY = 3 = 0
ACTIVATE_TO_READ_DELAY = 2 = 0
READ_TO_WRITE_DELAY = 2 = 1
READ_TO_READ_DELAY = 0 = 0
READ_TO_PRECHARGE_DELAY = 1 =1
WRITE_TO_WRITE_DELAY = 0 = 0
WRITE_TO_READ_DELAY = 4 = 3
WRITE_TO_PRECHARGE_DELAY = 5 = 4
STAGE2_DATA_DEPTH = 2 = 2
READ_ACK_PIPE_WIDTH = 6
ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
[x ps] MRS -> [ 7500 ps] MRS -> ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive.
[195000 ps] NOP -> [510000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
[370000 ps] MRS ->
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
[10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [40000 ps] ZQC ->
[1290000 ps] PRE @ (0) -> [30000 ps] MRS -> [10000 ps] NOP -> [40000 ps] NOP -> [262500 ps] RD @ (0, 0) ->
[140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
[580000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
[150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [580000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
[150000 ps] RD @ (0, 0) -> [580000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [580000 ps] RD @ (0, 0) ->
[140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
[150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [580000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
[580000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
[150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [580000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) ->
[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) ->
[150000 ps] RD @ (0, 0) -> [347500 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [110000 ps] NOP ->
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40324225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40326725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40329225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40331725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40334225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40336725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40339225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40341725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40344225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40346725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40474225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40476725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40479225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40481725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40484225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40486725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40489225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40491725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40494225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40496725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40624291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40626791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40629291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40631791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40634291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40636791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40639291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40641791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40644291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40646791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40774369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40776869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40779369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40781869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40784369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40786869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40789369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40791869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40794369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40796869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42722975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42725475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42727975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42730475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42732975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42735475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42737975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42740475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42742975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42745475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42872975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42875475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42877975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42880475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42882975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42885475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42887975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42890475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42892975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42895475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45124225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45126725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45129225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45131725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45134225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45136725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45139225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45141725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45144225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45146725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45274225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45276725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45279225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45281725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45284225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45286725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45289225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45291725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45294225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45296725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45424291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45426791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45429291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45431791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45434291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45436791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45439291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45441791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45444291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45446791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45574369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45576869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45579369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45581869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45584369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45586869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45589369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45591869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45594369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45596869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47522975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47525475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47527975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47530475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47532975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47535475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47537975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47540475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47542975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47545475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47672975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47675475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47677975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47680475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47682975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47685475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47687975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47690475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47692975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47695475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49924225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49926725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49929225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49931725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49934225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49936725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49939225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49941725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49944225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49946725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 50074225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 50076725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 50079225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 50081725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 50084225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 50086725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 50089225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 50091725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 50094225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 50096725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50224291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50226791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50229291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50231791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50234291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50236791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50239291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50241791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50244291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50246791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50374369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50376869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50379369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50381869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50384369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50386869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50389369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50391869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50394369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50396869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52322975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52325475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52327975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52330475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52332975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52335475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52337975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52340475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52342975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52345475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52472975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52475475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52477975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52480475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52482975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52485475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52487975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52490475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52492975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52495475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54724225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54726725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54729225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54731725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54734225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54736725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54739225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54741725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54744225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54746725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54874225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54876725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54879225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54881725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54884225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54886725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54889225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54891725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54894225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54896725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55024291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55026791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55029291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55031791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55034291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55036791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55039291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55041791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55044291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55046791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55174369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55176869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55179369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55181869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55184369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55186869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55189369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55191869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55194369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55196869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57122975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57125475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57127975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57130475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57132975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57135475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57137975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57140475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57142975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57145475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57272975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57275475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57277975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57280475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57282975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57285475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57287975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57290475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57292975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57295475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59524225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59526725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59529225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59531725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59534225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59536725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59539225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59541725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59544225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59546725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59674225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59676725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59679225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59681725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59684225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59686725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59689225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59691725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59694225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59696725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59824291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59826791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59829291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59831791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59834291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59836791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59839291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59841791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59844291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59846791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59974369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59976869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59979369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59981869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59984369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59986869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59989369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59991869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59994369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59996869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 61922975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 61925475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 61927975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 61930475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 61932975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 61935475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 61937975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 61940475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 61942975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 61945475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 62072975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 62075475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 62077975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 62080475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 62082975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 62085475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 62087975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 62090475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 62092975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 62095475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64324225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64326725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64329225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64331725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64334225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64336725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64339225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64341725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64344225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64346725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64474225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64476725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64479225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64481725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64484225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64486725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64489225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64491725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64494225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64496725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64624291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64626791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64629291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64631791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64634291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64636791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64639291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64641791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64644291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64646791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64774369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64776869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64779369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64781869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64784369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64786869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64789369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64791869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64794369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64796869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66722975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66725475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66727975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66730475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66732975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66735475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66737975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66740475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66742975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66745475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66872975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66875475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66877975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66880475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66882975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66885475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66887975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66890475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66892975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66895475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69124225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69126725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69129225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69131725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69134225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69136725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69139225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69141725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69144225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69146725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69274225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69276725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69279225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69281725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69284225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69286725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69289225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69291725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69294225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69296725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69424291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69426791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69429291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69431791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69434291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69436791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69439291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69441791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69444291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69446791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69574369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69576869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69579369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69581869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69584369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69586869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69589369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69591869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69594369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69596869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71522975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71525475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71527975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71530475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71532975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71535475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71537975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71540475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71542975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71545475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71672975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71675475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71677975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71680475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71682975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71685475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71687975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71690475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71692975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71695475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 73924225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 73926725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 73929225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 73931725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 73934225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 73936725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 73939225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 73941725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 73944225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 73946725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 74074225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 74076725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 74079225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 74081725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 74084225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 74086725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 74089225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 74091725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 74094225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 74096725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74224291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74226791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74229291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74231791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74234291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74236791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74239291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74241791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74244291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74246791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74374369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74376869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74379369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74381869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74384369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74386869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74389369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74391869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74394369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74396869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76322975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76325475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76327975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76330475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76332975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76335475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76337975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76340475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76342975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76345475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76472975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76475475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76477975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76480475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76482975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76485475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76487975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76490475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76492975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76495475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 76623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 76625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 76628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 76630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 76633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 76635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 76638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 76640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 76643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 76645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
[38270000 ps] MRS -> [10000 ps] NOP -> [40000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
[37500 ps] ACT @ (0, 0) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [37500 ps] RD @ (0, 0) -> [202500 ps] WR @ (0, 0) ->
[10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) ->
[10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) ->
[10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) ->
[10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) ->
[10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) ->
[10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) ->
[10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) ->
[10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) ->
[10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) ->
[10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) ->
[10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) ->
[10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) ->
[10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) ->
[10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) ->
[10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) ->
[10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) ->
[10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) ->
[10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) ->
[10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) ->
[10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) ->
[10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) ->
[10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) ->
[10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) ->
[10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) ->
[10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 0) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) ->
[10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) ->
[10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) ->
[10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) ->
[10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) ->
[10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) ->
[10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) ->
[10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) ->
[10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) ->
[10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) ->
[10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) ->
[10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) ->
[10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) ->
[10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) ->
[10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) ->
[10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) ->
[10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) ->
[10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) ->
[10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) ->
[10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) ->
[10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) ->
[10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) ->
[10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) ->
[10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) ->
[10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) ->
[10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) ->
[ 2500 ps] ACT @ (2, 0) -> [ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) ->
[10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) ->
[10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) ->
[10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) ->
[10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) ->
[10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) ->
[10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) ->
[10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) ->
[10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) ->
[10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) ->
[10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) ->
[10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) ->
[10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) ->
[10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) ->
[10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) ->
[10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) ->
[10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) ->
[10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) ->
[10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) ->
[10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) ->
[10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) ->
[10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) ->
[10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) ->
[10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) ->
[10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) ->
[10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 0) ->
[ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) ->
[10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) ->
[10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) ->
[10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) ->
[10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) ->
[10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) ->
[10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) ->
[10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) ->
[10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) ->
[10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) ->
[10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) ->
[10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) ->
[10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) ->
[10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) ->
[10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) ->
[10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) ->
[10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) ->
[10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) ->
[10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) ->
[10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) ->
[10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) ->
[10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) ->
[10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) ->
[10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) ->
[10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) ->
[10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 0) -> [ 7500 ps] WR @ (3, 976) ->
[10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) ->
[10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) ->
[10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) ->
[10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) ->
[10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) ->
[10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) ->
[10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) ->
[10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) ->
[10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) ->
[10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) ->
[10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) ->
[10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) ->
[10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) ->
[10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) ->
[10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) ->
[10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) ->
[10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) ->
[10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) ->
[10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) ->
[10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) ->
[10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) ->
[10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) ->
[10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) ->
[10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) ->
[10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) ->
[10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 0) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) ->
[10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) ->
[10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) ->
[10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) ->
[10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) ->
[10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) ->
[10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) ->
[10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) ->
[10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) ->
[10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) ->
[10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) ->
[10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) ->
[10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) ->
[10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) ->
[10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) ->
[10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) ->
[10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) ->
[10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) ->
[10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) ->
[10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) ->
[10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) ->
[10000 ps] WR @ (5, 768) -> [10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) ->
[10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) ->
[10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) ->
[ 5000 ps] NOP -> [ 5000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [65000 ps] PRE @ (0) ->
[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (5, 0) -> [17500 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) ->
[10000 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) ->
[10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 0) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) ->
[10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) ->
[10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) ->
[10000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) ->
[10000 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) ->
[10000 ps] WR @ (6, 136) -> [10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) ->
[10000 ps] WR @ (6, 176) -> [10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) ->
[10000 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) ->
[10000 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) ->
[10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) ->
[10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) ->
[10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) ->
[10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) ->
[10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) ->
[10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) ->
[10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) ->
[10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) ->
[10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) ->
[10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) ->
[10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) ->
[10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) ->
[10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) ->
[10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) ->
[10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) ->
[10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) ->
[10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) ->
[ 2500 ps] ACT @ (7, 0) -> [ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) ->
[10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) ->
[10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) ->
[10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) ->
[10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) ->
[10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) ->
[10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) ->
[10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) ->
[10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) ->
[10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) ->
[10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) ->
[10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) ->
[10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) ->
[10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) ->
[10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) ->
[10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) ->
[10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) ->
[10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) ->
[10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) ->
[10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) ->
[10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) ->
[10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) ->
[10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) ->
[10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) ->
[10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) ->
[10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 1) ->
[ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) ->
[10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) ->
[10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) ->
[10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) ->
[10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) ->
[10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) ->
[10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) ->
[10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) ->
[10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) ->
[10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) ->
[10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) ->
[10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) ->
[10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) ->
[10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) ->
[10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) ->
[10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) ->
[10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) ->
[10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) ->
[10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) ->
[10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) ->
[10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) ->
[10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) ->
[10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) ->
[10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) ->
[10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) ->
[10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 1) -> [ 7500 ps] WR @ (0, 976) ->
[10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 0) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) ->
[10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) ->
[10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) ->
[10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) ->
[10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) ->
[10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) ->
[10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) ->
[10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) ->
[10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) ->
[10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) ->
[10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) ->
[10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) ->
[10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) ->
[10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) ->
[10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) ->
[10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) ->
[10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) ->
[10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) ->
[10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) ->
[10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) ->
[10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) ->
[10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) ->
[10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) ->
[10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) ->
[10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) ->
[ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) ->
[10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) ->
[10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) ->
[10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) ->
[10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) ->
[10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) ->
[10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) ->
[10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) ->
[10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) ->
[10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) ->
[10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) ->
[10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) ->
[10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) ->
[10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) ->
[10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) ->
[10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) ->
[10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) ->
[10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) ->
[10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) ->
[10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) ->
[10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) ->
[10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) ->
[10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) ->
[10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) ->
[10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) ->
[10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 0) ->
[ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) ->
[10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) ->
[10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) ->
[10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) ->
[10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) ->
[10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) ->
[10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) ->
[10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) ->
[10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) ->
[10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) ->
[10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) ->
[10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) ->
[10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) ->
[10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) ->
[10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) ->
[10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) ->
[10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) ->
[10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) ->
[10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) ->
[10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) ->
[10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) ->
[10000 ps] RD @ (2, 792) -> [10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) ->
[10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) ->
[10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) ->
[10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (2, 936) ->
[10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
[17500 ps] ACT @ (2, 0) -> [15000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 0) -> [ 5000 ps] RD @ (2, 976) ->
[10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) ->
[10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) ->
[10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) ->
[10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) ->
[10000 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) ->
[10000 ps] RD @ (3, 160) -> [10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) ->
[10000 ps] RD @ (3, 200) -> [10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) ->
[10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) ->
[10000 ps] RD @ (3, 280) -> [10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) ->
[10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) ->
[10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) ->
[10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) ->
[10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) ->
[10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) ->
[10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) ->
[10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) ->
[10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) ->
[10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) ->
[10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) ->
[10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) ->
[10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) ->
[10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) ->
[10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) ->
[10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) ->
[10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) ->
[10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 0) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) ->
[10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) ->
[10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) ->
[10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) ->
[10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) ->
[10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) ->
[10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) ->
[10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) ->
[10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) ->
[10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) ->
[10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) ->
[10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) ->
[10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) ->
[10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) ->
[10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) ->
[10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) ->
[10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) ->
[10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) ->
[10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) ->
[10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) ->
[10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) ->
[10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) ->
[10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) ->
[10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) ->
[10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) ->
[10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) ->
[10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 0) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) ->
[10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) ->
[10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) ->
[10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) ->
[10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) ->
[10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) ->
[10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) ->
[10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) ->
[10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) ->
[10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) ->
[10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) ->
[10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) ->
[10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) ->
[10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) ->
[10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) ->
[10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) ->
[10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) ->
[10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) ->
[10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) ->
[10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) ->
[10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) ->
[10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) ->
[10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) ->
[10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) ->
[10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) ->
[10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) ->
[ 5000 ps] ACT @ (6, 0) -> [ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) ->
[10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) ->
[10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) ->
[10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) ->
[10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) ->
[10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) ->
[10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) ->
[10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) ->
[10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) ->
[10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) ->
[10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) ->
[10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) ->
[10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) ->
[10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) ->
[10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) ->
[10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) ->
[10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) ->
[10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) ->
[10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) ->
[10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) ->
[10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) ->
[10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) ->
[10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) ->
[10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) ->
[10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) ->
[10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 0) ->
[ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) ->
[10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) ->
[10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) ->
[10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) ->
[10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) ->
[10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) ->
[10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) ->
[10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) ->
[10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) ->
[10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) ->
[10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) ->
[10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) ->
[10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) ->
[10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) ->
[10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) ->
[10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) ->
[10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) ->
[10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) ->
[10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) ->
[10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) ->
[10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) ->
[10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) ->
[10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) ->
[10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) ->
[10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) ->
[10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 1) -> [ 5000 ps] RD @ (7, 976) ->
[10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) ->
[10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) ->
[10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) ->
[10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) ->
[10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) ->
[10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) ->
[10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) ->
[10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) ->
[10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) ->
[10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) ->
[10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) ->
[10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) ->
[10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) ->
[10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) ->
[10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) ->
[10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) ->
[10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) ->
[10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) ->
[10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) ->
[10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) ->
[10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) ->
[10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) ->
[10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) ->
[10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) ->
[10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) ->
[10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 1) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) ->
--------------------------------
DONE TEST 1: FIRST ROW
Number of Operations: 2304
Time Started: 77450 ns
Time Done: 101540 ns
Average Rate: 10 ns/request
--------------------------------
[10000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [27500 ps] NOP ->
FAILED: Address = 1150, expected data = cbcfbe97cbceb097cbcda297cbcc9497cbcb8897cbca7a97cbc96c97cbc85e97cbc75097cbc64297cbc53497cbc42697cbc31897cbc20a97cbc0fe97cbbff097, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 101620000.0 ps
[70000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (0, 8192) -> [17500 ps] WR @ (0, 0) ->
[10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) ->
[10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) ->
[10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) ->
[10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) ->
[10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) ->
[10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) ->
[10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) ->
[10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) ->
[10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) ->
[10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) ->
[10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) ->
[10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) ->
[10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) ->
[10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) ->
[10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) ->
[10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) ->
[10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) ->
[10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) ->
[10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) ->
[10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) ->
[10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) ->
[10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) ->
[10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) ->
[10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) ->
[10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 8192) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) ->
[10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) ->
[10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) ->
[10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) ->
[10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) ->
[10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) ->
[10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) ->
[10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) ->
[10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) ->
[10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) ->
[10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) ->
[10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) ->
[10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) ->
[10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) ->
[10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) ->
[10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) ->
[10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) ->
[10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) ->
[10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) ->
[10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) ->
[10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) ->
[10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) ->
[10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) ->
[10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) ->
[10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) ->
[10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) ->
[ 2500 ps] ACT @ (2, 8192) -> [ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) ->
[10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) ->
[10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) ->
[10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) ->
[10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) ->
[10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) ->
[10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) ->
[10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) ->
[10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) ->
[10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) ->
[10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) ->
[10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) ->
[10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) ->
[10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) ->
[10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) ->
[10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) ->
[10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) ->
[10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) ->
[10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) ->
[10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) ->
[10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) ->
[10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) ->
[10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) ->
[10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) ->
[10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) ->
[10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 8192) ->
[ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) ->
[10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) ->
[10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) ->
[10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) ->
[10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) ->
[10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) ->
[10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) ->
[10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) ->
[10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) ->
[10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) ->
[10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) ->
[10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) ->
[10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) ->
[10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) ->
[10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) ->
[10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) ->
[10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) ->
[10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) ->
[10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) ->
[10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) ->
[10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) ->
[10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) ->
[10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) ->
[10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) ->
[10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) ->
[10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 8192) -> [ 7500 ps] WR @ (3, 976) ->
[10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) ->
[10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) ->
[10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) ->
[10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) ->
[10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) ->
[10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) ->
[10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) ->
[10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) ->
[10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) ->
[10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) ->
[10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) ->
[10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) ->
[10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) ->
[10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) ->
[10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) ->
[10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) ->
[10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) ->
[10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) ->
[10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) ->
[10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) ->
[10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) ->
[10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) ->
[10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) ->
[10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) ->
[10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) ->
[10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 8192) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) ->
[10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) ->
[10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) ->
[10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) ->
[10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) ->
[10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) ->
[10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) ->
[10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) ->
[10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) ->
[10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) ->
[10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) ->
[10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) ->
[10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) ->
[10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) ->
[10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) ->
[10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) ->
[10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) ->
[10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) ->
[10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) ->
[10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) ->
[10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) ->
[10000 ps] WR @ (5, 768) -> [10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) ->
[10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) ->
[10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) ->
[10000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) ->
[10000 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) ->
[10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 8192) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) ->
[10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) ->
[10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) ->
[10000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) ->
[10000 ps] WR @ (6, 88) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (6, 8192) ->
[17500 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) ->
[10000 ps] WR @ (6, 136) -> [10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) ->
[10000 ps] WR @ (6, 176) -> [10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) ->
[10000 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) ->
[10000 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) ->
[10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) ->
[10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) ->
[10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) ->
[10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) ->
[10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) ->
[10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) ->
[10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) ->
[10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) ->
[10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) ->
[10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) ->
[10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) ->
[10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) ->
[10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) ->
[10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) ->
[10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) ->
[10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) ->
[10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) ->
[ 2500 ps] ACT @ (7, 8192) -> [ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) ->
[10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) ->
[10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) ->
[10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) ->
[10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) ->
[10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) ->
[10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) ->
[10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) ->
[10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) ->
[10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) ->
[10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) ->
[10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) ->
[10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) ->
[10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) ->
[10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) ->
[10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) ->
[10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) ->
[10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) ->
[10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) ->
[10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) ->
[10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) ->
[10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) ->
[10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) ->
[10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) ->
[10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) ->
[10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 8193) ->
[ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) ->
[10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) ->
[10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) ->
[10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) ->
[10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) ->
[10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) ->
[10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) ->
[10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) ->
[10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) ->
[10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) ->
[10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) ->
[10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) ->
[10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) ->
[10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) ->
[10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) ->
[10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) ->
[10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) ->
[10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) ->
[10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) ->
[10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) ->
[10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) ->
[10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) ->
[10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) ->
[10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) ->
[10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) ->
[10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 8193) -> [ 7500 ps] WR @ (0, 976) ->
[10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8192) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) ->
[10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) ->
[10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) ->
[10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) ->
[10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) ->
[10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) ->
[10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) ->
[10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) ->
[10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) ->
[10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) ->
[10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) ->
[10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) ->
[10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) ->
[10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) ->
[10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) ->
[10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) ->
[10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) ->
[10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) ->
[10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) ->
[10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) ->
[10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) ->
[10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) ->
[10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) ->
[10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) ->
[10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) ->
[ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 8192) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) ->
[10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) ->
[10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) ->
[10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) ->
[10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) ->
[10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) ->
[10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) ->
[10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) ->
[10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) ->
[10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) ->
[10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) ->
[10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) ->
[10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) ->
[10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) ->
[10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) ->
[10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) ->
[10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) ->
[10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) ->
[10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) ->
[10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) ->
[10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) ->
[10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) ->
[10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) ->
[10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) ->
[10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) ->
[10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 8192) ->
[ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) ->
[10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) ->
[10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) ->
[10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) ->
[10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) ->
[10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) ->
[10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) ->
[10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) ->
[10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) ->
[10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) ->
[10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) ->
[10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) ->
[10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) ->
[10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) ->
[10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) ->
[10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) ->
[10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) ->
[10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) ->
[10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) ->
[10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) ->
[10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) ->
[10000 ps] RD @ (2, 792) -> [10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) ->
[10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) ->
[10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) ->
[10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) ->
[10000 ps] RD @ (2, 952) -> [10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 8192) -> [ 5000 ps] RD @ (2, 976) ->
[10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) ->
[10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) ->
[10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) ->
[10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) ->
[ 7500 ps] NOP -> [ 2500 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [67500 ps] PRE @ (0) ->
[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (3, 8192) -> [15000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) ->
[10000 ps] RD @ (3, 160) -> [10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) ->
[10000 ps] RD @ (3, 200) -> [10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) ->
[10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) ->
[10000 ps] RD @ (3, 280) -> [10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) ->
[10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) ->
[10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) ->
[10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) ->
[10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) ->
[10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) ->
[10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) ->
[10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) ->
[10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) ->
[10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) ->
[10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) ->
[10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) ->
[10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) ->
[10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) ->
[10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) ->
[10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) ->
[10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) ->
[10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 8192) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) ->
[10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) ->
[10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) ->
[10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) ->
[10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) ->
[10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) ->
[10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) ->
[10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) ->
[10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) ->
[10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) ->
[10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) ->
[10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) ->
[10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) ->
[10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) ->
[10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) ->
[10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) ->
[10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) ->
[10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) ->
[10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) ->
[10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) ->
[10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) ->
[10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) ->
[10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) ->
[10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) ->
[10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) ->
[10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) ->
[10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 8192) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) ->
[10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) ->
[10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) ->
[10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) ->
[10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) ->
[10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) ->
[10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) ->
[10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) ->
[10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) ->
[10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) ->
[10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) ->
[10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) ->
[10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) ->
[10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) ->
[10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) ->
[10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) ->
[10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) ->
[10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) ->
[10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) ->
[10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) ->
[10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) ->
[10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) ->
[10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) ->
[10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) ->
[10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) ->
[10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) ->
[ 5000 ps] ACT @ (6, 8192) -> [ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) ->
[10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) ->
[10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) ->
[10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) ->
[10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) ->
[10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) ->
[10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) ->
[10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) ->
[10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) ->
[10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) ->
[10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) ->
[10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) ->
[10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) ->
[10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) ->
[10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) ->
[10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) ->
[10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) ->
[10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) ->
[10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) ->
[10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) ->
[10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) ->
[10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) ->
[10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) ->
[10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) ->
[10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) ->
[10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 8192) ->
[ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) ->
[10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) ->
[10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) ->
[10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) ->
[10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) ->
[10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) ->
[10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) ->
[10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) ->
[10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) ->
[10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) ->
[10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) ->
[10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) ->
[10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) ->
[10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) ->
[10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) ->
[10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) ->
[10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) ->
[10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) ->
[10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) ->
[10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) ->
[10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) ->
[10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) ->
[10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) ->
[10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) ->
[10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) ->
[10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 8193) -> [ 5000 ps] RD @ (7, 976) ->
[10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) ->
[10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) ->
[10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) ->
[10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) ->
[10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) ->
[10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) ->
[10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) ->
[10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) ->
[10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) ->
[10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) ->
[10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) ->
[10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) ->
[10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) ->
[10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) ->
[10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) ->
[10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) ->
[10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) ->
[10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) ->
[10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) ->
[10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) ->
[10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) ->
[10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) ->
[10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) ->
[10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) ->
[10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) ->
[10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 8193) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) ->
--------------------------------
DONE TEST 1: MIDDLE ROW
Number of Operations: 2304
Time Started: 101640 ns
Time Done: 126130 ns
Average Rate: 10 ns/request
--------------------------------
[10000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> FAILED: Address = 8389758, expected data = 33cfbf6733ceb16733cda36733cc956733cb896733ca7b6733c96d6733c85f6733c7516733c6436733c5356733c4276733c3196733c20b6733c0ff6733bff167, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 126210000.0 ps
[97500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 16383) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) ->
[10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) ->
[10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) ->
[10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) ->
[10000 ps] WR @ (0, 144) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 16383) ->
[17500 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) ->
[10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) ->
[10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) ->
[10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) ->
[10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) ->
[10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) ->
[10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) ->
[10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) ->
[10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) ->
[10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) ->
[10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) ->
[10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) ->
[10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) ->
[10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) ->
[10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) ->
[10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) ->
[10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) ->
[10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) ->
[10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) ->
[10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) ->
[10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 16383) -> [ 7500 ps] WR @ (0, 976) ->
[10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) ->
[10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) ->
[10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) ->
[10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) ->
[10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) ->
[10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) ->
[10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) ->
[10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) ->
[10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) ->
[10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) ->
[10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) ->
[10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) ->
[10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) ->
[10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) ->
[10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) ->
[10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) ->
[10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) ->
[10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) ->
[10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) ->
[10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) ->
[10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) ->
[10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) ->
[10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) ->
[10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) ->
[10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) ->
[10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 16383) -> [ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) ->
[10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) ->
[10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) ->
[10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) ->
[10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) ->
[10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) ->
[10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) ->
[10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) ->
[10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) ->
[10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) ->
[10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) ->
[10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) ->
[10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) ->
[10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) ->
[10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) ->
[10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) ->
[10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) ->
[10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) ->
[10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) ->
[10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) ->
[10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) ->
[10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) ->
[10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) ->
[10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) ->
[10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) ->
[10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) ->
[10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 16383) -> [ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) ->
[10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) ->
[10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) ->
[10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) ->
[10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) ->
[10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) ->
[10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) ->
[10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) ->
[10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) ->
[10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) ->
[10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) ->
[10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) ->
[10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) ->
[10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) ->
[10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) ->
[10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) ->
[10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) ->
[10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) ->
[10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) ->
[10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) ->
[10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) ->
[10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) ->
[10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) ->
[10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) ->
[10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) ->
[10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) ->
[ 2500 ps] ACT @ (4, 16383) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) ->
[10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) ->
[10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) ->
[10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) ->
[10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) ->
[10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) ->
[10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) ->
[10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) ->
[10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) ->
[10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) ->
[10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) ->
[10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) ->
[10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) ->
[10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) ->
[10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) ->
[10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) ->
[10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) ->
[10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) ->
[10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) ->
[10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) ->
[10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) ->
[10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) ->
[10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) ->
[10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) ->
[10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) ->
[10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 16383) ->
[ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) ->
[10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) ->
[10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) ->
[10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) ->
[10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) ->
[10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) ->
[10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) ->
[10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) ->
[10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) ->
[10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) ->
[10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) ->
[10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) ->
[10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) ->
[10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) ->
[10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) ->
[10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) ->
[10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) ->
[10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) ->
[10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) ->
[10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) ->
[10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> [10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) ->
[10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) ->
[10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) ->
[10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) ->
[10000 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) ->
[10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 16383) -> [ 7500 ps] WR @ (5, 976) ->
[10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) ->
[10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) ->
[10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) ->
[10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) ->
[10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> [10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) ->
[10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> [10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) ->
[10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) -> [ 5000 ps] NOP ->
[ 5000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [65000 ps] PRE @ (0) -> [30000 ps] REF ->
[360000 ps] NOP -> [17500 ps] ACT @ (6, 16383) -> [17500 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) ->
[10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) ->
[10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) ->
[10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) ->
[10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) ->
[10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) ->
[10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) ->
[10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) ->
[10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) ->
[10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) ->
[10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) ->
[10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) ->
[10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) ->
[10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) ->
[10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) ->
[10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) ->
[10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) ->
[10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) ->
[10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 16383) -> [ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) ->
[10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) ->
[10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) ->
[10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) ->
[10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) ->
[10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) ->
[10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) ->
[10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) ->
[10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) ->
[10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) ->
[10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) ->
[10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) ->
[10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) ->
[10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) ->
[10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) ->
[10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) ->
[10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) ->
[10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) ->
[10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) ->
[10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) ->
[10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) ->
[10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) ->
[10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) ->
[10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) ->
[10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) ->
[10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) ->
[10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 0) -> [ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) ->
[10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) ->
[10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) ->
[10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) ->
[10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) ->
[10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) ->
[10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) ->
[10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) ->
[10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) ->
[10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) ->
[10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) ->
[10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) ->
[10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) ->
[10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) ->
[10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) ->
[10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) ->
[10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) ->
[10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) ->
[10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) ->
[10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) ->
[10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) ->
[10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) ->
[10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) ->
[10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) ->
[10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) ->
[10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) ->
[ 2500 ps] ACT @ (1, 0) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) ->
[10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16383) -> [15000 ps] RD @ (0, 0) ->
[10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) ->
[10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) ->
[10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) ->
[10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) ->
[10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) ->
[10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) ->
[10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) ->
[10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) ->
[10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) ->
[10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) ->
[10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) ->
[10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) ->
[10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) ->
[10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) ->
[10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) ->
[10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) ->
[10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) ->
[10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) ->
[10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) ->
[10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) ->
[10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) ->
[10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) ->
[10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) ->
[10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) ->
[10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 16383) ->
[ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) ->
[10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) ->
[10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) ->
[10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) ->
[10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) ->
[10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) ->
[10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) ->
[10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) ->
[10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) ->
[10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) ->
[10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) ->
[10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) ->
[10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) ->
[10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) ->
[10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) ->
[10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) ->
[10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) ->
[10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) ->
[10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) ->
[10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) ->
[10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) ->
[10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) ->
[10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) ->
[10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) ->
[10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) ->
[10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 16383) -> [ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) ->
[10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) ->
[10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) ->
[10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) ->
[10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) ->
[10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) ->
[10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) ->
[10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) ->
[10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) ->
[10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) ->
[10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) ->
[10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) ->
[10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) ->
[10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) ->
[10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) ->
[10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) ->
[10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) ->
[10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) ->
[10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) ->
[10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) ->
[10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) ->
[10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> [10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) ->
[10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) ->
[10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) ->
[10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) ->
[10000 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> [10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) ->
[ 5000 ps] ACT @ (3, 16383) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) ->
[10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) ->
[10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) ->
[10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) ->
[10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) ->
[10000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> [10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) ->
[10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> [10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) ->
[10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) ->
[10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (3, 280) -> [10000 ps] RD @ (3, 288) ->
[10000 ps] RD @ (3, 296) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (3, 16383) ->
[15000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) ->
[10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) ->
[10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) ->
[10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) ->
[10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) ->
[10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) ->
[10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) ->
[10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) ->
[10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) ->
[10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) ->
[10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) ->
[10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) ->
[10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) ->
[10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) ->
[10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) ->
[10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) ->
[10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 16383) ->
[ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) ->
[10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) ->
[10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) ->
[10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) ->
[10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) ->
[10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) ->
[10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) ->
[10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) ->
[10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) ->
[10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) ->
[10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) ->
[10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) ->
[10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) ->
[10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) ->
[10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) ->
[10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) ->
[10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) ->
[10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) ->
[10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) ->
[10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) ->
[10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) ->
[10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) ->
[10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) ->
[10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) ->
[10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) ->
[10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 16383) -> [ 5000 ps] RD @ (4, 976) ->
[10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) ->
[10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) ->
[10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) ->
[10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) ->
[10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) ->
[10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) ->
[10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) ->
[10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) ->
[10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) ->
[10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) ->
[10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) ->
[10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) ->
[10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) ->
[10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) ->
[10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) ->
[10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) ->
[10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) ->
[10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) ->
[10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) ->
[10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) ->
[10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) ->
[10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) ->
[10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) ->
[10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) ->
[10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) ->
[10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 16383) -> [ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) ->
[10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) ->
[10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) ->
[10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) ->
[10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) ->
[10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) ->
[10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) ->
[10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) ->
[10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) ->
[10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) ->
[10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) ->
[10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) ->
[10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) ->
[10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) ->
[10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) ->
[10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) ->
[10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) ->
[10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) ->
[10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) ->
[10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) ->
[10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) ->
[10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) ->
[10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) ->
[10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) ->
[10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) ->
[10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) ->
[10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 16383) -> [ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) ->
[10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) ->
[10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) ->
[10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) ->
[10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) ->
[10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) ->
[10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) ->
[10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) ->
[10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) ->
[10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) ->
[10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) ->
[10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) ->
[10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) ->
[10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) ->
[10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) ->
[10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) ->
[10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) ->
[10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) ->
[10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) ->
[10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) ->
[10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) ->
[10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) ->
[10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) ->
[10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) ->
[10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) ->
[10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) ->
[ 5000 ps] ACT @ (0, 0) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) ->
[10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) ->
[10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) ->
[10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) ->
[10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) ->
[10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) ->
[10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) ->
[10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) ->
[10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) ->
[10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) ->
[10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) ->
[10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) ->
[10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) ->
[10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) ->
[10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) ->
[10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) ->
[10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) ->
[10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) ->
[10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) ->
[10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) ->
[10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) ->
[10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) ->
[10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) ->
[10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) ->
[10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) ->
[10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 0) ->
[ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) ->
--------------------------------
DONE TEST 1: LAST ROW
Number of Operations: 2304
Time Started: 126230 ns
Time Done: 150800 ns
Average Rate: 10 ns/request
--------------------------------
[10000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) ->
[10000 ps] RD @ (0, 1016) -> FAILED: Address = 16777342, expected data = 585c7fb0585b71b0585a63b0585955b0585849b058573bb058562db058551fb0585411b0585303b05851f5b05850e7b0584fd9b0584ecbb0584dbfb0584cb1b0, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 150880000.0 ps
[97500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2852) -> [10000 ps] ACT @ (0, 1773) ->
[ 7500 ps] WR @ (4, 960) -> [10000 ps] WR @ (0, 960) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15998) ->
[10000 ps] ACT @ (0, 694) -> [17500 ps] WR @ (0, 960) -> [10000 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14919) ->
[17500 ps] WR @ (4, 952) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12761) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13840) ->
[17500 ps] WR @ (4, 952) -> [10000 ps] WR @ (0, 952) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10602) ->
[10000 ps] ACT @ (0, 11682) -> [17500 ps] WR @ (0, 952) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 9523) -> [17500 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8444) -> [17500 ps] WR @ (4, 952) ->
[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 7365) -> [17500 ps] WR @ (0, 944) ->
[ 2500 ps] ACT @ (4, 5206) -> [42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6286) -> [17500 ps] WR @ (0, 944) -> [10000 ps] WR @ (4, 944) ->
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4127) -> [17500 ps] WR @ (4, 944) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) ->
[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3048) -> [17500 ps] WR @ (4, 944) -> [10000 ps] WR @ (0, 944) -> [35000 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16194) -> [10000 ps] ACT @ (0, 890) -> [17500 ps] WR @ (0, 944) -> [10000 ps] WR @ (4, 936) ->
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15115) -> [17500 ps] WR @ (4, 936) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12957) ->
[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14036) -> [17500 ps] WR @ (4, 936) -> [10000 ps] WR @ (0, 936) -> [35000 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10798) -> [10000 ps] ACT @ (0, 11878) -> [17500 ps] WR @ (0, 936) -> [10000 ps] WR @ (4, 936) ->
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9719) -> [17500 ps] WR @ (4, 936) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) ->
[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8640) -> [17500 ps] WR @ (4, 936) -> [10000 ps] WR @ (0, 928) -> [35000 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5402) -> [10000 ps] ACT @ (0, 6482) -> [17500 ps] WR @ (0, 928) -> [10000 ps] WR @ (4, 928) ->
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4323) -> [17500 ps] WR @ (4, 928) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2165) ->
[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3244) -> [17500 ps] WR @ (4, 928) -> [10000 ps] WR @ (0, 928) -> [35000 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6) -> [10000 ps] ACT @ (0, 1086) -> [17500 ps] WR @ (0, 928) -> [10000 ps] WR @ (4, 928) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14232) -> [10000 ps] ACT @ (4, 15311) -> [17500 ps] WR @ (4, 920) ->
[10000 ps] WR @ (0, 920) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) -> [17500 ps] WR @ (0, 920) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 10994) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) -> [17500 ps] WR @ (0, 920) -> [10000 ps] WR @ (4, 920) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8836) -> [10000 ps] ACT @ (4, 9915) -> [17500 ps] WR @ (4, 920) ->
[10000 ps] WR @ (0, 920) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) -> [17500 ps] WR @ (0, 912) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 5598) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6678) -> [17500 ps] WR @ (0, 912) -> [10000 ps] WR @ (4, 912) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3440) -> [10000 ps] ACT @ (4, 4519) -> [17500 ps] WR @ (4, 912) ->
[10000 ps] WR @ (0, 912) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) -> [17500 ps] WR @ (0, 912) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 202) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) -> [17500 ps] WR @ (0, 912) -> [10000 ps] WR @ (4, 912) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14428) -> [10000 ps] ACT @ (4, 15507) -> [17500 ps] WR @ (4, 904) ->
[10000 ps] WR @ (0, 904) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) -> [17500 ps] WR @ (0, 904) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 11190) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12270) -> [17500 ps] WR @ (0, 904) -> [10000 ps] WR @ (4, 904) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9032) -> [10000 ps] ACT @ (4, 10111) -> [17500 ps] WR @ (4, 904) ->
[10000 ps] WR @ (0, 904) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) -> [17500 ps] WR @ (0, 896) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 5794) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) -> [17500 ps] WR @ (0, 896) -> [10000 ps] WR @ (4, 896) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3636) -> [10000 ps] ACT @ (4, 4715) -> [17500 ps] WR @ (4, 896) ->
[10000 ps] WR @ (0, 896) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) -> [17500 ps] WR @ (0, 896) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 398) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1478) -> [17500 ps] WR @ (0, 896) -> [10000 ps] WR @ (4, 896) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14624) -> [10000 ps] ACT @ (4, 15703) -> [17500 ps] WR @ (4, 888) ->
[10000 ps] WR @ (0, 888) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12465) -> [10000 ps] ACT @ (0, 13545) ->
[17500 ps] WR @ (0, 888) -> [10000 ps] WR @ (4, 888) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11386) -> [17500 ps] WR @ (4, 888) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9228) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10307) -> [17500 ps] WR @ (4, 888) ->
[10000 ps] WR @ (0, 888) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7069) -> [10000 ps] ACT @ (0, 8149) ->
[17500 ps] WR @ (0, 880) -> [10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5990) -> [17500 ps] WR @ (4, 880) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3832) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4911) -> [17500 ps] WR @ (4, 880) ->
[10000 ps] WR @ (0, 880) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1673) -> [10000 ps] ACT @ (0, 2753) ->
[17500 ps] WR @ (0, 880) -> [10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 594) -> [17500 ps] WR @ (4, 880) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14820) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15899) -> [17500 ps] WR @ (4, 872) ->
[10000 ps] WR @ (0, 872) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12661) -> [10000 ps] ACT @ (0, 13741) ->
[17500 ps] WR @ (0, 872) -> [10000 ps] WR @ (4, 872) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11582) -> [17500 ps] WR @ (4, 872) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9424) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10503) -> [17500 ps] WR @ (4, 872) ->
[10000 ps] WR @ (0, 872) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7265) -> [10000 ps] ACT @ (0, 8345) ->
[17500 ps] WR @ (0, 872) -> [10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6186) -> [17500 ps] WR @ (4, 864) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4028) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5107) -> [17500 ps] WR @ (4, 864) ->
[10000 ps] WR @ (0, 864) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1869) -> [10000 ps] ACT @ (0, 2949) ->
[17500 ps] WR @ (0, 864) -> [10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 790) -> [17500 ps] WR @ (4, 864) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15016) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16095) -> [17500 ps] WR @ (4, 856) ->
[10000 ps] WR @ (0, 856) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12857) -> [10000 ps] ACT @ (0, 13937) ->
[17500 ps] WR @ (0, 856) -> [10000 ps] WR @ (4, 856) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10699) ->
[10000 ps] ACT @ (4, 11778) -> [17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9620) ->
[17500 ps] WR @ (0, 856) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7461) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) ->
[17500 ps] WR @ (0, 856) -> [10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5303) ->
[10000 ps] ACT @ (4, 6382) -> [17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 848) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4224) ->
[17500 ps] WR @ (0, 848) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2065) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) ->
[17500 ps] WR @ (0, 848) -> [10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16291) ->
[10000 ps] ACT @ (4, 986) -> [17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 840) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) ->
[17500 ps] WR @ (0, 840) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13053) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) ->
[17500 ps] WR @ (0, 840) -> [10000 ps] WR @ (4, 840) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10895) ->
[10000 ps] ACT @ (4, 11974) -> [17500 ps] WR @ (4, 840) -> [10000 ps] WR @ (0, 840) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) ->
[17500 ps] WR @ (0, 840) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7657) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) ->
[17500 ps] WR @ (0, 840) -> [10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5499) ->
[10000 ps] ACT @ (4, 6578) -> [17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) ->
[17500 ps] WR @ (0, 832) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2261) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) ->
[17500 ps] WR @ (0, 832) -> [10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 103) ->
[10000 ps] ACT @ (4, 1182) -> [17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) ->
[17500 ps] WR @ (0, 824) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13249) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) ->
[17500 ps] WR @ (0, 824) -> [10000 ps] WR @ (4, 824) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11091) ->
[10000 ps] ACT @ (4, 12170) -> [17500 ps] WR @ (4, 824) -> [10000 ps] WR @ (0, 824) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 8932) -> [10000 ps] ACT @ (0, 10012) -> [17500 ps] WR @ (0, 824) -> [10000 ps] WR @ (4, 824) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 7853) -> [17500 ps] WR @ (4, 816) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5695) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 6774) -> [17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 3536) -> [10000 ps] ACT @ (0, 4616) -> [17500 ps] WR @ (0, 816) -> [10000 ps] WR @ (4, 816) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 2457) -> [17500 ps] WR @ (4, 816) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 299) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 1378) -> [17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 14524) -> [10000 ps] ACT @ (0, 15604) -> [17500 ps] WR @ (0, 808) -> [10000 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 13445) -> [17500 ps] WR @ (4, 808) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 12366) -> [17500 ps] WR @ (4, 808) -> [10000 ps] WR @ (0, 808) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 9128) -> [10000 ps] ACT @ (0, 10208) -> [17500 ps] WR @ (0, 808) -> [10000 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 8049) -> [17500 ps] WR @ (4, 800) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5891) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 6970) -> [17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 3732) -> [10000 ps] ACT @ (0, 4812) -> [17500 ps] WR @ (0, 800) -> [10000 ps] WR @ (4, 800) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 2653) -> [17500 ps] WR @ (4, 800) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 1574) -> [17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 14720) -> [10000 ps] ACT @ (0, 15800) -> [17500 ps] WR @ (0, 792) -> [10000 ps] WR @ (4, 792) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 13641) -> [17500 ps] WR @ (4, 792) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11483) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 12562) -> [17500 ps] WR @ (4, 792) -> [10000 ps] WR @ (0, 792) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 9324) -> [10000 ps] ACT @ (0, 10404) -> [17500 ps] WR @ (0, 792) -> [10000 ps] WR @ (4, 792) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7166) -> [10000 ps] ACT @ (4, 8245) -> [17500 ps] WR @ (4, 792) -> [10000 ps] WR @ (0, 784) ->
[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 6087) -> [17500 ps] WR @ (0, 784) ->
[ 2500 ps] ACT @ (4, 3928) -> [42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5008) -> [17500 ps] WR @ (0, 784) -> [10000 ps] WR @ (4, 784) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1770) -> [10000 ps] ACT @ (4, 2849) -> [17500 ps] WR @ (4, 784) ->
[10000 ps] WR @ (0, 784) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 691) -> [17500 ps] WR @ (0, 784) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 14916) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15996) -> [17500 ps] WR @ (0, 776) -> [10000 ps] WR @ (4, 776) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12758) -> [10000 ps] ACT @ (4, 13837) -> [17500 ps] WR @ (4, 776) ->
[10000 ps] WR @ (0, 776) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11679) -> [17500 ps] WR @ (0, 776) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 9520) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10600) -> [17500 ps] WR @ (0, 776) -> [10000 ps] WR @ (4, 776) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7362) -> [10000 ps] ACT @ (4, 8441) -> [17500 ps] WR @ (4, 776) ->
[10000 ps] WR @ (0, 768) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6283) -> [17500 ps] WR @ (0, 768) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 4124) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5204) -> [17500 ps] WR @ (0, 768) -> [10000 ps] WR @ (4, 768) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1966) -> [10000 ps] ACT @ (4, 3045) -> [17500 ps] WR @ (4, 768) ->
[10000 ps] WR @ (0, 768) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 887) -> [17500 ps] WR @ (0, 768) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 15112) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16192) -> [17500 ps] WR @ (0, 760) -> [10000 ps] WR @ (4, 760) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12954) -> [10000 ps] ACT @ (4, 14033) -> [17500 ps] WR @ (4, 760) ->
[10000 ps] WR @ (0, 760) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11875) -> [17500 ps] WR @ (0, 760) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 9716) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10796) -> [17500 ps] WR @ (0, 760) -> [10000 ps] WR @ (4, 760) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7558) -> [10000 ps] ACT @ (4, 8637) -> [17500 ps] WR @ (4, 760) ->
[10000 ps] WR @ (0, 752) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5399) -> [10000 ps] ACT @ (0, 6479) ->
[17500 ps] WR @ (0, 752) -> [10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4320) -> [17500 ps] WR @ (4, 752) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2162) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3241) -> [17500 ps] WR @ (4, 752) ->
[10000 ps] WR @ (0, 752) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3) -> [10000 ps] ACT @ (0, 1083) ->
[17500 ps] WR @ (0, 752) -> [10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15308) -> [17500 ps] WR @ (4, 744) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13150) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14229) -> [17500 ps] WR @ (4, 744) ->
[10000 ps] WR @ (0, 744) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10991) -> [10000 ps] ACT @ (0, 12071) ->
[17500 ps] WR @ (0, 744) -> [10000 ps] WR @ (4, 744) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9912) -> [17500 ps] WR @ (4, 744) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7754) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8833) -> [17500 ps] WR @ (4, 744) ->
[10000 ps] WR @ (0, 736) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5595) -> [10000 ps] ACT @ (0, 6675) ->
[17500 ps] WR @ (0, 736) -> [10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4516) -> [17500 ps] WR @ (4, 736) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2358) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3437) -> [17500 ps] WR @ (4, 736) ->
[10000 ps] WR @ (0, 736) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 199) -> [10000 ps] ACT @ (0, 1279) ->
[17500 ps] WR @ (0, 736) -> [10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15504) -> [17500 ps] WR @ (4, 728) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13346) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14425) -> [17500 ps] WR @ (4, 728) ->
[10000 ps] WR @ (0, 728) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11187) -> [10000 ps] ACT @ (0, 12267) ->
[17500 ps] WR @ (0, 728) -> [10000 ps] WR @ (4, 728) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10108) -> [17500 ps] WR @ (4, 728) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7950) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9029) -> [17500 ps] WR @ (4, 728) ->
[10000 ps] WR @ (0, 720) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5791) -> [10000 ps] ACT @ (0, 6871) ->
[17500 ps] WR @ (0, 720) -> [10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3633) ->
[10000 ps] ACT @ (4, 4712) -> [17500 ps] WR @ (4, 720) -> [10000 ps] WR @ (0, 720) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) ->
[17500 ps] WR @ (0, 720) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 395) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) ->
[17500 ps] WR @ (0, 720) -> [10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14621) ->
[10000 ps] ACT @ (4, 15700) -> [17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) ->
[17500 ps] WR @ (0, 712) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11383) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12463) ->
[17500 ps] WR @ (0, 712) -> [10000 ps] WR @ (4, 712) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9225) ->
[10000 ps] ACT @ (4, 10304) -> [17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) ->
[17500 ps] WR @ (0, 704) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5987) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) ->
[17500 ps] WR @ (0, 704) -> [10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3829) ->
[10000 ps] ACT @ (4, 4908) -> [17500 ps] WR @ (4, 704) -> [10000 ps] WR @ (0, 704) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) ->
[17500 ps] WR @ (0, 704) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 591) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) ->
[17500 ps] WR @ (0, 704) -> [10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14817) ->
[10000 ps] ACT @ (4, 15896) -> [17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) ->
[17500 ps] WR @ (0, 696) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11579) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12659) ->
[17500 ps] WR @ (0, 696) -> [10000 ps] WR @ (4, 696) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9421) ->
[10000 ps] ACT @ (4, 10500) -> [17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) ->
[17500 ps] WR @ (0, 696) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6183) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) ->
[17500 ps] WR @ (0, 688) -> [10000 ps] WR @ (4, 688) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4025) ->
[10000 ps] ACT @ (4, 5104) -> [17500 ps] WR @ (4, 688) -> [10000 ps] WR @ (0, 688) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 1866) -> [10000 ps] ACT @ (0, 2946) -> [17500 ps] WR @ (0, 688) -> [10000 ps] WR @ (4, 688) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 787) -> [17500 ps] WR @ (4, 688) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15013) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 16092) -> [17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 12854) -> [10000 ps] ACT @ (0, 13934) -> [17500 ps] WR @ (0, 680) -> [10000 ps] WR @ (4, 680) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 11775) -> [17500 ps] WR @ (4, 680) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9617) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 10696) -> [17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 7458) -> [10000 ps] ACT @ (0, 8538) -> [17500 ps] WR @ (0, 680) -> [10000 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 6379) -> [17500 ps] WR @ (4, 672) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4221) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 5300) -> [17500 ps] WR @ (4, 672) -> [10000 ps] WR @ (0, 672) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 2062) -> [10000 ps] ACT @ (0, 3142) -> [17500 ps] WR @ (0, 672) -> [10000 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 983) -> [17500 ps] WR @ (4, 672) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15209) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 16288) -> [17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 13050) -> [10000 ps] ACT @ (0, 14130) -> [17500 ps] WR @ (0, 664) -> [10000 ps] WR @ (4, 664) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 11971) -> [17500 ps] WR @ (4, 664) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9813) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 10892) -> [17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 7654) -> [10000 ps] ACT @ (0, 8734) -> [17500 ps] WR @ (0, 664) -> [10000 ps] WR @ (4, 656) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 6575) -> [17500 ps] WR @ (4, 656) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4417) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 5496) -> [17500 ps] WR @ (4, 656) -> [10000 ps] WR @ (0, 656) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 2258) -> [10000 ps] ACT @ (0, 3338) -> [17500 ps] WR @ (0, 656) -> [10000 ps] WR @ (4, 656) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 100) -> [10000 ps] ACT @ (4, 1179) -> [17500 ps] WR @ (4, 656) -> [10000 ps] WR @ (0, 656) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15405) -> [17500 ps] WR @ (0, 648) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14326) -> [17500 ps] WR @ (0, 648) -> [10000 ps] WR @ (4, 648) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11088) -> [10000 ps] ACT @ (4, 12167) -> [17500 ps] WR @ (4, 648) -> [10000 ps] WR @ (0, 648) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10009) -> [17500 ps] WR @ (0, 648) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7850) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8930) -> [17500 ps] WR @ (0, 648) -> [10000 ps] WR @ (4, 640) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5692) -> [10000 ps] ACT @ (4, 6771) -> [17500 ps] WR @ (4, 640) -> [10000 ps] WR @ (0, 640) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4613) -> [17500 ps] WR @ (0, 640) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3534) -> [17500 ps] WR @ (0, 640) -> [10000 ps] WR @ (4, 640) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 296) -> [10000 ps] ACT @ (4, 1375) -> [17500 ps] WR @ (4, 640) -> [10000 ps] WR @ (0, 640) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15601) -> [17500 ps] WR @ (0, 632) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13442) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14522) -> [17500 ps] WR @ (0, 632) -> [10000 ps] WR @ (4, 632) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11284) -> [10000 ps] ACT @ (4, 12363) -> [17500 ps] WR @ (4, 632) -> [10000 ps] WR @ (0, 632) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10205) -> [17500 ps] WR @ (0, 632) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8046) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9126) -> [17500 ps] WR @ (0, 632) -> [10000 ps] WR @ (4, 624) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5888) -> [10000 ps] ACT @ (4, 6967) -> [17500 ps] WR @ (4, 624) -> [10000 ps] WR @ (0, 624) ->
[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 4809) -> [17500 ps] WR @ (0, 624) ->
[ 2500 ps] ACT @ (4, 2650) -> [42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) -> [17500 ps] WR @ (0, 624) -> [10000 ps] WR @ (4, 624) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 492) -> [10000 ps] ACT @ (4, 1571) -> [17500 ps] WR @ (4, 624) ->
[10000 ps] WR @ (0, 624) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14717) -> [10000 ps] ACT @ (0, 15797) ->
[17500 ps] WR @ (0, 616) -> [10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) -> [17500 ps] WR @ (4, 616) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11480) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12559) -> [17500 ps] WR @ (4, 616) ->
[10000 ps] WR @ (0, 616) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9321) -> [10000 ps] ACT @ (0, 10401) ->
[17500 ps] WR @ (0, 616) -> [10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8242) -> [17500 ps] WR @ (4, 616) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6084) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7163) -> [17500 ps] WR @ (4, 608) ->
[10000 ps] WR @ (0, 608) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3925) -> [10000 ps] ACT @ (0, 5005) ->
[17500 ps] WR @ (0, 608) -> [10000 ps] WR @ (4, 608) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) -> [17500 ps] WR @ (4, 608) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 688) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1767) -> [17500 ps] WR @ (4, 608) ->
[10000 ps] WR @ (0, 608) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14913) -> [10000 ps] ACT @ (0, 15993) ->
[17500 ps] WR @ (0, 600) -> [10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13834) -> [17500 ps] WR @ (4, 600) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11676) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12755) -> [17500 ps] WR @ (4, 600) ->
[10000 ps] WR @ (0, 600) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9517) -> [10000 ps] ACT @ (0, 10597) ->
[17500 ps] WR @ (0, 600) -> [10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) -> [17500 ps] WR @ (4, 600) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6280) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7359) -> [17500 ps] WR @ (4, 592) ->
[10000 ps] WR @ (0, 592) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4121) -> [10000 ps] ACT @ (0, 5201) ->
[17500 ps] WR @ (0, 592) -> [10000 ps] WR @ (4, 592) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3042) -> [17500 ps] WR @ (4, 592) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 884) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1963) -> [17500 ps] WR @ (4, 592) ->
[10000 ps] WR @ (0, 592) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15109) -> [10000 ps] ACT @ (0, 16189) ->
[17500 ps] WR @ (0, 584) -> [10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) ->
[10000 ps] ACT @ (4, 14030) -> [17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 584) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) ->
[17500 ps] WR @ (0, 584) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9713) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) ->
[17500 ps] WR @ (0, 584) -> [10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7555) ->
[10000 ps] ACT @ (4, 8634) -> [17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) ->
[17500 ps] WR @ (0, 576) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4317) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) ->
[17500 ps] WR @ (0, 576) -> [10000 ps] WR @ (4, 576) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2159) ->
[10000 ps] ACT @ (4, 3238) -> [17500 ps] WR @ (4, 576) -> [10000 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) ->
[17500 ps] WR @ (0, 576) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15305) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) ->
[17500 ps] WR @ (0, 576) -> [10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13147) ->
[10000 ps] ACT @ (4, 14226) -> [17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 568) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) ->
[17500 ps] WR @ (0, 568) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9909) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) ->
[17500 ps] WR @ (0, 568) -> [10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7751) ->
[10000 ps] ACT @ (4, 8830) -> [17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) ->
[17500 ps] WR @ (0, 560) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4513) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) ->
[17500 ps] WR @ (0, 560) -> [10000 ps] WR @ (4, 560) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2355) ->
[10000 ps] ACT @ (4, 3434) -> [17500 ps] WR @ (4, 560) -> [10000 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) ->
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[17500 ps] WR @ (0, 560) -> [10000 ps] WR @ (4, 552) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13343) ->
[10000 ps] ACT @ (4, 14422) -> [17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 552) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 11184) -> [10000 ps] ACT @ (0, 12264) -> [17500 ps] WR @ (0, 552) -> [10000 ps] WR @ (4, 552) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 10105) -> [17500 ps] WR @ (4, 552) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7947) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 9026) -> [17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 544) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 5788) -> [10000 ps] ACT @ (0, 6868) -> [17500 ps] WR @ (0, 544) -> [10000 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 3630) -> [17500 ps] WR @ (4, 544) -> [10000 ps] WR @ (0, 544) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 392) -> [10000 ps] ACT @ (0, 1472) -> [17500 ps] WR @ (0, 544) -> [10000 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 15697) -> [17500 ps] WR @ (4, 536) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13539) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 14618) -> [17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 536) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 11380) -> [10000 ps] ACT @ (0, 12460) -> [17500 ps] WR @ (0, 536) -> [10000 ps] WR @ (4, 536) -> [45000 ps] PRE @ (4) ->
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[ 7500 ps] ACT @ (4, 5984) -> [10000 ps] ACT @ (0, 7064) -> [17500 ps] WR @ (0, 528) -> [10000 ps] WR @ (4, 528) -> [45000 ps] PRE @ (4) ->
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[17500 ps] ACT @ (4, 3826) -> [17500 ps] WR @ (4, 528) -> [10000 ps] WR @ (0, 528) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 588) -> [10000 ps] ACT @ (0, 1668) -> [17500 ps] WR @ (0, 528) -> [10000 ps] WR @ (4, 528) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 15893) -> [17500 ps] WR @ (4, 520) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13735) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 14814) -> [17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 11576) -> [10000 ps] ACT @ (0, 12656) -> [17500 ps] WR @ (0, 520) -> [10000 ps] WR @ (4, 520) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9418) -> [10000 ps] ACT @ (4, 10497) -> [17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8339) -> [17500 ps] WR @ (0, 520) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7260) -> [17500 ps] WR @ (0, 512) -> [10000 ps] WR @ (4, 512) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4022) -> [10000 ps] ACT @ (4, 5101) -> [17500 ps] WR @ (4, 512) -> [10000 ps] WR @ (0, 512) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2943) -> [17500 ps] WR @ (0, 512) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 784) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1864) -> [17500 ps] WR @ (0, 512) -> [10000 ps] WR @ (4, 512) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15010) -> [10000 ps] ACT @ (4, 16089) -> [17500 ps] WR @ (4, 504) -> [10000 ps] WR @ (0, 504) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13931) -> [17500 ps] WR @ (0, 504) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12852) -> [17500 ps] WR @ (0, 504) -> [10000 ps] WR @ (4, 504) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9614) -> [10000 ps] ACT @ (4, 10693) -> [17500 ps] WR @ (4, 504) -> [10000 ps] WR @ (0, 504) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8535) -> [17500 ps] WR @ (0, 504) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6376) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7456) -> [17500 ps] WR @ (0, 496) -> [10000 ps] WR @ (4, 496) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4218) -> [10000 ps] ACT @ (4, 5297) -> [17500 ps] WR @ (4, 496) -> [10000 ps] WR @ (0, 496) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3139) -> [17500 ps] WR @ (0, 496) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2060) -> [17500 ps] WR @ (0, 496) -> [10000 ps] WR @ (4, 496) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15206) -> [10000 ps] ACT @ (4, 16285) -> [17500 ps] WR @ (4, 488) -> [10000 ps] WR @ (0, 488) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14127) -> [17500 ps] WR @ (0, 488) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11968) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13048) -> [17500 ps] WR @ (0, 488) -> [10000 ps] WR @ (4, 488) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9810) -> [10000 ps] ACT @ (4, 10889) -> [17500 ps] WR @ (4, 488) -> [10000 ps] WR @ (0, 488) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7651) -> [10000 ps] ACT @ (0, 8731) -> [17500 ps] WR @ (0, 488) ->
[10000 ps] WR @ (4, 480) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6572) -> [17500 ps] WR @ (4, 480) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 4414) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5493) -> [17500 ps] WR @ (4, 480) -> [10000 ps] WR @ (0, 480) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2255) -> [10000 ps] ACT @ (0, 3335) -> [17500 ps] WR @ (0, 480) ->
[10000 ps] WR @ (4, 480) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1176) -> [17500 ps] WR @ (4, 480) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 15402) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 97) -> [17500 ps] WR @ (4, 480) -> [10000 ps] WR @ (0, 472) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13243) -> [10000 ps] ACT @ (0, 14323) -> [17500 ps] WR @ (0, 472) ->
[10000 ps] WR @ (4, 472) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12164) -> [17500 ps] WR @ (4, 472) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 10006) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11085) -> [17500 ps] WR @ (4, 472) -> [10000 ps] WR @ (0, 472) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7847) -> [10000 ps] ACT @ (0, 8927) -> [17500 ps] WR @ (0, 472) ->
[10000 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6768) -> [17500 ps] WR @ (4, 464) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 4610) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5689) -> [17500 ps] WR @ (4, 464) -> [10000 ps] WR @ (0, 464) ->
[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 3531) -> [10000 ps] ACT @ (4, 2451) ->
[ 7500 ps] WR @ (0, 464) -> [10000 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1372) -> [17500 ps] WR @ (4, 464) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15598) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 293) -> [17500 ps] WR @ (4, 464) ->
[10000 ps] WR @ (0, 456) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13439) -> [10000 ps] ACT @ (0, 14519) ->
[17500 ps] WR @ (0, 456) -> [10000 ps] WR @ (4, 456) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12360) -> [17500 ps] WR @ (4, 456) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10202) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11281) -> [17500 ps] WR @ (4, 456) ->
[10000 ps] WR @ (0, 456) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8043) -> [10000 ps] ACT @ (0, 9123) ->
[17500 ps] WR @ (0, 456) -> [10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5885) ->
[10000 ps] ACT @ (4, 6964) -> [17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) ->
[17500 ps] WR @ (0, 448) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2647) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3727) ->
[17500 ps] WR @ (0, 448) -> [10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 489) ->
[10000 ps] ACT @ (4, 1568) -> [17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15794) ->
[17500 ps] WR @ (0, 440) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14715) ->
[17500 ps] WR @ (0, 440) -> [10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11477) ->
[10000 ps] ACT @ (4, 12556) -> [17500 ps] WR @ (4, 440) -> [10000 ps] WR @ (0, 440) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) ->
[17500 ps] WR @ (0, 440) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8239) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9319) ->
[17500 ps] WR @ (0, 440) -> [10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6081) ->
[10000 ps] ACT @ (4, 7160) -> [17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5002) ->
[17500 ps] WR @ (0, 432) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3923) ->
[17500 ps] WR @ (0, 432) -> [10000 ps] WR @ (4, 432) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 685) ->
[10000 ps] ACT @ (4, 1764) -> [17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) ->
[17500 ps] WR @ (0, 424) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13831) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14911) ->
[17500 ps] WR @ (0, 424) -> [10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11673) ->
[10000 ps] ACT @ (4, 12752) -> [17500 ps] WR @ (4, 424) -> [10000 ps] WR @ (0, 424) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10594) ->
[17500 ps] WR @ (0, 424) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9515) ->
[17500 ps] WR @ (0, 424) -> [10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6277) ->
[10000 ps] ACT @ (4, 7356) -> [17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 4118) -> [10000 ps] ACT @ (0, 5198) -> [17500 ps] WR @ (0, 416) -> [10000 ps] WR @ (4, 416) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 3039) -> [17500 ps] WR @ (4, 416) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 881) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 1960) -> [17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 15106) -> [10000 ps] ACT @ (0, 16186) -> [17500 ps] WR @ (0, 408) -> [10000 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 14027) -> [17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11869) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 12948) -> [17500 ps] WR @ (4, 408) -> [10000 ps] WR @ (0, 408) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 9710) -> [10000 ps] ACT @ (0, 10790) -> [17500 ps] WR @ (0, 408) -> [10000 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 8631) -> [17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6473) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 7552) -> [17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 4314) -> [10000 ps] ACT @ (0, 5394) -> [17500 ps] WR @ (0, 400) -> [10000 ps] WR @ (4, 400) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 3235) -> [17500 ps] WR @ (4, 400) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1077) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 2156) -> [17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 15302) -> [10000 ps] ACT @ (0, 16382) -> [17500 ps] WR @ (0, 392) -> [10000 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 14223) -> [17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12065) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 13144) -> [17500 ps] WR @ (4, 392) -> [10000 ps] WR @ (0, 392) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 9906) -> [10000 ps] ACT @ (0, 10986) -> [17500 ps] WR @ (0, 392) -> [10000 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 8827) -> [17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6669) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 7748) -> [17500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 4510) -> [10000 ps] ACT @ (0, 5590) -> [17500 ps] WR @ (0, 384) -> [10000 ps] WR @ (4, 384) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2352) -> [10000 ps] ACT @ (4, 3431) -> [17500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1273) -> [17500 ps] WR @ (0, 384) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 194) -> [17500 ps] WR @ (0, 384) -> [10000 ps] WR @ (4, 376) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13340) -> [10000 ps] ACT @ (4, 14419) -> [17500 ps] WR @ (4, 376) -> [10000 ps] WR @ (0, 376) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12261) -> [17500 ps] WR @ (0, 376) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10102) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11182) -> [17500 ps] WR @ (0, 376) -> [10000 ps] WR @ (4, 376) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7944) -> [10000 ps] ACT @ (4, 9023) -> [17500 ps] WR @ (4, 376) -> [10000 ps] WR @ (0, 368) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6865) -> [17500 ps] WR @ (0, 368) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5786) -> [17500 ps] WR @ (0, 368) -> [10000 ps] WR @ (4, 368) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2548) -> [10000 ps] ACT @ (4, 3627) -> [17500 ps] WR @ (4, 368) -> [10000 ps] WR @ (0, 368) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1469) -> [17500 ps] WR @ (0, 368) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15694) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 390) -> [17500 ps] WR @ (0, 368) -> [10000 ps] WR @ (4, 360) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13536) -> [10000 ps] ACT @ (4, 14615) -> [17500 ps] WR @ (4, 360) -> [10000 ps] WR @ (0, 360) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12457) -> [17500 ps] WR @ (0, 360) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11378) -> [17500 ps] WR @ (0, 360) -> [10000 ps] WR @ (4, 360) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8140) -> [10000 ps] ACT @ (4, 9219) -> [17500 ps] WR @ (4, 360) -> [10000 ps] WR @ (0, 352) ->
[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7061) -> [17500 ps] WR @ (0, 352) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4902) ->
[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5982) -> [17500 ps] WR @ (0, 352) -> [10000 ps] WR @ (4, 352) -> [35000 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2744) -> [10000 ps] ACT @ (4, 3823) -> [17500 ps] WR @ (4, 352) -> [10000 ps] WR @ (0, 352) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 585) -> [10000 ps] ACT @ (0, 1665) -> [17500 ps] WR @ (0, 352) ->
[10000 ps] WR @ (4, 352) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15890) -> [17500 ps] WR @ (4, 344) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 13732) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14811) -> [17500 ps] WR @ (4, 344) -> [10000 ps] WR @ (0, 344) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11573) -> [10000 ps] ACT @ (0, 12653) -> [17500 ps] WR @ (0, 344) ->
[10000 ps] WR @ (4, 344) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10494) -> [17500 ps] WR @ (4, 344) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 8336) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9415) -> [17500 ps] WR @ (4, 344) -> [10000 ps] WR @ (0, 344) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6177) -> [10000 ps] ACT @ (0, 7257) -> [17500 ps] WR @ (0, 336) ->
[10000 ps] WR @ (4, 336) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5098) -> [17500 ps] WR @ (4, 336) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 2940) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4019) -> [17500 ps] WR @ (4, 336) -> [10000 ps] WR @ (0, 336) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 781) -> [10000 ps] ACT @ (0, 1861) -> [17500 ps] WR @ (0, 336) ->
[10000 ps] WR @ (4, 336) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16086) -> [17500 ps] WR @ (4, 328) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 13928) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15007) -> [17500 ps] WR @ (4, 328) -> [10000 ps] WR @ (0, 328) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11769) -> [10000 ps] ACT @ (0, 12849) -> [17500 ps] WR @ (0, 328) ->
[10000 ps] WR @ (4, 328) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10690) -> [17500 ps] WR @ (4, 328) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 8532) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9611) -> [17500 ps] WR @ (4, 328) -> [10000 ps] WR @ (0, 328) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6373) -> [10000 ps] ACT @ (0, 7453) -> [17500 ps] WR @ (0, 320) ->
[10000 ps] WR @ (4, 320) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5294) -> [17500 ps] WR @ (4, 320) -> [ 5000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 3136) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4215) -> [17500 ps] WR @ (4, 320) -> [10000 ps] WR @ (0, 320) ->
[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 977) -> [10000 ps] ACT @ (0, 2057) -> [17500 ps] WR @ (0, 320) ->
[10000 ps] WR @ (4, 320) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15203) -> [10000 ps] ACT @ (4, 16282) ->
[17500 ps] WR @ (4, 312) -> [10000 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) -> [17500 ps] WR @ (0, 312) ->
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11965) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13045) -> [17500 ps] WR @ (0, 312) ->
[10000 ps] WR @ (4, 312) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9807) -> [10000 ps] ACT @ (4, 10886) ->
[17500 ps] WR @ (4, 312) -> [10000 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> [17500 ps] WR @ (0, 312) ->
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6569) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) -> [17500 ps] WR @ (0, 304) ->
[10000 ps] WR @ (4, 304) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4411) -> [10000 ps] ACT @ (4, 5490) ->
[17500 ps] WR @ (4, 304) -> [10000 ps] WR @ (0, 304) -> [35000 ps] NOP -> [10000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) ->
[17500 ps] WR @ (0, 304) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [17500 ps] WR @ (0, 304) -> [65000 ps] PRE @ (0) ->
[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 1173) -> [17500 ps] WR @ (4, 304) -> [ 2500 ps] ACT @ (0, 15399) ->
[42500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 94) -> [17500 ps] WR @ (4, 304) -> [10000 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 14320) -> [17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12161) -> [22500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 13241) -> [17500 ps] WR @ (0, 296) -> [10000 ps] WR @ (4, 296) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 10003) -> [10000 ps] ACT @ (4, 11082) -> [17500 ps] WR @ (4, 296) -> [10000 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 8924) -> [17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6765) -> [22500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 7845) -> [17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 4607) -> [10000 ps] ACT @ (4, 5686) -> [17500 ps] WR @ (4, 288) -> [10000 ps] WR @ (0, 288) -> [45000 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 3528) -> [17500 ps] WR @ (0, 288) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1369) -> [22500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 2449) -> [17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 15595) -> [10000 ps] ACT @ (4, 290) -> [17500 ps] WR @ (4, 288) -> [10000 ps] WR @ (0, 280) -> [35000 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13436) -> [10000 ps] ACT @ (0, 14516) -> [17500 ps] WR @ (0, 280) -> [10000 ps] WR @ (4, 280) ->
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12357) -> [17500 ps] WR @ (4, 280) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10199) ->
[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11278) -> [17500 ps] WR @ (4, 280) -> [10000 ps] WR @ (0, 280) -> [35000 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8040) -> [10000 ps] ACT @ (0, 9120) -> [17500 ps] WR @ (0, 280) -> [10000 ps] WR @ (4, 272) ->
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6961) -> [17500 ps] WR @ (4, 272) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4803) ->
[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5882) -> [17500 ps] WR @ (4, 272) -> [10000 ps] WR @ (0, 272) -> [35000 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2644) -> [10000 ps] ACT @ (0, 3724) -> [17500 ps] WR @ (0, 272) -> [10000 ps] WR @ (4, 272) ->
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1565) -> [17500 ps] WR @ (4, 272) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15791) ->
[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 486) -> [17500 ps] WR @ (4, 272) -> [10000 ps] WR @ (0, 264) -> [35000 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13632) -> [10000 ps] ACT @ (0, 14712) -> [17500 ps] WR @ (0, 264) -> [10000 ps] WR @ (4, 264) ->
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12553) -> [17500 ps] WR @ (4, 264) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10395) ->
[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11474) -> [17500 ps] WR @ (4, 264) -> [10000 ps] WR @ (0, 264) -> [35000 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8236) -> [10000 ps] ACT @ (0, 9316) -> [17500 ps] WR @ (0, 264) -> [10000 ps] WR @ (4, 264) ->
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7157) -> [17500 ps] WR @ (4, 256) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4999) ->
[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6078) -> [17500 ps] WR @ (4, 256) -> [10000 ps] WR @ (0, 256) -> [35000 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2840) -> [10000 ps] ACT @ (0, 3920) -> [17500 ps] WR @ (0, 256) -> [10000 ps] WR @ (4, 256) ->
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1761) -> [17500 ps] WR @ (4, 256) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15987) ->
[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 682) -> [17500 ps] WR @ (4, 256) -> [10000 ps] WR @ (0, 248) -> [35000 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13828) -> [10000 ps] ACT @ (0, 14908) -> [17500 ps] WR @ (0, 248) -> [10000 ps] WR @ (4, 248) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) -> [10000 ps] ACT @ (4, 12749) -> [17500 ps] WR @ (4, 248) ->
[10000 ps] WR @ (0, 248) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) -> [17500 ps] WR @ (0, 248) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 8432) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9512) -> [17500 ps] WR @ (0, 248) -> [10000 ps] WR @ (4, 248) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6274) -> [10000 ps] ACT @ (4, 7353) -> [17500 ps] WR @ (4, 240) ->
[10000 ps] WR @ (0, 240) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) -> [17500 ps] WR @ (0, 240) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 3036) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) -> [17500 ps] WR @ (0, 240) -> [10000 ps] WR @ (4, 240) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 878) -> [10000 ps] ACT @ (4, 1957) -> [17500 ps] WR @ (4, 240) ->
[10000 ps] WR @ (0, 240) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) -> [17500 ps] WR @ (0, 232) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 14024) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) -> [17500 ps] WR @ (0, 232) -> [10000 ps] WR @ (4, 232) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11866) -> [10000 ps] ACT @ (4, 12945) -> [17500 ps] WR @ (4, 232) ->
[10000 ps] WR @ (0, 232) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) -> [17500 ps] WR @ (0, 232) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 8628) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) -> [17500 ps] WR @ (0, 232) -> [10000 ps] WR @ (4, 232) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6470) -> [10000 ps] ACT @ (4, 7549) -> [17500 ps] WR @ (4, 224) ->
[10000 ps] WR @ (0, 224) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) -> [17500 ps] WR @ (0, 224) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 3232) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) -> [17500 ps] WR @ (0, 224) -> [10000 ps] WR @ (4, 224) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1074) -> [10000 ps] ACT @ (4, 2153) -> [17500 ps] WR @ (4, 224) ->
[10000 ps] WR @ (0, 224) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) -> [17500 ps] WR @ (0, 216) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 14220) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) -> [17500 ps] WR @ (0, 216) -> [10000 ps] WR @ (4, 216) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12062) -> [10000 ps] ACT @ (4, 13141) -> [17500 ps] WR @ (4, 216) ->
[10000 ps] WR @ (0, 216) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9903) -> [10000 ps] ACT @ (0, 10983) ->
[17500 ps] WR @ (0, 216) -> [10000 ps] WR @ (4, 216) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8824) -> [17500 ps] WR @ (4, 216) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6666) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7745) -> [17500 ps] WR @ (4, 208) ->
[10000 ps] WR @ (0, 208) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4507) -> [10000 ps] ACT @ (0, 5587) ->
[17500 ps] WR @ (0, 208) -> [10000 ps] WR @ (4, 208) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3428) -> [17500 ps] WR @ (4, 208) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1270) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2349) -> [17500 ps] WR @ (4, 208) ->
[10000 ps] WR @ (0, 208) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15495) -> [10000 ps] ACT @ (0, 191) ->
[17500 ps] WR @ (0, 208) -> [10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14416) -> [17500 ps] WR @ (4, 200) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12258) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13337) -> [17500 ps] WR @ (4, 200) ->
[10000 ps] WR @ (0, 200) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10099) -> [10000 ps] ACT @ (0, 11179) ->
[17500 ps] WR @ (0, 200) -> [10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9020) -> [17500 ps] WR @ (4, 200) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6862) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7941) -> [17500 ps] WR @ (4, 192) ->
[10000 ps] WR @ (0, 192) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4703) -> [10000 ps] ACT @ (0, 5783) ->
[17500 ps] WR @ (0, 192) -> [10000 ps] WR @ (4, 192) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3624) -> [17500 ps] WR @ (4, 192) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1466) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2545) -> [17500 ps] WR @ (4, 192) ->
[10000 ps] WR @ (0, 192) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15691) -> [10000 ps] ACT @ (0, 387) ->
[17500 ps] WR @ (0, 192) -> [10000 ps] WR @ (4, 184) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14612) -> [17500 ps] WR @ (4, 184) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12454) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13533) -> [17500 ps] WR @ (4, 184) ->
[10000 ps] WR @ (0, 184) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10295) -> [10000 ps] ACT @ (0, 11375) ->
[17500 ps] WR @ (0, 184) -> [10000 ps] WR @ (4, 184) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8137) ->
[10000 ps] ACT @ (4, 9216) -> [17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7058) ->
[17500 ps] WR @ (0, 176) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4899) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) ->
[17500 ps] WR @ (0, 176) -> [10000 ps] WR @ (4, 176) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2741) ->
[10000 ps] ACT @ (4, 3820) -> [17500 ps] WR @ (4, 176) -> [10000 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1662) ->
[17500 ps] WR @ (0, 176) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15887) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 583) ->
[17500 ps] WR @ (0, 176) -> [10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13729) ->
[10000 ps] ACT @ (4, 14808) -> [17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) ->
[17500 ps] WR @ (0, 168) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10491) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) ->
[17500 ps] WR @ (0, 168) -> [10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8333) ->
[10000 ps] ACT @ (4, 9412) -> [17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7254) ->
[17500 ps] WR @ (0, 160) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5095) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6175) ->
[17500 ps] WR @ (0, 160) -> [10000 ps] WR @ (4, 160) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2937) ->
[10000 ps] ACT @ (4, 4016) -> [17500 ps] WR @ (4, 160) -> [10000 ps] WR @ (0, 160) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) ->
[17500 ps] WR @ (0, 160) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16083) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) ->
[17500 ps] WR @ (0, 160) -> [10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13925) ->
[10000 ps] ACT @ (4, 15004) -> [17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12846) ->
[17500 ps] WR @ (0, 152) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10687) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11767) ->
[17500 ps] WR @ (0, 152) -> [10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8529) ->
[10000 ps] ACT @ (4, 9608) -> [17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 6370) -> [10000 ps] ACT @ (0, 7450) -> [17500 ps] WR @ (0, 144) -> [10000 ps] WR @ (4, 144) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 5291) -> [17500 ps] WR @ (4, 144) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 4212) -> [17500 ps] WR @ (4, 144) -> [10000 ps] WR @ (0, 144) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 974) -> [10000 ps] ACT @ (0, 2054) -> [17500 ps] WR @ (0, 144) -> [10000 ps] WR @ (4, 144) -> [65000 ps] PRE @ (0) ->
[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 16279) -> [17500 ps] WR @ (4, 136) -> [ 2500 ps] ACT @ (0, 14121) ->
[42500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15200) -> [17500 ps] WR @ (4, 136) -> [10000 ps] WR @ (0, 136) -> [35000 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11962) -> [10000 ps] ACT @ (0, 13042) -> [17500 ps] WR @ (0, 136) -> [10000 ps] WR @ (4, 136) ->
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10883) -> [17500 ps] WR @ (4, 136) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) ->
[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9804) -> [17500 ps] WR @ (4, 136) -> [10000 ps] WR @ (0, 136) -> [35000 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6566) -> [10000 ps] ACT @ (0, 7646) -> [17500 ps] WR @ (0, 128) -> [10000 ps] WR @ (4, 128) ->
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5487) -> [17500 ps] WR @ (4, 128) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) ->
[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4408) -> [17500 ps] WR @ (4, 128) -> [10000 ps] WR @ (0, 128) -> [35000 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1170) -> [10000 ps] ACT @ (0, 2250) -> [17500 ps] WR @ (0, 128) -> [10000 ps] WR @ (4, 128) ->
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 91) -> [17500 ps] WR @ (4, 128) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) ->
[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15396) -> [17500 ps] WR @ (4, 120) -> [10000 ps] WR @ (0, 120) -> [35000 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12158) -> [10000 ps] ACT @ (0, 13238) -> [17500 ps] WR @ (0, 120) -> [10000 ps] WR @ (4, 120) ->
[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11079) -> [17500 ps] WR @ (4, 120) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) ->
[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10000) -> [17500 ps] WR @ (4, 120) -> [10000 ps] WR @ (0, 120) -> [35000 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6762) -> [10000 ps] ACT @ (0, 7842) -> [17500 ps] WR @ (0, 112) -> [10000 ps] WR @ (4, 112) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) -> [10000 ps] ACT @ (4, 5683) -> [17500 ps] WR @ (4, 112) ->
[10000 ps] WR @ (0, 112) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) -> [17500 ps] WR @ (0, 112) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 1366) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2446) -> [17500 ps] WR @ (0, 112) -> [10000 ps] WR @ (4, 112) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15592) -> [10000 ps] ACT @ (4, 287) -> [17500 ps] WR @ (4, 112) ->
[10000 ps] WR @ (0, 104) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) -> [17500 ps] WR @ (0, 104) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 12354) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) -> [17500 ps] WR @ (0, 104) -> [10000 ps] WR @ (4, 104) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10196) -> [10000 ps] ACT @ (4, 11275) -> [17500 ps] WR @ (4, 104) ->
[10000 ps] WR @ (0, 104) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) -> [17500 ps] WR @ (0, 104) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 6958) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) -> [17500 ps] WR @ (0, 96) -> [10000 ps] WR @ (4, 96) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4800) -> [10000 ps] ACT @ (4, 5879) -> [17500 ps] WR @ (4, 96) ->
[10000 ps] WR @ (0, 96) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) -> [17500 ps] WR @ (0, 96) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 1562) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) -> [17500 ps] WR @ (0, 96) -> [10000 ps] WR @ (4, 96) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15788) -> [10000 ps] ACT @ (4, 483) -> [17500 ps] WR @ (4, 96) ->
[10000 ps] WR @ (0, 88) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) -> [17500 ps] WR @ (0, 88) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 12550) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) -> [17500 ps] WR @ (0, 88) -> [10000 ps] WR @ (4, 88) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10392) -> [10000 ps] ACT @ (4, 11471) -> [17500 ps] WR @ (4, 88) ->
[10000 ps] WR @ (0, 88) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) -> [17500 ps] WR @ (0, 88) -> [ 5000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 7154) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) -> [17500 ps] WR @ (0, 88) -> [10000 ps] WR @ (4, 80) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4996) -> [10000 ps] ACT @ (4, 6075) -> [17500 ps] WR @ (4, 80) ->
[10000 ps] WR @ (0, 80) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2837) -> [10000 ps] ACT @ (0, 3917) ->
[17500 ps] WR @ (0, 80) -> [10000 ps] WR @ (4, 80) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1758) -> [17500 ps] WR @ (4, 80) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15984) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 679) -> [17500 ps] WR @ (4, 80) ->
[10000 ps] WR @ (0, 72) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13825) -> [10000 ps] ACT @ (0, 14905) ->
[17500 ps] WR @ (0, 72) -> [10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12746) -> [17500 ps] WR @ (4, 72) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10588) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11667) -> [17500 ps] WR @ (4, 72) ->
[10000 ps] WR @ (0, 72) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8429) -> [10000 ps] ACT @ (0, 9509) ->
[17500 ps] WR @ (0, 72) -> [10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7350) -> [17500 ps] WR @ (4, 64) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5192) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6271) -> [17500 ps] WR @ (4, 64) ->
[10000 ps] WR @ (0, 64) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3033) -> [10000 ps] ACT @ (0, 4113) ->
[17500 ps] WR @ (0, 64) -> [10000 ps] WR @ (4, 64) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1954) -> [17500 ps] WR @ (4, 64) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16180) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 875) -> [17500 ps] WR @ (4, 64) ->
[10000 ps] WR @ (0, 56) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14021) -> [10000 ps] ACT @ (0, 15101) ->
[17500 ps] WR @ (0, 56) -> [10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12942) -> [17500 ps] WR @ (4, 56) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10784) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11863) -> [17500 ps] WR @ (4, 56) ->
[10000 ps] WR @ (0, 56) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8625) -> [10000 ps] ACT @ (0, 9705) ->
[17500 ps] WR @ (0, 56) -> [10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7546) -> [17500 ps] WR @ (4, 48) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5388) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6467) -> [17500 ps] WR @ (4, 48) ->
[10000 ps] WR @ (0, 48) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3229) -> [10000 ps] ACT @ (0, 4309) ->
[17500 ps] WR @ (0, 48) -> [10000 ps] WR @ (4, 48) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1071) ->
[10000 ps] ACT @ (4, 2150) -> [17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) ->
[17500 ps] WR @ (0, 40) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) ->
[17500 ps] WR @ (0, 40) -> [10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12059) ->
[10000 ps] ACT @ (4, 13138) -> [17500 ps] WR @ (4, 40) -> [10000 ps] WR @ (0, 40) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10980) ->
[17500 ps] WR @ (0, 40) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9901) ->
[17500 ps] WR @ (0, 40) -> [10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6663) ->
[10000 ps] ACT @ (4, 7742) -> [17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) ->
[17500 ps] WR @ (0, 32) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) ->
[17500 ps] WR @ (0, 32) -> [10000 ps] WR @ (4, 32) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1267) ->
[10000 ps] ACT @ (4, 2346) -> [17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 188) ->
[17500 ps] WR @ (0, 32) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15493) ->
[17500 ps] WR @ (0, 24) -> [10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12255) ->
[10000 ps] ACT @ (4, 13334) -> [17500 ps] WR @ (4, 24) -> [10000 ps] WR @ (0, 24) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) ->
[17500 ps] WR @ (0, 24) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) ->
[17500 ps] WR @ (0, 24) -> [10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6859) ->
[10000 ps] ACT @ (4, 7938) -> [17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5780) ->
[17500 ps] WR @ (0, 16) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4701) ->
[17500 ps] WR @ (0, 16) -> [10000 ps] WR @ (4, 16) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1463) ->
[10000 ps] ACT @ (4, 2542) -> [17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 15688) -> [10000 ps] ACT @ (0, 384) -> [17500 ps] WR @ (0, 16) -> [10000 ps] WR @ (4, 8) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 14609) -> [17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12451) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 13530) -> [17500 ps] WR @ (4, 8) -> [10000 ps] WR @ (0, 8) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 10292) -> [10000 ps] ACT @ (0, 11372) -> [17500 ps] WR @ (0, 8) -> [10000 ps] WR @ (4, 8) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 9213) -> [17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7055) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 8134) -> [17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 4896) -> [10000 ps] ACT @ (0, 5976) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (4, 0) -> [45000 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 3817) -> [17500 ps] WR @ (4, 0) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1659) -> [22500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 2738) -> [17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 580) ->
[17500 ps] WR @ (0, 0) -> [ 2500 ps] ACT @ (7, 15884) -> [17500 ps] WR @ (7, 1016) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13727) ->
[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14805) -> [17500 ps] WR @ (7, 1016) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) ->
[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13726) -> [17500 ps] WR @ (7, 1016) -> [ 2500 ps] ACT @ (3, 12647) -> [ 2500 ps] PRE @ (4) ->
[15000 ps] WR @ (3, 1016) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10489) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) ->
[17500 ps] WR @ (3, 1016) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10488) -> [10000 ps] ACT @ (0, 9410) ->
[ 7500 ps] WR @ (7, 1016) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (0, 8331) -> [10000 ps] ACT @ (7, 9409) ->
[17500 ps] WR @ (7, 1016) -> [ 2500 ps] ACT @ (4, 7251) -> [42500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8330) -> [17500 ps] WR @ (7, 1016) ->
[ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7251) -> [10000 ps] ACT @ (4, 6172) -> [ 7500 ps] WR @ (3, 1008) ->
[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5093) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6172) -> [17500 ps] WR @ (3, 1008) ->
[ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5092) -> [10000 ps] ACT @ (0, 4014) -> [ 7500 ps] WR @ (7, 1008) ->
[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (0, 2935) -> [10000 ps] ACT @ (7, 4013) -> [17500 ps] WR @ (7, 1008) ->
[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1855) -> [ 2500 ps] NOP -> [20000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2934) ->
[17500 ps] WR @ (7, 1008) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1855) -> [17500 ps] WR @ (3, 1008) -> [65000 ps] PRE @ (0) ->
[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 776) -> [10000 ps] ACT @ (3, 776) -> [10000 ps] ACT @ (0, 16081) ->
[ 7500 ps] WR @ (3, 1008) -> [ 2500 ps] ACT @ (7, 16080) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13922) ->
[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15001) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (3, 13922) -> [10000 ps] ACT @ (4, 12843) -> [ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) ->
[ 7500 ps] ACT @ (4, 11764) -> [10000 ps] ACT @ (3, 12843) -> [17500 ps] WR @ (3, 1000) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10685) ->
[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11764) -> [17500 ps] WR @ (3, 1000) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (7, 10684) -> [10000 ps] ACT @ (0, 9606) -> [ 7500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8526) ->
[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9605) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (3, 8526) -> [10000 ps] ACT @ (4, 7447) -> [ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) ->
[ 7500 ps] ACT @ (4, 6368) -> [10000 ps] ACT @ (3, 7447) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5289) ->
[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6368) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (7, 5288) -> [10000 ps] ACT @ (0, 4210) -> [ 7500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3130) ->
[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4209) -> [17500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (3, 3130) -> [10000 ps] ACT @ (4, 2051) -> [ 7500 ps] WR @ (3, 992) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) ->
[ 7500 ps] ACT @ (4, 972) -> [10000 ps] ACT @ (3, 2051) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16277) ->
[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 972) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (7, 16276) -> [10000 ps] ACT @ (0, 15198) -> [ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14118) ->
[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15197) -> [17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (3, 14118) -> [10000 ps] ACT @ (4, 13039) -> [ 7500 ps] WR @ (3, 984) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) ->
[ 7500 ps] ACT @ (4, 11960) -> [10000 ps] ACT @ (3, 13039) -> [17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10881) ->
[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11960) -> [17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (7, 10880) -> [10000 ps] ACT @ (0, 9802) -> [ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8722) ->
[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9801) -> [17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8722) ->
[17500 ps] WR @ (3, 984) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> [17500 ps] WR @ (3, 976) -> [ 5000 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 5484) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> [17500 ps] WR @ (3, 976) -> [10000 ps] WR @ (7, 976) ->
[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3326) -> [10000 ps] ACT @ (7, 4405) -> [17500 ps] WR @ (7, 976) ->
[10000 ps] WR @ (3, 976) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> [17500 ps] WR @ (3, 976) -> [ 5000 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 88) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> [17500 ps] WR @ (3, 976) -> [10000 ps] WR @ (7, 976) ->
[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14314) -> [10000 ps] ACT @ (7, 15393) -> [17500 ps] WR @ (7, 968) ->
[10000 ps] WR @ (3, 968) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12155) -> [10000 ps] ACT @ (3, 13235) ->
[17500 ps] WR @ (3, 968) -> [10000 ps] WR @ (7, 968) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11076) -> [17500 ps] WR @ (7, 968) ->
[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8918) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9997) -> [17500 ps] WR @ (7, 968) ->
[10000 ps] WR @ (3, 968) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6759) -> [10000 ps] ACT @ (3, 7839) ->
[17500 ps] WR @ (3, 960) -> [10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5680) -> [17500 ps] WR @ (7, 960) ->
[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3522) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4601) -> [17500 ps] WR @ (7, 960) ->
[10000 ps] WR @ (3, 960) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1363) -> [10000 ps] ACT @ (3, 2443) ->
[17500 ps] WR @ (3, 960) -> [10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 284) -> [17500 ps] WR @ (7, 960) ->
[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14510) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15589) -> [17500 ps] WR @ (7, 952) ->
[10000 ps] WR @ (3, 952) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12351) -> [10000 ps] ACT @ (3, 13431) ->
[17500 ps] WR @ (3, 952) -> [10000 ps] WR @ (7, 952) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11272) -> [17500 ps] WR @ (7, 952) ->
[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9114) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10193) -> [17500 ps] WR @ (7, 952) ->
[10000 ps] WR @ (3, 952) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6955) -> [10000 ps] ACT @ (3, 8035) ->
[17500 ps] WR @ (3, 944) -> [10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5876) -> [17500 ps] WR @ (7, 944) ->
[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3718) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4797) -> [17500 ps] WR @ (7, 944) ->
[10000 ps] WR @ (3, 944) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1559) -> [10000 ps] ACT @ (3, 2639) ->
[17500 ps] WR @ (3, 944) -> [10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 480) -> [17500 ps] WR @ (7, 944) ->
[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14706) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15785) -> [17500 ps] WR @ (7, 936) ->
[10000 ps] WR @ (3, 936) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12547) -> [10000 ps] ACT @ (3, 13627) ->
[17500 ps] WR @ (3, 936) -> [10000 ps] WR @ (7, 936) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10389) ->
[10000 ps] ACT @ (7, 11468) -> [17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9310) ->
[17500 ps] WR @ (3, 936) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8231) ->
[17500 ps] WR @ (3, 936) -> [10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4993) ->
[10000 ps] ACT @ (7, 6072) -> [17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 928) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3914) ->
[17500 ps] WR @ (3, 928) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2835) ->
[17500 ps] WR @ (3, 928) -> [10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15981) ->
[10000 ps] ACT @ (7, 676) -> [17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14902) ->
[17500 ps] WR @ (3, 920) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13823) ->
[17500 ps] WR @ (3, 920) -> [10000 ps] WR @ (7, 920) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10585) ->
[10000 ps] ACT @ (7, 11664) -> [17500 ps] WR @ (7, 920) -> [10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9506) ->
[17500 ps] WR @ (3, 920) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8427) ->
[17500 ps] WR @ (3, 920) -> [10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 5189) ->
[10000 ps] ACT @ (7, 6268) -> [17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 912) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4110) ->
[17500 ps] WR @ (3, 912) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3031) ->
[17500 ps] WR @ (3, 912) -> [10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 16177) ->
[10000 ps] ACT @ (7, 872) -> [17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 904) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15098) ->
[17500 ps] WR @ (3, 904) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14019) ->
[17500 ps] WR @ (3, 904) -> [10000 ps] WR @ (7, 904) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10781) ->
[10000 ps] ACT @ (7, 11860) -> [17500 ps] WR @ (7, 904) -> [10000 ps] WR @ (3, 904) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
[ 7500 ps] ACT @ (7, 8622) -> [10000 ps] ACT @ (3, 9702) -> [17500 ps] WR @ (3, 904) -> [10000 ps] WR @ (7, 904) -> [45000 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 7543) -> [17500 ps] WR @ (7, 896) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) -> [22500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 6464) -> [17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 896) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
[ 7500 ps] ACT @ (7, 3226) -> [10000 ps] ACT @ (3, 4306) -> [17500 ps] WR @ (3, 896) -> [10000 ps] WR @ (7, 896) -> [45000 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 2147) -> [17500 ps] WR @ (7, 896) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16373) -> [22500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 1068) -> [17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
[ 7500 ps] ACT @ (7, 14214) -> [10000 ps] ACT @ (3, 15294) -> [17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 13135) -> [17500 ps] WR @ (7, 888) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) -> [22500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 12056) -> [17500 ps] WR @ (7, 888) -> [10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
[ 7500 ps] ACT @ (7, 8818) -> [10000 ps] ACT @ (3, 9898) -> [17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 7739) -> [17500 ps] WR @ (7, 880) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5581) -> [22500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 6660) -> [17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
[ 7500 ps] ACT @ (7, 3422) -> [10000 ps] ACT @ (3, 4502) -> [17500 ps] WR @ (3, 880) -> [10000 ps] WR @ (7, 880) -> [45000 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 2343) -> [17500 ps] WR @ (7, 880) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) -> [22500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 1264) -> [17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
[ 7500 ps] ACT @ (7, 14410) -> [10000 ps] ACT @ (3, 15490) -> [17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) -> [45000 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 13331) -> [17500 ps] WR @ (7, 872) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11173) -> [22500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 12252) -> [17500 ps] WR @ (7, 872) -> [10000 ps] WR @ (3, 872) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
[ 7500 ps] ACT @ (7, 9014) -> [10000 ps] ACT @ (3, 10094) -> [17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) -> [35000 ps] PRE @ (3) ->
[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) -> [17500 ps] WR @ (7, 864) -> [10000 ps] WR @ (3, 864) ->
[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5777) -> [17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3618) ->
[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4698) -> [17500 ps] WR @ (3, 864) -> [10000 ps] WR @ (7, 864) -> [35000 ps] PRE @ (3) ->
[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 1460) -> [10000 ps] ACT @ (7, 2539) -> [17500 ps] WR @ (7, 864) -> [10000 ps] WR @ (3, 864) ->
[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 381) -> [17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14606) ->
[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15686) -> [17500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) -> [35000 ps] PRE @ (3) ->
[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 12448) -> [10000 ps] ACT @ (7, 13527) -> [17500 ps] WR @ (7, 856) -> [10000 ps] WR @ (3, 856) ->
[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11369) -> [17500 ps] WR @ (3, 856) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9210) ->
[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10290) -> [17500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) -> [35000 ps] PRE @ (3) ->
[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7052) -> [10000 ps] ACT @ (7, 8131) -> [17500 ps] WR @ (7, 848) -> [10000 ps] WR @ (3, 848) ->
[ 5000 ps] NOP -> [40000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5973) -> [17500 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 4894) -> [17500 ps] WR @ (3, 848) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP ->
[17500 ps] ACT @ (7, 3814) -> [17500 ps] WR @ (7, 848) -> [ 2500 ps] ACT @ (3, 1656) -> [42500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2735) ->
[17500 ps] WR @ (7, 848) -> [10000 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 577) -> [17500 ps] WR @ (3, 848) ->
[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14802) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15882) -> [17500 ps] WR @ (3, 840) ->
[10000 ps] WR @ (7, 840) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 12644) -> [10000 ps] ACT @ (7, 13723) ->
[17500 ps] WR @ (7, 840) -> [10000 ps] WR @ (3, 840) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11565) -> [17500 ps] WR @ (3, 840) ->
[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9406) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10486) -> [17500 ps] WR @ (3, 840) ->
[10000 ps] WR @ (7, 840) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7248) -> [10000 ps] ACT @ (7, 8327) ->
[17500 ps] WR @ (7, 840) -> [10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5089) ->
[10000 ps] ACT @ (3, 6169) -> [17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 832) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) ->
[17500 ps] WR @ (7, 832) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1852) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) ->
[17500 ps] WR @ (7, 832) -> [10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 16077) ->
[10000 ps] ACT @ (3, 773) -> [17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) ->
[17500 ps] WR @ (7, 824) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12840) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) ->
[17500 ps] WR @ (7, 824) -> [10000 ps] WR @ (3, 824) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10681) ->
[10000 ps] ACT @ (3, 11761) -> [17500 ps] WR @ (3, 824) -> [10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) ->
[17500 ps] WR @ (7, 824) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7444) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) ->
[17500 ps] WR @ (7, 824) -> [10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5285) ->
[10000 ps] ACT @ (3, 6365) -> [17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 816) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) ->
[17500 ps] WR @ (7, 816) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2048) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) ->
[17500 ps] WR @ (7, 816) -> [10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 16273) ->
[10000 ps] ACT @ (3, 969) -> [17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) ->
[17500 ps] WR @ (7, 808) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13036) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) ->
[17500 ps] WR @ (7, 808) -> [10000 ps] WR @ (3, 808) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10877) ->
[10000 ps] ACT @ (3, 11957) -> [17500 ps] WR @ (3, 808) -> [10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) ->
[17500 ps] WR @ (7, 808) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7640) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) ->
[17500 ps] WR @ (7, 808) -> [10000 ps] WR @ (3, 800) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5481) ->
[10000 ps] ACT @ (3, 6561) -> [17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
[ 7500 ps] ACT @ (3, 3323) -> [10000 ps] ACT @ (7, 4402) -> [17500 ps] WR @ (7, 800) -> [10000 ps] WR @ (3, 800) -> [45000 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 2244) -> [17500 ps] WR @ (3, 800) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 85) -> [22500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 1165) -> [17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
[ 7500 ps] ACT @ (3, 14311) -> [10000 ps] ACT @ (7, 15390) -> [17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) -> [45000 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 13232) -> [17500 ps] WR @ (3, 792) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11073) -> [22500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 12153) -> [17500 ps] WR @ (3, 792) -> [10000 ps] WR @ (7, 792) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
[ 7500 ps] ACT @ (3, 8915) -> [10000 ps] ACT @ (7, 9994) -> [17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) -> [45000 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 7836) -> [17500 ps] WR @ (3, 784) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5677) -> [22500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 6757) -> [17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
[ 7500 ps] ACT @ (3, 3519) -> [10000 ps] ACT @ (7, 4598) -> [17500 ps] WR @ (7, 784) -> [10000 ps] WR @ (3, 784) -> [45000 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 2440) -> [17500 ps] WR @ (3, 784) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 281) -> [22500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 1361) -> [17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
[ 7500 ps] ACT @ (3, 14507) -> [10000 ps] ACT @ (7, 15586) -> [17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 13428) -> [17500 ps] WR @ (3, 776) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11269) -> [22500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 12349) -> [17500 ps] WR @ (3, 776) -> [10000 ps] WR @ (7, 776) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
[ 7500 ps] ACT @ (3, 9111) -> [10000 ps] ACT @ (7, 10190) -> [17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 8032) -> [17500 ps] WR @ (3, 768) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> [22500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 6953) -> [17500 ps] WR @ (3, 768) -> [ 2500 ps] ACT @ (4, 2852) -> [ 7500 ps] WR @ (7, 768) -> [ 2500 ps] ACT @ (0, 1773) ->
[35000 ps] RD @ (4, 960) -> [10000 ps] RD @ (0, 960) -> [ 7500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15998) ->
[10000 ps] ACT @ (0, 694) -> [15000 ps] RD @ (0, 960) -> [10000 ps] RD @ (4, 952) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14919) ->
[15000 ps] RD @ (4, 952) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12761) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13840) ->
[15000 ps] RD @ (4, 952) -> [10000 ps] RD @ (0, 952) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11682) ->
[10000 ps] ACT @ (4, 10602) -> [ 5000 ps] RD @ (0, 952) -> [10000 ps] RD @ (4, 952) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9523) ->
[15000 ps] RD @ (4, 952) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7365) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8444) ->
[15000 ps] RD @ (4, 952) -> [10000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6286) ->
[10000 ps] ACT @ (4, 5206) -> [ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 944) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4127) ->
[15000 ps] RD @ (4, 944) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3048) ->
[15000 ps] RD @ (4, 944) -> [10000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 890) ->
[10000 ps] ACT @ (4, 16194) -> [ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15115) ->
[15000 ps] RD @ (4, 936) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12957) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14036) ->
[15000 ps] RD @ (4, 936) -> [10000 ps] RD @ (0, 936) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11878) ->
[10000 ps] ACT @ (4, 10798) -> [ 5000 ps] RD @ (0, 936) -> [10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9719) ->
[15000 ps] RD @ (4, 936) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8640) ->
[15000 ps] RD @ (4, 936) -> [10000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6482) ->
[10000 ps] ACT @ (4, 5402) -> [ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4323) ->
[15000 ps] RD @ (4, 928) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2165) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3244) ->
[15000 ps] RD @ (4, 928) -> [10000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1086) ->
[10000 ps] ACT @ (4, 6) -> [ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 14232) -> [10000 ps] ACT @ (4, 15311) -> [15000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) -> [17500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 13153) -> [15000 ps] RD @ (0, 920) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 12074) -> [15000 ps] RD @ (0, 920) -> [10000 ps] RD @ (4, 920) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 9915) -> [10000 ps] ACT @ (0, 8836) -> [ 5000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 7757) -> [15000 ps] RD @ (0, 912) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 6678) -> [15000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 4519) -> [10000 ps] ACT @ (0, 3440) -> [ 5000 ps] RD @ (4, 912) -> [10000 ps] RD @ (0, 912) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 2361) -> [15000 ps] RD @ (0, 912) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 1282) -> [15000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 15507) -> [10000 ps] ACT @ (0, 14428) -> [ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 13349) -> [15000 ps] RD @ (0, 904) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 12270) -> [15000 ps] RD @ (0, 904) -> [10000 ps] RD @ (4, 904) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 10111) -> [10000 ps] ACT @ (0, 9032) -> [ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 7953) -> [15000 ps] RD @ (0, 896) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 6874) -> [15000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 4715) -> [10000 ps] ACT @ (0, 3636) -> [ 5000 ps] RD @ (4, 896) -> [10000 ps] RD @ (0, 896) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 2557) -> [15000 ps] RD @ (0, 896) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 1478) -> [15000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 15703) -> [10000 ps] ACT @ (0, 14624) -> [ 5000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) -> [17500 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12465) -> [10000 ps] ACT @ (0, 13545) -> [15000 ps] RD @ (0, 888) -> [10000 ps] RD @ (4, 888) ->
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11386) -> [15000 ps] RD @ (4, 888) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9228) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10307) -> [15000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8149) -> [10000 ps] ACT @ (4, 7069) -> [ 5000 ps] RD @ (0, 880) -> [10000 ps] RD @ (4, 880) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5990) -> [15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3832) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4911) -> [15000 ps] RD @ (4, 880) -> [10000 ps] RD @ (0, 880) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2753) -> [10000 ps] ACT @ (4, 1673) -> [ 5000 ps] RD @ (0, 880) -> [10000 ps] RD @ (4, 880) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 594) -> [15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14820) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15899) -> [15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13741) -> [10000 ps] ACT @ (4, 12661) -> [ 5000 ps] RD @ (0, 872) -> [10000 ps] RD @ (4, 872) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11582) -> [15000 ps] RD @ (4, 872) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9424) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10503) -> [15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8345) -> [10000 ps] ACT @ (4, 7265) -> [ 5000 ps] RD @ (0, 872) -> [10000 ps] RD @ (4, 864) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6186) -> [15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4028) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5107) -> [15000 ps] RD @ (4, 864) -> [10000 ps] RD @ (0, 864) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2949) -> [10000 ps] ACT @ (4, 1869) -> [ 5000 ps] RD @ (0, 864) -> [10000 ps] RD @ (4, 864) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 790) -> [15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15016) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16095) -> [15000 ps] RD @ (4, 856) -> [10000 ps] RD @ (0, 856) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13937) -> [10000 ps] ACT @ (4, 12857) -> [ 5000 ps] RD @ (0, 856) -> [10000 ps] RD @ (4, 856) ->
[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) -> [15000 ps] RD @ (4, 856) ->
[10000 ps] RD @ (0, 856) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9620) -> [15000 ps] RD @ (0, 856) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 7461) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) -> [15000 ps] RD @ (0, 856) -> [10000 ps] RD @ (4, 848) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6382) -> [10000 ps] ACT @ (0, 5303) -> [ 5000 ps] RD @ (4, 848) ->
[10000 ps] RD @ (0, 848) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4224) -> [15000 ps] RD @ (0, 848) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 2065) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) -> [15000 ps] RD @ (0, 848) -> [10000 ps] RD @ (4, 848) ->
[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 986) -> [10000 ps] ACT @ (0, 16291) ->
[ 5000 ps] RD @ (4, 848) -> [10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) -> [15000 ps] RD @ (0, 840) ->
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13053) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) -> [15000 ps] RD @ (0, 840) ->
[10000 ps] RD @ (4, 840) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11974) -> [10000 ps] ACT @ (0, 10895) ->
[ 5000 ps] RD @ (4, 840) -> [10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) -> [15000 ps] RD @ (0, 840) ->
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7657) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) -> [15000 ps] RD @ (0, 840) ->
[10000 ps] RD @ (4, 832) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6578) -> [10000 ps] ACT @ (0, 5499) ->
[ 5000 ps] RD @ (4, 832) -> [10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) -> [15000 ps] RD @ (0, 832) ->
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2261) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) -> [15000 ps] RD @ (0, 832) ->
[10000 ps] RD @ (4, 832) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1182) -> [10000 ps] ACT @ (0, 103) ->
[ 5000 ps] RD @ (4, 832) -> [10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) -> [15000 ps] RD @ (0, 824) ->
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13249) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) -> [15000 ps] RD @ (0, 824) ->
[10000 ps] RD @ (4, 824) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12170) -> [10000 ps] ACT @ (0, 11091) ->
[ 5000 ps] RD @ (4, 824) -> [10000 ps] RD @ (0, 824) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8932) ->
[10000 ps] ACT @ (0, 10012) -> [15000 ps] RD @ (0, 824) -> [10000 ps] RD @ (4, 824) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) ->
[15000 ps] RD @ (4, 816) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5695) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6774) ->
[15000 ps] RD @ (4, 816) -> [10000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4616) ->
[10000 ps] ACT @ (4, 3536) -> [ 5000 ps] RD @ (0, 816) -> [10000 ps] RD @ (4, 816) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2457) ->
[15000 ps] RD @ (4, 816) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 299) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1378) ->
[15000 ps] RD @ (4, 816) -> [10000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15604) ->
[10000 ps] ACT @ (4, 14524) -> [ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13445) ->
[15000 ps] RD @ (4, 808) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12366) ->
[15000 ps] RD @ (4, 808) -> [10000 ps] RD @ (0, 808) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10208) ->
[10000 ps] ACT @ (4, 9128) -> [ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8049) ->
[15000 ps] RD @ (4, 800) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5891) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6970) ->
[15000 ps] RD @ (4, 800) -> [10000 ps] RD @ (0, 800) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4812) ->
[10000 ps] ACT @ (4, 3732) -> [ 5000 ps] RD @ (0, 800) -> [10000 ps] RD @ (4, 800) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2653) ->
[15000 ps] RD @ (4, 800) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1574) ->
[15000 ps] RD @ (4, 800) -> [10000 ps] RD @ (0, 800) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15800) ->
[10000 ps] ACT @ (4, 14720) -> [ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13641) ->
[15000 ps] RD @ (4, 792) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11483) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12562) ->
[15000 ps] RD @ (4, 792) -> [10000 ps] RD @ (0, 792) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10404) ->
[10000 ps] ACT @ (4, 9324) -> [ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 7166) -> [10000 ps] ACT @ (4, 8245) -> [15000 ps] RD @ (4, 792) -> [10000 ps] RD @ (0, 784) -> [17500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 6087) -> [15000 ps] RD @ (0, 784) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3928) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 5008) -> [15000 ps] RD @ (0, 784) -> [10000 ps] RD @ (4, 784) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 2849) -> [10000 ps] ACT @ (0, 1770) -> [ 5000 ps] RD @ (4, 784) -> [10000 ps] RD @ (0, 784) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 691) -> [15000 ps] RD @ (0, 784) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 15996) -> [15000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 13837) -> [10000 ps] ACT @ (0, 12758) -> [ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 776) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 11679) -> [15000 ps] RD @ (0, 776) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 10600) -> [15000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 8441) -> [10000 ps] ACT @ (0, 7362) -> [ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 6283) -> [15000 ps] RD @ (0, 768) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 5204) -> [15000 ps] RD @ (0, 768) -> [10000 ps] RD @ (4, 768) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 3045) -> [10000 ps] ACT @ (0, 1966) -> [ 5000 ps] RD @ (4, 768) -> [10000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 887) -> [15000 ps] RD @ (0, 768) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 16192) -> [15000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 14033) -> [10000 ps] ACT @ (0, 12954) -> [ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 760) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 11875) -> [15000 ps] RD @ (0, 760) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 10796) -> [15000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 8637) -> [10000 ps] ACT @ (0, 7558) -> [ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 752) -> [17500 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5399) -> [10000 ps] ACT @ (0, 6479) -> [15000 ps] RD @ (0, 752) -> [10000 ps] RD @ (4, 752) ->
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4320) -> [15000 ps] RD @ (4, 752) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2162) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3241) -> [15000 ps] RD @ (4, 752) -> [10000 ps] RD @ (0, 752) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1083) -> [10000 ps] ACT @ (4, 3) -> [ 5000 ps] RD @ (0, 752) -> [10000 ps] RD @ (4, 752) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15308) -> [15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13150) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14229) -> [15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 744) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12071) -> [10000 ps] ACT @ (4, 10991) -> [ 5000 ps] RD @ (0, 744) -> [10000 ps] RD @ (4, 744) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9912) -> [15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7754) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8833) -> [15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 736) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6675) -> [10000 ps] ACT @ (4, 5595) -> [ 5000 ps] RD @ (0, 736) -> [10000 ps] RD @ (4, 736) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4516) -> [15000 ps] RD @ (4, 736) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2358) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3437) -> [15000 ps] RD @ (4, 736) -> [10000 ps] RD @ (0, 736) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1279) -> [10000 ps] ACT @ (4, 199) -> [ 5000 ps] RD @ (0, 736) -> [10000 ps] RD @ (4, 736) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15504) -> [15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13346) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14425) -> [15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 728) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12267) -> [10000 ps] ACT @ (4, 11187) -> [ 5000 ps] RD @ (0, 728) -> [10000 ps] RD @ (4, 728) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10108) -> [15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7950) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9029) -> [15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 720) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6871) -> [10000 ps] ACT @ (4, 5791) -> [ 5000 ps] RD @ (0, 720) -> [10000 ps] RD @ (4, 720) ->
[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) -> [15000 ps] RD @ (4, 720) ->
[10000 ps] RD @ (0, 720) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) -> [15000 ps] RD @ (0, 720) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 395) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) -> [15000 ps] RD @ (0, 720) -> [10000 ps] RD @ (4, 720) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15700) -> [10000 ps] ACT @ (0, 14621) -> [ 5000 ps] RD @ (4, 712) ->
[10000 ps] RD @ (0, 712) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) -> [15000 ps] RD @ (0, 712) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 11383) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12463) -> [15000 ps] RD @ (0, 712) -> [10000 ps] RD @ (4, 712) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10304) -> [10000 ps] ACT @ (0, 9225) -> [ 5000 ps] RD @ (4, 712) ->
[10000 ps] RD @ (0, 712) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) -> [15000 ps] RD @ (0, 704) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 5987) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) -> [15000 ps] RD @ (0, 704) -> [10000 ps] RD @ (4, 704) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4908) -> [10000 ps] ACT @ (0, 3829) -> [ 5000 ps] RD @ (4, 704) ->
[10000 ps] RD @ (0, 704) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) -> [15000 ps] RD @ (0, 704) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 591) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) -> [15000 ps] RD @ (0, 704) -> [10000 ps] RD @ (4, 704) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15896) -> [10000 ps] ACT @ (0, 14817) -> [ 5000 ps] RD @ (4, 696) ->
[10000 ps] RD @ (0, 696) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) -> [15000 ps] RD @ (0, 696) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 11579) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12659) -> [15000 ps] RD @ (0, 696) -> [10000 ps] RD @ (4, 696) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10500) -> [10000 ps] ACT @ (0, 9421) -> [ 5000 ps] RD @ (4, 696) ->
[10000 ps] RD @ (0, 696) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) -> [15000 ps] RD @ (0, 696) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 6183) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> [15000 ps] RD @ (0, 688) -> [10000 ps] RD @ (4, 688) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5104) -> [10000 ps] ACT @ (0, 4025) -> [ 5000 ps] RD @ (4, 688) ->
[10000 ps] RD @ (0, 688) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) -> [10000 ps] ACT @ (0, 2946) ->
[15000 ps] RD @ (0, 688) -> [10000 ps] RD @ (4, 688) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) -> [15000 ps] RD @ (4, 688) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15013) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) -> [15000 ps] RD @ (4, 680) ->
[10000 ps] RD @ (0, 680) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13934) -> [10000 ps] ACT @ (4, 12854) ->
[ 5000 ps] RD @ (0, 680) -> [10000 ps] RD @ (4, 680) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) -> [15000 ps] RD @ (4, 680) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9617) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) -> [15000 ps] RD @ (4, 680) ->
[10000 ps] RD @ (0, 680) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8538) -> [10000 ps] ACT @ (4, 7458) ->
[ 5000 ps] RD @ (0, 680) -> [10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) -> [15000 ps] RD @ (4, 672) ->
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[10000 ps] RD @ (0, 672) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3142) -> [10000 ps] ACT @ (4, 2062) ->
[ 5000 ps] RD @ (0, 672) -> [10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) -> [15000 ps] RD @ (4, 672) ->
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[10000 ps] RD @ (0, 664) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14130) -> [10000 ps] ACT @ (4, 13050) ->
[ 5000 ps] RD @ (0, 664) -> [10000 ps] RD @ (4, 664) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) -> [15000 ps] RD @ (4, 664) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9813) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) -> [15000 ps] RD @ (4, 664) ->
[10000 ps] RD @ (0, 664) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8734) -> [10000 ps] ACT @ (4, 7654) ->
[ 5000 ps] RD @ (0, 664) -> [10000 ps] RD @ (4, 656) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) -> [15000 ps] RD @ (4, 656) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4417) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) -> [15000 ps] RD @ (4, 656) ->
[10000 ps] RD @ (0, 656) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3338) -> [10000 ps] ACT @ (4, 2258) ->
[ 5000 ps] RD @ (0, 656) -> [10000 ps] RD @ (4, 656) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 100) ->
[10000 ps] ACT @ (4, 1179) -> [15000 ps] RD @ (4, 656) -> [10000 ps] RD @ (0, 656) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15405) ->
[15000 ps] RD @ (0, 648) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14326) ->
[15000 ps] RD @ (0, 648) -> [10000 ps] RD @ (4, 648) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12167) ->
[10000 ps] ACT @ (0, 11088) -> [ 5000 ps] RD @ (4, 648) -> [10000 ps] RD @ (0, 648) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10009) ->
[15000 ps] RD @ (0, 648) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7850) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8930) ->
[15000 ps] RD @ (0, 648) -> [10000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6771) ->
[10000 ps] ACT @ (0, 5692) -> [ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4613) ->
[15000 ps] RD @ (0, 640) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3534) ->
[15000 ps] RD @ (0, 640) -> [10000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1375) ->
[10000 ps] ACT @ (0, 296) -> [ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15601) ->
[15000 ps] RD @ (0, 632) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13442) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14522) ->
[15000 ps] RD @ (0, 632) -> [10000 ps] RD @ (4, 632) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12363) ->
[10000 ps] ACT @ (0, 11284) -> [ 5000 ps] RD @ (4, 632) -> [10000 ps] RD @ (0, 632) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10205) ->
[15000 ps] RD @ (0, 632) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8046) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9126) ->
[15000 ps] RD @ (0, 632) -> [10000 ps] RD @ (4, 624) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6967) ->
[10000 ps] ACT @ (0, 5888) -> [ 5000 ps] RD @ (4, 624) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (0, 624) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 4809) -> [15000 ps] RD @ (0, 624) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) -> [15000 ps] RD @ (0, 624) ->
[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 2650) -> [15000 ps] RD @ (4, 624) ->
[ 5000 ps] ACT @ (0, 492) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1571) -> [15000 ps] RD @ (4, 624) -> [10000 ps] RD @ (0, 624) ->
[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15797) -> [10000 ps] ACT @ (4, 14717) -> [ 5000 ps] RD @ (0, 616) ->
[10000 ps] RD @ (4, 616) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) -> [15000 ps] RD @ (4, 616) -> [ 7500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 11480) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12559) -> [15000 ps] RD @ (4, 616) -> [10000 ps] RD @ (0, 616) ->
[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10401) -> [10000 ps] ACT @ (4, 9321) -> [ 5000 ps] RD @ (0, 616) ->
[10000 ps] RD @ (4, 616) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8242) -> [15000 ps] RD @ (4, 616) -> [ 7500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 6084) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7163) -> [15000 ps] RD @ (4, 608) -> [10000 ps] RD @ (0, 608) ->
[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5005) -> [10000 ps] ACT @ (4, 3925) -> [ 5000 ps] RD @ (0, 608) ->
[10000 ps] RD @ (4, 608) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) -> [15000 ps] RD @ (4, 608) -> [ 7500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 688) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1767) -> [15000 ps] RD @ (4, 608) -> [10000 ps] RD @ (0, 608) ->
[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15993) -> [10000 ps] ACT @ (4, 14913) -> [ 5000 ps] RD @ (0, 600) ->
[10000 ps] RD @ (4, 600) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13834) -> [15000 ps] RD @ (4, 600) -> [ 7500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 11676) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12755) -> [15000 ps] RD @ (4, 600) -> [10000 ps] RD @ (0, 600) ->
[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10597) -> [10000 ps] ACT @ (4, 9517) -> [ 5000 ps] RD @ (0, 600) ->
[10000 ps] RD @ (4, 600) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) -> [15000 ps] RD @ (4, 600) -> [ 7500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 6280) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7359) -> [15000 ps] RD @ (4, 592) -> [10000 ps] RD @ (0, 592) ->
[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5201) -> [10000 ps] ACT @ (4, 4121) -> [ 5000 ps] RD @ (0, 592) ->
[10000 ps] RD @ (4, 592) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3042) -> [15000 ps] RD @ (4, 592) -> [ 7500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 884) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1963) -> [15000 ps] RD @ (4, 592) -> [10000 ps] RD @ (0, 592) ->
[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16189) -> [10000 ps] ACT @ (4, 15109) -> [ 5000 ps] RD @ (0, 584) ->
[10000 ps] RD @ (4, 584) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) -> [10000 ps] ACT @ (4, 14030) ->
[15000 ps] RD @ (4, 584) -> [10000 ps] RD @ (0, 584) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) -> [15000 ps] RD @ (0, 584) ->
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9713) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) -> [15000 ps] RD @ (0, 584) ->
[10000 ps] RD @ (4, 584) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8634) -> [10000 ps] ACT @ (0, 7555) ->
[ 5000 ps] RD @ (4, 584) -> [10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) -> [15000 ps] RD @ (0, 576) ->
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[10000 ps] RD @ (4, 576) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3238) -> [10000 ps] ACT @ (0, 2159) ->
[ 5000 ps] RD @ (4, 576) -> [10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) -> [15000 ps] RD @ (0, 576) ->
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15305) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) -> [15000 ps] RD @ (0, 576) ->
[10000 ps] RD @ (4, 568) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14226) -> [10000 ps] ACT @ (0, 13147) ->
[ 5000 ps] RD @ (4, 568) -> [10000 ps] RD @ (0, 568) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) -> [15000 ps] RD @ (0, 568) ->
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9909) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) -> [15000 ps] RD @ (0, 568) ->
[10000 ps] RD @ (4, 568) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8830) -> [10000 ps] ACT @ (0, 7751) ->
[ 5000 ps] RD @ (4, 568) -> [10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) -> [15000 ps] RD @ (0, 560) ->
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4513) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) -> [15000 ps] RD @ (0, 560) ->
[10000 ps] RD @ (4, 560) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3434) -> [10000 ps] ACT @ (0, 2355) ->
[ 5000 ps] RD @ (4, 560) -> [10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) -> [15000 ps] RD @ (0, 560) ->
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15501) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) -> [15000 ps] RD @ (0, 560) ->
[10000 ps] RD @ (4, 552) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14422) -> [10000 ps] ACT @ (0, 13343) ->
[ 5000 ps] RD @ (4, 552) -> [10000 ps] RD @ (0, 552) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11184) ->
[10000 ps] ACT @ (0, 12264) -> [15000 ps] RD @ (0, 552) -> [10000 ps] RD @ (4, 552) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10105) ->
[15000 ps] RD @ (4, 552) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7947) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9026) ->
[15000 ps] RD @ (4, 552) -> [10000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6868) ->
[10000 ps] ACT @ (4, 5788) -> [ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4709) ->
[15000 ps] RD @ (4, 544) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2551) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3630) ->
[15000 ps] RD @ (4, 544) -> [10000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1472) ->
[10000 ps] ACT @ (4, 392) -> [ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15697) ->
[15000 ps] RD @ (4, 536) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13539) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14618) ->
[15000 ps] RD @ (4, 536) -> [10000 ps] RD @ (0, 536) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12460) ->
[10000 ps] ACT @ (4, 11380) -> [ 5000 ps] RD @ (0, 536) -> [10000 ps] RD @ (4, 536) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10301) ->
[15000 ps] RD @ (4, 536) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8143) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9222) ->
[15000 ps] RD @ (4, 536) -> [10000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7064) ->
[10000 ps] ACT @ (4, 5984) -> [ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4905) ->
[15000 ps] RD @ (4, 528) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2747) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3826) ->
[15000 ps] RD @ (4, 528) -> [10000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1668) ->
[10000 ps] ACT @ (4, 588) -> [ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15893) ->
[15000 ps] RD @ (4, 520) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13735) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14814) ->
[15000 ps] RD @ (4, 520) -> [10000 ps] RD @ (0, 520) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12656) ->
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[ 7500 ps] ACT @ (0, 9418) -> [10000 ps] ACT @ (4, 10497) -> [15000 ps] RD @ (4, 520) -> [10000 ps] RD @ (0, 520) -> [17500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 8339) -> [15000 ps] RD @ (0, 520) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 7260) -> [15000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 5101) -> [10000 ps] ACT @ (0, 4022) -> [ 5000 ps] RD @ (4, 512) -> [10000 ps] RD @ (0, 512) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 2943) -> [15000 ps] RD @ (0, 512) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 784) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 1864) -> [15000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 16089) -> [10000 ps] ACT @ (0, 15010) -> [ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 13931) -> [15000 ps] RD @ (0, 504) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) -> [ 2500 ps] PRE @ (0) ->
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[ 7500 ps] ACT @ (4, 10693) -> [10000 ps] ACT @ (0, 9614) -> [ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 8535) -> [15000 ps] RD @ (0, 504) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6376) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 7456) -> [15000 ps] RD @ (0, 496) -> [10000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
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[17500 ps] ACT @ (0, 3139) -> [15000 ps] RD @ (0, 496) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) -> [ 2500 ps] PRE @ (0) ->
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[10000 ps] RD @ (0, 400) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 5394) ->
[10000 ps] ACT @ (4, 4314) -> [ 5000 ps] RD @ (0, 400) -> [10000 ps] RD @ (4, 400) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3235) ->
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[10000 ps] RD @ (0, 264) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14712) -> [10000 ps] ACT @ (4, 13632) ->
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[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10395) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11474) -> [15000 ps] RD @ (4, 264) ->
[10000 ps] RD @ (0, 264) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9316) -> [10000 ps] ACT @ (4, 8236) ->
[ 5000 ps] RD @ (0, 264) -> [10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7157) -> [15000 ps] RD @ (4, 256) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4999) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6078) -> [15000 ps] RD @ (4, 256) ->
[10000 ps] RD @ (0, 256) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3920) -> [10000 ps] ACT @ (4, 2840) ->
[ 5000 ps] RD @ (0, 256) -> [10000 ps] RD @ (4, 256) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1761) -> [15000 ps] RD @ (4, 256) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15987) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 682) -> [15000 ps] RD @ (4, 256) ->
[10000 ps] RD @ (0, 248) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14908) -> [10000 ps] ACT @ (4, 13828) ->
[ 5000 ps] RD @ (0, 248) -> [10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) ->
[10000 ps] ACT @ (4, 12749) -> [15000 ps] RD @ (4, 248) -> [10000 ps] RD @ (0, 248) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) ->
[15000 ps] RD @ (0, 248) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8432) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9512) ->
[15000 ps] RD @ (0, 248) -> [10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7353) ->
[10000 ps] ACT @ (0, 6274) -> [ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) ->
[15000 ps] RD @ (0, 240) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) ->
[15000 ps] RD @ (0, 240) -> [10000 ps] RD @ (4, 240) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1957) ->
[10000 ps] ACT @ (0, 878) -> [ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) ->
[15000 ps] RD @ (0, 232) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) ->
[15000 ps] RD @ (0, 232) -> [10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12945) ->
[10000 ps] ACT @ (0, 11866) -> [ 5000 ps] RD @ (4, 232) -> [10000 ps] RD @ (0, 232) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) ->
[15000 ps] RD @ (0, 232) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) ->
[15000 ps] RD @ (0, 232) -> [10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7549) ->
[10000 ps] ACT @ (0, 6470) -> [ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) ->
[15000 ps] RD @ (0, 224) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) ->
[15000 ps] RD @ (0, 224) -> [10000 ps] RD @ (4, 224) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2153) ->
[10000 ps] ACT @ (0, 1074) -> [ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) ->
[15000 ps] RD @ (0, 216) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) ->
[15000 ps] RD @ (0, 216) -> [10000 ps] RD @ (4, 216) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13141) ->
[10000 ps] ACT @ (0, 12062) -> [ 5000 ps] RD @ (4, 216) -> [10000 ps] RD @ (0, 216) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 9903) -> [10000 ps] ACT @ (0, 10983) -> [15000 ps] RD @ (0, 216) -> [10000 ps] RD @ (4, 216) -> [17500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 8824) -> [15000 ps] RD @ (4, 216) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6666) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 7745) -> [15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 5587) -> [10000 ps] ACT @ (4, 4507) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 208) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 3428) -> [15000 ps] RD @ (4, 208) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1270) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 2349) -> [15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 191) -> [10000 ps] ACT @ (4, 15495) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 14416) -> [15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12258) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 13337) -> [15000 ps] RD @ (4, 200) -> [10000 ps] RD @ (0, 200) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 11179) -> [10000 ps] ACT @ (4, 10099) -> [ 5000 ps] RD @ (0, 200) -> [10000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 9020) -> [15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6862) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 7941) -> [15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 5783) -> [10000 ps] ACT @ (4, 4703) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 192) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 3624) -> [15000 ps] RD @ (4, 192) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1466) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 2545) -> [15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 387) -> [10000 ps] ACT @ (4, 15691) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 184) -> [27500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 14612) -> [15000 ps] RD @ (4, 184) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12454) -> [ 2500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 13533) -> [15000 ps] RD @ (4, 184) -> [10000 ps] RD @ (0, 184) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 11375) -> [10000 ps] ACT @ (4, 10295) -> [ 5000 ps] RD @ (0, 184) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (4, 184) ->
[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8137) -> [10000 ps] ACT @ (4, 9216) -> [15000 ps] RD @ (4, 184) ->
[10000 ps] RD @ (0, 176) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 7058) ->
[15000 ps] RD @ (0, 176) -> [ 5000 ps] ACT @ (4, 4899) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) -> [15000 ps] RD @ (0, 176) ->
[10000 ps] RD @ (4, 176) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3820) -> [10000 ps] ACT @ (0, 2741) ->
[ 5000 ps] RD @ (4, 176) -> [10000 ps] RD @ (0, 176) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1662) -> [15000 ps] RD @ (0, 176) ->
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15887) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 583) -> [15000 ps] RD @ (0, 176) ->
[10000 ps] RD @ (4, 168) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14808) -> [10000 ps] ACT @ (0, 13729) ->
[ 5000 ps] RD @ (4, 168) -> [10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) -> [15000 ps] RD @ (0, 168) ->
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10491) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) -> [15000 ps] RD @ (0, 168) ->
[10000 ps] RD @ (4, 168) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9412) -> [10000 ps] ACT @ (0, 8333) ->
[ 5000 ps] RD @ (4, 168) -> [10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7254) -> [15000 ps] RD @ (0, 160) ->
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5095) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6175) -> [15000 ps] RD @ (0, 160) ->
[10000 ps] RD @ (4, 160) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4016) -> [10000 ps] ACT @ (0, 2937) ->
[ 5000 ps] RD @ (4, 160) -> [10000 ps] RD @ (0, 160) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) -> [15000 ps] RD @ (0, 160) ->
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16083) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) -> [15000 ps] RD @ (0, 160) ->
[10000 ps] RD @ (4, 152) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15004) -> [10000 ps] ACT @ (0, 13925) ->
[ 5000 ps] RD @ (4, 152) -> [10000 ps] RD @ (0, 152) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12846) -> [15000 ps] RD @ (0, 152) ->
[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10687) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11767) -> [15000 ps] RD @ (0, 152) ->
[10000 ps] RD @ (4, 152) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9608) -> [10000 ps] ACT @ (0, 8529) ->
[ 5000 ps] RD @ (4, 152) -> [10000 ps] RD @ (0, 152) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6370) ->
[10000 ps] ACT @ (0, 7450) -> [15000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5291) ->
[15000 ps] RD @ (4, 144) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4212) ->
[15000 ps] RD @ (4, 144) -> [10000 ps] RD @ (0, 144) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2054) ->
[10000 ps] ACT @ (4, 974) -> [ 5000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16279) ->
[15000 ps] RD @ (4, 136) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14121) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15200) ->
[15000 ps] RD @ (4, 136) -> [10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13042) ->
[10000 ps] ACT @ (4, 11962) -> [ 5000 ps] RD @ (0, 136) -> [10000 ps] RD @ (4, 136) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10883) ->
[15000 ps] RD @ (4, 136) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9804) ->
[15000 ps] RD @ (4, 136) -> [10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7646) ->
[10000 ps] ACT @ (4, 6566) -> [ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5487) ->
[15000 ps] RD @ (4, 128) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4408) ->
[15000 ps] RD @ (4, 128) -> [10000 ps] RD @ (0, 128) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2250) ->
[10000 ps] ACT @ (4, 1170) -> [ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 91) ->
[15000 ps] RD @ (4, 128) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15396) ->
[15000 ps] RD @ (4, 120) -> [10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13238) ->
[10000 ps] ACT @ (4, 12158) -> [ 5000 ps] RD @ (0, 120) -> [10000 ps] RD @ (4, 120) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11079) ->
[15000 ps] RD @ (4, 120) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10000) ->
[15000 ps] RD @ (4, 120) -> [10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7842) ->
[10000 ps] ACT @ (4, 6762) -> [ 5000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (0, 4604) -> [10000 ps] ACT @ (4, 5683) -> [15000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 112) -> [17500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 3525) -> [15000 ps] RD @ (0, 112) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 2446) -> [15000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 287) -> [10000 ps] ACT @ (0, 15592) -> [ 5000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 14513) -> [15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12354) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 13434) -> [15000 ps] RD @ (0, 104) -> [10000 ps] RD @ (4, 104) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 11275) -> [10000 ps] ACT @ (0, 10196) -> [ 5000 ps] RD @ (4, 104) -> [10000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 9117) -> [15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 8038) -> [15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 5879) -> [10000 ps] ACT @ (0, 4800) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 96) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 3721) -> [15000 ps] RD @ (0, 96) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1562) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 2642) -> [15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 483) -> [10000 ps] ACT @ (0, 15788) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 14709) -> [15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 13630) -> [15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 88) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 11471) -> [10000 ps] ACT @ (0, 10392) -> [ 5000 ps] RD @ (4, 88) -> [10000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 9313) -> [15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7154) -> [ 2500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 8234) -> [15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (4, 6075) -> [10000 ps] ACT @ (0, 4996) -> [ 5000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 80) -> [17500 ps] PRE @ (4) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2837) -> [10000 ps] ACT @ (0, 3917) -> [15000 ps] RD @ (0, 80) -> [10000 ps] RD @ (4, 80) ->
[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1758) -> [15000 ps] RD @ (4, 80) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15984) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 679) -> [15000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 72) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14905) -> [10000 ps] ACT @ (4, 13825) -> [ 5000 ps] RD @ (0, 72) -> [10000 ps] RD @ (4, 72) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12746) -> [15000 ps] RD @ (4, 72) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10588) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11667) -> [15000 ps] RD @ (4, 72) -> [10000 ps] RD @ (0, 72) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9509) -> [10000 ps] ACT @ (4, 8429) -> [ 5000 ps] RD @ (0, 72) -> [10000 ps] RD @ (4, 72) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7350) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5192) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6271) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 64) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4113) -> [10000 ps] ACT @ (4, 3033) -> [ 5000 ps] RD @ (0, 64) -> [10000 ps] RD @ (4, 64) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1954) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16180) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 875) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 56) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15101) -> [10000 ps] ACT @ (4, 14021) -> [ 5000 ps] RD @ (0, 56) -> [10000 ps] RD @ (4, 56) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12942) -> [15000 ps] RD @ (4, 56) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10784) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11863) -> [15000 ps] RD @ (4, 56) -> [10000 ps] RD @ (0, 56) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9705) -> [10000 ps] ACT @ (4, 8625) -> [ 5000 ps] RD @ (0, 56) -> [10000 ps] RD @ (4, 56) ->
[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7546) -> [15000 ps] RD @ (4, 48) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5388) ->
[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6467) -> [15000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) -> [17500 ps] PRE @ (0) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4309) -> [10000 ps] ACT @ (4, 3229) -> [ 5000 ps] RD @ (0, 48) -> [10000 ps] RD @ (4, 48) ->
[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1071) -> [10000 ps] ACT @ (4, 2150) -> [15000 ps] RD @ (4, 48) ->
[10000 ps] RD @ (0, 48) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) -> [15000 ps] RD @ (0, 40) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 14217) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) -> [15000 ps] RD @ (0, 40) -> [10000 ps] RD @ (4, 40) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13138) -> [10000 ps] ACT @ (0, 12059) -> [ 5000 ps] RD @ (4, 40) ->
[10000 ps] RD @ (0, 40) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10980) -> [15000 ps] RD @ (0, 40) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 8821) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9901) -> [15000 ps] RD @ (0, 40) -> [10000 ps] RD @ (4, 40) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7742) -> [10000 ps] ACT @ (0, 6663) -> [ 5000 ps] RD @ (4, 32) ->
[10000 ps] RD @ (0, 32) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) -> [15000 ps] RD @ (0, 32) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 3425) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) -> [15000 ps] RD @ (0, 32) -> [10000 ps] RD @ (4, 32) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2346) -> [10000 ps] ACT @ (0, 1267) -> [ 5000 ps] RD @ (4, 32) ->
[10000 ps] RD @ (0, 32) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 188) -> [15000 ps] RD @ (0, 32) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 14413) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15493) -> [15000 ps] RD @ (0, 24) -> [10000 ps] RD @ (4, 24) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13334) -> [10000 ps] ACT @ (0, 12255) -> [ 5000 ps] RD @ (4, 24) ->
[10000 ps] RD @ (0, 24) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) -> [15000 ps] RD @ (0, 24) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 9017) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) -> [15000 ps] RD @ (0, 24) -> [10000 ps] RD @ (4, 24) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7938) -> [10000 ps] ACT @ (0, 6859) -> [ 5000 ps] RD @ (4, 16) ->
[10000 ps] RD @ (0, 16) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5780) -> [15000 ps] RD @ (0, 16) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 3621) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4701) -> [15000 ps] RD @ (0, 16) -> [10000 ps] RD @ (4, 16) ->
[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2542) -> [10000 ps] ACT @ (0, 1463) -> [ 5000 ps] RD @ (4, 16) ->
[10000 ps] RD @ (0, 16) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15688) -> [10000 ps] ACT @ (0, 384) ->
[15000 ps] RD @ (0, 16) -> [10000 ps] RD @ (4, 8) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) -> [15000 ps] RD @ (4, 8) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12451) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13530) -> [15000 ps] RD @ (4, 8) ->
[10000 ps] RD @ (0, 8) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11372) -> [10000 ps] ACT @ (4, 10292) ->
[ 5000 ps] RD @ (0, 8) -> [10000 ps] RD @ (4, 8) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9213) -> [15000 ps] RD @ (4, 8) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7055) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) -> [15000 ps] RD @ (4, 0) ->
[10000 ps] RD @ (0, 0) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5976) -> [10000 ps] ACT @ (4, 4896) ->
[ 5000 ps] RD @ (0, 0) -> [10000 ps] RD @ (4, 0) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) -> [15000 ps] RD @ (4, 0) ->
[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1659) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2738) -> [15000 ps] RD @ (4, 0) ->
[10000 ps] RD @ (0, 0) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 580) -> [15000 ps] RD @ (0, 0) -> [ 5000 ps] ACT @ (7, 15884) ->
[15000 ps] RD @ (7, 1016) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13727) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14805) ->
[15000 ps] RD @ (7, 1016) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13726) ->
[15000 ps] RD @ (7, 1016) -> [ 5000 ps] ACT @ (3, 12647) -> [ 2500 ps] PRE @ (4) -> [12500 ps] RD @ (3, 1016) -> [ 7500 ps] PRE @ (0) ->
[17500 ps] ACT @ (0, 10489) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> [15000 ps] RD @ (3, 1016) -> [ 7500 ps] PRE @ (7) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10488) -> [10000 ps] ACT @ (0, 9410) -> [ 5000 ps] RD @ (7, 1016) -> [27500 ps] PRE @ (7) ->
[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 9409) -> [10000 ps] ACT @ (0, 8331) -> [ 5000 ps] RD @ (7, 1016) -> [ 5000 ps] ACT @ (4, 7251) ->
[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8330) -> [15000 ps] RD @ (7, 1016) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (3, 7251) -> [10000 ps] ACT @ (4, 6172) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5093) ->
[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6172) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (7, 5092) -> [10000 ps] ACT @ (0, 4014) -> [ 5000 ps] RD @ (7, 1008) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (7, 4013) -> [10000 ps] ACT @ (0, 2935) -> [ 5000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1855) ->
[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2934) -> [15000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (3, 1855) -> [10000 ps] ACT @ (4, 776) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16081) ->
[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 776) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (7, 16080) -> [10000 ps] ACT @ (0, 15002) -> [ 5000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13922) ->
[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15001) -> [15000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (3, 13922) -> [10000 ps] ACT @ (4, 12843) -> [ 5000 ps] RD @ (3, 1000) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (3, 12843) -> [10000 ps] ACT @ (4, 11764) -> [ 5000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10685) ->
[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11764) -> [15000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (7, 10684) -> [10000 ps] ACT @ (0, 9606) -> [ 5000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8526) ->
[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9605) -> [15000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (3, 8526) -> [10000 ps] ACT @ (4, 7447) -> [ 5000 ps] RD @ (3, 1000) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) ->
[ 7500 ps] ACT @ (3, 7447) -> [10000 ps] ACT @ (4, 6368) -> [ 5000 ps] RD @ (3, 992) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5289) ->
[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6368) -> [15000 ps] RD @ (3, 992) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (7, 5288) -> [10000 ps] ACT @ (0, 4210) -> [ 5000 ps] RD @ (7, 992) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4209) ->
[15000 ps] RD @ (7, 992) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 3130) ->
[10000 ps] ACT @ (3, 3130) -> [15000 ps] RD @ (3, 992) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 972) ->
[10000 ps] ACT @ (3, 2051) -> [15000 ps] RD @ (3, 992) -> [ 5000 ps] ACT @ (0, 16277) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 972) ->
[15000 ps] RD @ (3, 992) -> [ 5000 ps] ACT @ (7, 16276) -> [ 2500 ps] PRE @ (0) -> [12500 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (4) ->
[17500 ps] ACT @ (4, 14118) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15197) -> [15000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (3) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 14118) -> [10000 ps] ACT @ (4, 13039) -> [ 5000 ps] RD @ (3, 984) -> [27500 ps] PRE @ (3) ->
[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13039) -> [10000 ps] ACT @ (4, 11960) -> [ 5000 ps] RD @ (3, 984) -> [ 5000 ps] ACT @ (0, 10881) ->
[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11960) -> [15000 ps] RD @ (3, 984) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) ->
[ 7500 ps] ACT @ (7, 10880) -> [10000 ps] ACT @ (0, 9802) -> [ 5000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8722) ->
[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9801) -> [15000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8722) ->
[15000 ps] RD @ (3, 984) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> [15000 ps] RD @ (3, 976) -> [ 7500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 5484) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> [15000 ps] RD @ (3, 976) -> [10000 ps] RD @ (7, 976) ->
[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4405) -> [10000 ps] ACT @ (3, 3326) -> [ 5000 ps] RD @ (7, 976) ->
[10000 ps] RD @ (3, 976) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> [15000 ps] RD @ (3, 976) -> [ 7500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 88) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> [15000 ps] RD @ (3, 976) -> [10000 ps] RD @ (7, 976) ->
[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15393) -> [10000 ps] ACT @ (3, 14314) -> [ 5000 ps] RD @ (7, 968) ->
[10000 ps] RD @ (3, 968) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12155) -> [10000 ps] ACT @ (3, 13235) ->
[15000 ps] RD @ (3, 968) -> [10000 ps] RD @ (7, 968) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11076) -> [15000 ps] RD @ (7, 968) ->
[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8918) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9997) -> [15000 ps] RD @ (7, 968) ->
[10000 ps] RD @ (3, 968) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7839) -> [10000 ps] ACT @ (7, 6759) ->
[ 5000 ps] RD @ (3, 960) -> [10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5680) -> [15000 ps] RD @ (7, 960) ->
[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3522) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4601) -> [15000 ps] RD @ (7, 960) ->
[10000 ps] RD @ (3, 960) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 2443) -> [10000 ps] ACT @ (7, 1363) ->
[ 5000 ps] RD @ (3, 960) -> [10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 284) -> [15000 ps] RD @ (7, 960) ->
[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14510) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15589) -> [15000 ps] RD @ (7, 952) ->
[10000 ps] RD @ (3, 952) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 13431) -> [10000 ps] ACT @ (7, 12351) ->
[ 5000 ps] RD @ (3, 952) -> [10000 ps] RD @ (7, 952) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11272) -> [15000 ps] RD @ (7, 952) ->
[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9114) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10193) -> [15000 ps] RD @ (7, 952) ->
[10000 ps] RD @ (3, 952) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 8035) -> [10000 ps] ACT @ (7, 6955) ->
[ 5000 ps] RD @ (3, 944) -> [10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5876) -> [15000 ps] RD @ (7, 944) ->
[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3718) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4797) -> [15000 ps] RD @ (7, 944) ->
[10000 ps] RD @ (3, 944) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 2639) -> [10000 ps] ACT @ (7, 1559) ->
[ 5000 ps] RD @ (3, 944) -> [10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 480) -> [15000 ps] RD @ (7, 944) ->
[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14706) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15785) -> [15000 ps] RD @ (7, 936) ->
[10000 ps] RD @ (3, 936) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 13627) -> [10000 ps] ACT @ (7, 12547) ->
[ 5000 ps] RD @ (3, 936) -> [10000 ps] RD @ (7, 936) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10389) ->
[10000 ps] ACT @ (7, 11468) -> [15000 ps] RD @ (7, 936) -> [10000 ps] RD @ (3, 936) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9310) ->
[15000 ps] RD @ (3, 936) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8231) ->
[15000 ps] RD @ (3, 936) -> [10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6072) ->
[10000 ps] ACT @ (3, 4993) -> [ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 928) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3914) ->
[15000 ps] RD @ (3, 928) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2835) ->
[15000 ps] RD @ (3, 928) -> [10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 676) ->
[10000 ps] ACT @ (3, 15981) -> [ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 920) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14902) ->
[15000 ps] RD @ (3, 920) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13823) ->
[15000 ps] RD @ (3, 920) -> [10000 ps] RD @ (7, 920) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 11664) ->
[10000 ps] ACT @ (3, 10585) -> [ 5000 ps] RD @ (7, 920) -> [10000 ps] RD @ (3, 920) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9506) ->
[15000 ps] RD @ (3, 920) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8427) ->
[15000 ps] RD @ (3, 920) -> [10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6268) ->
[10000 ps] ACT @ (3, 5189) -> [ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 912) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4110) ->
[15000 ps] RD @ (3, 912) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3031) ->
[15000 ps] RD @ (3, 912) -> [10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 872) ->
[10000 ps] ACT @ (3, 16177) -> [ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 904) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15098) ->
[15000 ps] RD @ (3, 904) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14019) ->
[15000 ps] RD @ (3, 904) -> [10000 ps] RD @ (7, 904) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 11860) ->
[10000 ps] ACT @ (3, 10781) -> [ 5000 ps] RD @ (7, 904) -> [10000 ps] RD @ (3, 904) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) ->
[ 7500 ps] ACT @ (7, 8622) -> [10000 ps] ACT @ (3, 9702) -> [15000 ps] RD @ (3, 904) -> [10000 ps] RD @ (7, 904) -> [17500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 7543) -> [15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) -> [ 2500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 6464) -> [15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 896) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
[ 7500 ps] ACT @ (3, 4306) -> [10000 ps] ACT @ (7, 3226) -> [ 5000 ps] RD @ (3, 896) -> [10000 ps] RD @ (7, 896) -> [27500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 2147) -> [15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16373) -> [ 2500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 1068) -> [15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 888) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
[ 7500 ps] ACT @ (3, 15294) -> [10000 ps] ACT @ (7, 14214) -> [ 5000 ps] RD @ (3, 888) -> [10000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 13135) -> [15000 ps] RD @ (7, 888) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) -> [ 2500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 12056) -> [15000 ps] RD @ (7, 888) -> [10000 ps] RD @ (3, 888) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
[ 7500 ps] ACT @ (3, 9898) -> [10000 ps] ACT @ (7, 8818) -> [ 5000 ps] RD @ (3, 888) -> [10000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 7739) -> [15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5581) -> [ 2500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 6660) -> [15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
[ 7500 ps] ACT @ (3, 4502) -> [10000 ps] ACT @ (7, 3422) -> [ 5000 ps] RD @ (3, 880) -> [10000 ps] RD @ (7, 880) -> [27500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 2343) -> [15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) -> [ 2500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 1264) -> [15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
[ 7500 ps] ACT @ (3, 15490) -> [10000 ps] ACT @ (7, 14410) -> [ 5000 ps] RD @ (3, 872) -> [10000 ps] RD @ (7, 872) -> [27500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 13331) -> [15000 ps] RD @ (7, 872) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11173) -> [ 2500 ps] PRE @ (7) ->
[17500 ps] ACT @ (7, 12252) -> [15000 ps] RD @ (7, 872) -> [10000 ps] RD @ (3, 872) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) ->
[ 7500 ps] ACT @ (3, 10094) -> [10000 ps] ACT @ (7, 9014) -> [ 5000 ps] RD @ (3, 872) -> [10000 ps] RD @ (7, 872) -> [17500 ps] PRE @ (3) ->
[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) -> [15000 ps] RD @ (7, 864) -> [10000 ps] RD @ (3, 864) ->
[17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5777) -> [15000 ps] RD @ (3, 864) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3618) ->
[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4698) -> [15000 ps] RD @ (3, 864) -> [10000 ps] RD @ (7, 864) -> [17500 ps] PRE @ (7) ->
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 2539) -> [10000 ps] ACT @ (3, 1460) -> [ 5000 ps] RD @ (7, 864) -> [10000 ps] RD @ (3, 864) ->
[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 381) -> [15000 ps] RD @ (3, 864) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14606) ->
[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15686) -> [15000 ps] RD @ (3, 856) -> [10000 ps] RD @ (7, 856) -> [17500 ps] PRE @ (7) ->
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 13527) -> [10000 ps] ACT @ (3, 12448) -> [ 5000 ps] RD @ (7, 856) -> [10000 ps] RD @ (3, 856) ->
[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11369) -> [15000 ps] RD @ (3, 856) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9210) ->
[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10290) -> [15000 ps] RD @ (3, 856) -> [10000 ps] RD @ (7, 856) -> [17500 ps] PRE @ (7) ->
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8131) -> [10000 ps] ACT @ (3, 7052) -> [ 5000 ps] RD @ (7, 848) -> [10000 ps] RD @ (3, 848) ->
[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5973) -> [15000 ps] RD @ (3, 848) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3814) ->
[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4894) -> [15000 ps] RD @ (3, 848) -> [10000 ps] RD @ (7, 848) -> [17500 ps] PRE @ (7) ->
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 2735) -> [10000 ps] ACT @ (3, 1656) -> [ 5000 ps] RD @ (7, 848) -> [10000 ps] RD @ (3, 848) ->
[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 577) -> [15000 ps] RD @ (3, 848) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14802) ->
[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15882) -> [15000 ps] RD @ (3, 840) -> [10000 ps] RD @ (7, 840) -> [17500 ps] PRE @ (7) ->
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 13723) -> [10000 ps] ACT @ (3, 12644) -> [ 5000 ps] RD @ (7, 840) -> [10000 ps] RD @ (3, 840) ->
[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11565) -> [15000 ps] RD @ (3, 840) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9406) ->
[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10486) -> [15000 ps] RD @ (3, 840) -> [10000 ps] RD @ (7, 840) -> [17500 ps] PRE @ (7) ->
[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8327) -> [10000 ps] ACT @ (3, 7248) -> [ 5000 ps] RD @ (7, 840) -> [10000 ps] RD @ (3, 832) ->
[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5089) -> [10000 ps] ACT @ (3, 6169) -> [15000 ps] RD @ (3, 832) ->
[10000 ps] RD @ (7, 832) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) -> [15000 ps] RD @ (7, 832) -> [ 7500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 1852) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) -> [15000 ps] RD @ (7, 832) -> [10000 ps] RD @ (3, 832) ->
[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 773) -> [10000 ps] ACT @ (7, 16077) -> [ 5000 ps] RD @ (3, 832) ->
[10000 ps] RD @ (7, 824) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) -> [15000 ps] RD @ (7, 824) -> [ 7500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 12840) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) -> [15000 ps] RD @ (7, 824) -> [10000 ps] RD @ (3, 824) ->
[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11761) -> [10000 ps] ACT @ (7, 10681) -> [ 5000 ps] RD @ (3, 824) ->
[10000 ps] RD @ (7, 824) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) -> [15000 ps] RD @ (7, 824) -> [ 7500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 7444) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) -> [15000 ps] RD @ (7, 824) -> [10000 ps] RD @ (3, 816) ->
[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6365) -> [10000 ps] ACT @ (7, 5285) -> [ 5000 ps] RD @ (3, 816) ->
[10000 ps] RD @ (7, 816) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) -> [15000 ps] RD @ (7, 816) -> [ 7500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 2048) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) -> [15000 ps] RD @ (7, 816) -> [10000 ps] RD @ (3, 816) ->
[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 969) -> [10000 ps] ACT @ (7, 16273) -> [ 5000 ps] RD @ (3, 816) ->
[10000 ps] RD @ (7, 808) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) -> [15000 ps] RD @ (7, 808) -> [ 7500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 13036) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) -> [15000 ps] RD @ (7, 808) -> [10000 ps] RD @ (3, 808) ->
[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11957) -> [10000 ps] ACT @ (7, 10877) -> [ 5000 ps] RD @ (3, 808) ->
[10000 ps] RD @ (7, 808) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) -> [15000 ps] RD @ (7, 808) -> [ 7500 ps] PRE @ (3) ->
[17500 ps] ACT @ (3, 7640) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) -> [15000 ps] RD @ (7, 808) -> [10000 ps] RD @ (3, 800) ->
[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6561) -> [10000 ps] ACT @ (7, 5481) -> [ 5000 ps] RD @ (3, 800) ->
[10000 ps] RD @ (7, 800) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3323) -> [10000 ps] ACT @ (7, 4402) ->
[15000 ps] RD @ (7, 800) -> [10000 ps] RD @ (3, 800) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2244) -> [15000 ps] RD @ (3, 800) ->
[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 85) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1165) -> [15000 ps] RD @ (3, 800) ->
[10000 ps] RD @ (7, 800) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15390) -> [10000 ps] ACT @ (3, 14311) ->
[ 5000 ps] RD @ (7, 792) -> [10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13232) -> [15000 ps] RD @ (3, 792) ->
[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11073) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12153) -> [15000 ps] RD @ (3, 792) ->
[10000 ps] RD @ (7, 792) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 9994) -> [10000 ps] ACT @ (3, 8915) ->
[ 5000 ps] RD @ (7, 792) -> [10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7836) -> [15000 ps] RD @ (3, 784) ->
[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5677) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6757) -> [15000 ps] RD @ (3, 784) ->
[10000 ps] RD @ (7, 784) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4598) -> [10000 ps] ACT @ (3, 3519) ->
[ 5000 ps] RD @ (7, 784) -> [10000 ps] RD @ (3, 784) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2440) -> [15000 ps] RD @ (3, 784) ->
[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 281) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) -> [15000 ps] RD @ (3, 784) ->
[10000 ps] RD @ (7, 784) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15586) -> [10000 ps] ACT @ (3, 14507) ->
[ 5000 ps] RD @ (7, 776) -> [10000 ps] RD @ (3, 776) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) -> [15000 ps] RD @ (3, 776) ->
[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11269) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12349) -> [15000 ps] RD @ (3, 776) ->
[10000 ps] RD @ (7, 776) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (7, 10190) ->
[10000 ps] ACT @ (3, 9111) -> [ 5000 ps] RD @ (7, 776) -> [10000 ps] RD @ (3, 776) -> [27500 ps] PRE @ (3) ->
--------------------------------
DONE TEST 2: RANDOM
Number of Operations: 2304
Time Started: 150900 ns
Time Done: 260510 ns
Average Rate: 47 ns/request
--------------------------------
[17500 ps] ACT @ (3, 8032) ->
[15000 ps] RD @ (3, 768) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6953) ->
[15000 ps] RD @ (3, 768) -> [10000 ps] RD @ (7, 768) -> FAILED: Address = 18962384, expected data = 8fa2201f8fa1121f8fa0041f8f9ef61f8f9dea1f8f9cdc1f8f9bce1f8f9ac01f8f99b21f8f98a41f8f97961f8f96881f8f957a1f8f946c1f8f93601f8f92521f, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 260640000.0 ps
------- SUMMARY -------
Number of Writes = 4608
Number of Reads = 4608
Number of Success = 4604
Number of Fails = 4
Number of Injected Errors = 4
$stop called at time : 261610 ns : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 456
run: Time (s): cpu = 00:00:17 ; elapsed = 00:57:38 . Memory (MB): peak = 2833.148 ; gain = 8.004 ; free physical = 174 ; free virtual = 23702
## quit
INFO: xsimkernel Simulation Memory Usage: 305696 KB (Peak: 371232 KB), Simulation CPU Usage: 2965430 ms
INFO: [Common 17-206] Exiting xsim at Wed Jul 5 17:44:52 2023...
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