211 lines
7.0 KiB
Verilog
211 lines
7.0 KiB
Verilog
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 05/13/2023 07:48:19 AM
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// Design Name:
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// Module Name: ddr3_micron_sim
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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`timescale 1ps / 1ps
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`define den8192Mb
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`define sg125
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`define x8
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module ddr3_micron_sim;
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`ifdef den1024Mb
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`include "1024Mb_ddr3_parameters.vh"
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`elsif den2048Mb
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`include "2048Mb_ddr3_parameters.vh"
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`elsif den4096Mb
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`include "4096Mb_ddr3_parameters.vh"
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`elsif den8192Mb
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`include "8192Mb_ddr3_parameters.vh"
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`else
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// NOTE: Intentionally cause a compile fail here to force the users
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// to select the correct component density before continuing
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ERROR: You must specify component density with +define+den____Mb.
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`endif
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reg i_controller_clk, i_ddr3_clk;
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reg i_rst_n;
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// Wishbone Interface
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reg i_wb_cyc; //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
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reg i_wb_stb; //request a transfer
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reg i_wb_we; //write-enable (1 = write, 0 = read)
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reg[$bits(ddr3_controller.i_wb_addr)-1:0] i_wb_addr; //burst-addressable {row,bank,col}
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reg[$bits(ddr3_controller.i_wb_data)-1:0] i_wb_data; //write data, for a 4:1 controller data width is 8 times the number of pins on the device
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wire o_wb_stall; //1 = busy, cannot accept requests
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wire o_wb_ack; //1 = read/write request has completed
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wire[$bits(ddr3_controller.o_wb_data)-1:0] o_wb_data; //read data, for a 4:1 controller data width is 8 times the number of pins on the device
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// PHY Interface to DDR3 Device
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wire ck_en; // CKE
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wire cs_n; // chip select signal
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wire odt; // on-die termination
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wire ras_n; // RAS#
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wire cas_n; // CAS#
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wire we_n; // WE#
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wire reset_n;
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wire[$bits(ddr3_top.o_ddr3_addr)-1:0] addr;
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wire[$bits(ddr3_top.o_ddr3_ba_addr)-1:0] ba_addr;
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wire[$bits(ddr3_top.io_ddr3_dq)-1:0] dq;
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wire[$bits(ddr3_top.io_ddr3_dqs)-1:0] dqs;
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wire[$bits(ddr3_top.io_ddr3_dqs_n)-1:0] dqs_n;
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wire o_ddr3_clk_p, o_ddr3_clk_n;
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// DDR3 Controller
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ddr3_top #(
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.ROW_BITS(14), //width of row address
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.COL_BITS(10), //width of column address
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.BA_BITS(3), //width of bank address
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.DQ_BITS(8), //width of DQ
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.CONTROLLER_CLK_PERIOD(5), //ns, period of clock input to this DDR3 controller module
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.DDR3_CLK_PERIOD(1.25), //ns, period of clock input to DDR3 RAM device
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.LANES(1), //8 lanes of DQ
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.OPT_LOWPOWER(1), //1 = low power, 0 = low logic
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.OPT_BUS_ABORT(1) //1 = can abort bus, 0 = no absort (i_wb_cyc will be ignored, ideal for an AXI implementation which cannot abort transaction)
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) ddr3_top
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(
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.i_controller_clk(i_controller_clk),
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.i_ddr3_clk(i_ddr3_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD, i_ddr3_clk has period of DDR3_CLK_PERIOD
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.i_ref_clk(i_controller_clk),
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.i_rst_n(i_rst_n), //200MHz input clock
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// Wishbone inputs
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.i_wb_cyc(i_wb_cyc), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
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.i_wb_stb(i_wb_stb), //request a transfer
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.i_wb_we(i_wb_we), //write-enable (1 = write, 0 = read)
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.i_wb_addr(i_wb_addr), //burst-addressable {row,bank,col}
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.i_wb_data(i_wb_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
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.i_wb_sel(), //byte strobe for write (1 = write the byte)
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.i_aux(), //for AXI-interface compatibility (given upon strobe)
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// Wishbone outputs
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.o_wb_stall(o_wb_stall), //1 = busy, cannot accept requests
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.o_wb_ack(o_wb_ack), //1 = read/write request has completed
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.o_wb_data(o_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
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// PHY Interface (to be added later)
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.o_ddr3_clk_p(o_ddr3_clk_p),
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.o_ddr3_clk_n(o_ddr3_clk_n),
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.o_ddr3_cke(ck_en), // CKE
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.o_ddr3_cs_n(cs_n), // chip select signal
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.o_ddr3_odt(odt), // on-die termination
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.o_ddr3_ras_n(ras_n), // RAS#
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.o_ddr3_cas_n(cas_n), // CAS#
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.o_ddr3_we_n(we_n), // WE#
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.o_ddr3_reset_n(reset_n),
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.o_ddr3_addr(addr),
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.o_ddr3_ba_addr(ba_addr),
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.io_ddr3_dq(dq),
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.io_ddr3_dqs(dqs),
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.io_ddr3_dqs_n(dqs_n)
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////////////////////////////////////
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);
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always #2500 i_controller_clk = !i_controller_clk;
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always #625 i_ddr3_clk = !i_ddr3_clk;
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initial begin
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i_controller_clk = 1;
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i_ddr3_clk = 1;
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end
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integer stored_time = 0;
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always begin
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if($rtoi($time/1000) != $rtoi(stored_time/1000)) begin
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$write("%t ", $time);
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stored_time = $time;
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end
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#10;
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end
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// DDR3 Device
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ddr3 ddr3_0(
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.rst_n(reset_n),
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.ck(o_ddr3_clk_p),
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.ck_n(o_ddr3_clk_n),
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.cke(ck_en),
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.cs_n(cs_n),
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.ras_n(ras_n),
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.cas_n(cas_n),
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.we_n(we_n),
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.dm_tdqs(),
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.ba(ba_addr),
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.addr(addr),
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.dq(dq),
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.dqs(dqs),
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.dqs_n(dqs_n),
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.tdqs_n(),
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.odt(odt)
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);
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initial begin
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@(negedge i_controller_clk)
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i_rst_n = 0;
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i_wb_cyc = 0;
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i_wb_stb = 0;
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i_wb_we = 0;
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i_wb_addr = 0;
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i_wb_data = 0;
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@(negedge i_controller_clk)
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i_rst_n = 1;
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wait(ddr3_controller.state_calibrate == ddr3_controller.DONE_CALIBRATE);
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// burst read 1
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wait(!o_wb_stall);
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@(negedge i_controller_clk);
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i_wb_cyc = 1;
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i_wb_stb = 1;
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i_wb_we = 1;
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i_wb_addr = 0;
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i_wb_data = "_ANGELO_";//64'h88_77_66_55_44_33_22_11;
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@(negedge i_controller_clk);
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i_wb_addr = 1;
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i_wb_data = "_JACOBO_";//64'h00_ff_ee_dd_cc_bb_aa_99;
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@(negedge i_controller_clk);
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i_wb_stb = 0;
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i_wb_data = 0;
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/*
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#100_000;
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wait(!o_wb_stall);
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i_wb_stb = 1;
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i_wb_data = 64'h88_77_66_55_44_33_22_11;
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@(negedge i_controller_clk);
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i_wb_data = 64'h00_ff_ee_dd_cc_bb_aa_99;
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@(negedge i_controller_clk);
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i_wb_data = 64'h88_77_66_55_44_33_22_11;
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@(negedge i_controller_clk);
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i_wb_data = 64'h00_ff_ee_dd_cc_bb_aa_99;
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@(negedge i_controller_clk);
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i_wb_data = 64'h88_77_66_55_44_33_22_11;
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@(negedge i_controller_clk);
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i_wb_data = 64'h00_ff_ee_dd_cc_bb_aa_99;
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i_wb_stb = 0;
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*/
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wait(!o_wb_stall);
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@(negedge i_controller_clk);
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i_wb_stb = 1;
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i_wb_we = 0;
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i_wb_addr = 0;
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//i_wb_data = 64'h88_77_66_55_44_33_22_11;
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@(negedge i_controller_clk);
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i_wb_addr = 1;
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@(negedge i_controller_clk);
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i_wb_stb = 0;
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//wait(ddr3_controller.o_wb_ack);
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#100_000;
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$stop;
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end
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endmodule
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