UberDDR3/testbench/ddr3_dimm_micron_sim_behav....

213 lines
12 KiB
XML

<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="ddr3_dimm_micron_sim_behav.wdb" id="1">
<top_modules>
<top_module name="ddr3_dimm_micron_sim" />
<top_module name="glbl" />
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="64,090.179 ns"></ZoomStartTime>
<ZoomEndTime time="64,220.813 ns"></ZoomEndTime>
<Cursor1Time time="64,130.000 ns"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="268"></NameColumnWidth>
<ValueColumnWidth column_width="66"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="44" />
<wvobject fp_name="divider869" type="divider">
<obj_property name="label">Clocks and Reset</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_rst_n">
<obj_property name="ElementShortName">i_rst_n</obj_property>
<obj_property name="ObjectShortName">i_rst_n</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_controller_clk">
<obj_property name="ElementShortName">i_controller_clk</obj_property>
<obj_property name="ObjectShortName">i_controller_clk</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_ddr3_clk">
<obj_property name="ElementShortName">i_ddr3_clk</obj_property>
<obj_property name="ObjectShortName">i_ddr3_clk</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_ddr3_clk_90">
<obj_property name="ElementShortName">i_ddr3_clk_90</obj_property>
<obj_property name="ObjectShortName">i_ddr3_clk_90</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_ref_clk">
<obj_property name="ElementShortName">i_ref_clk</obj_property>
<obj_property name="ObjectShortName">i_ref_clk</obj_property>
</wvobject>
<wvobject fp_name="divider869" type="divider">
<obj_property name="label">Calibration</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/calibration_state">
<obj_property name="ElementShortName">calibration_state[319:0]</obj_property>
<obj_property name="ObjectShortName">calibration_state[319:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/command_used">
<obj_property name="ElementShortName">command_used[23:0]</obj_property>
<obj_property name="ObjectShortName">command_used[23:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
<obj_property name="CustomSignalColor">#FFD700</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_ddr3_clk">
<obj_property name="ElementShortName">i_ddr3_clk</obj_property>
<obj_property name="ObjectShortName">i_ddr3_clk</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dq">
<obj_property name="ElementShortName">io_ddr3_dq[15:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dq[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs">
<obj_property name="ElementShortName">io_ddr3_dqs[1:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dqs[1:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/idelay_dqs">
<obj_property name="ElementShortName">idelay_dqs[1:0]</obj_property>
<obj_property name="ObjectShortName">idelay_dqs[1:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/lane">
<obj_property name="ElementShortName">lane[0:0]</obj_property>
<obj_property name="ObjectShortName">lane[0:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/instruction_address">
<obj_property name="ElementShortName">instruction_address[4:0]</obj_property>
<obj_property name="ObjectShortName">instruction_address[4:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/read_test_address_counter">
<obj_property name="ElementShortName">read_test_address_counter[25:0]</obj_property>
<obj_property name="ObjectShortName">read_test_address_counter[25:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/write_test_address_counter">
<obj_property name="ElementShortName">write_test_address_counter[31:0]</obj_property>
<obj_property name="ObjectShortName">write_test_address_counter[31:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/correct_read_data">
<obj_property name="ElementShortName">correct_read_data[31:0]</obj_property>
<obj_property name="ObjectShortName">correct_read_data[31:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/wrong_read_data">
<obj_property name="ElementShortName">wrong_read_data[31:0]</obj_property>
<obj_property name="ObjectShortName">wrong_read_data[31:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="divider869" type="divider">
<obj_property name="label">WIshbone Interface</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_controller_clk">
<obj_property name="ElementShortName">i_controller_clk</obj_property>
<obj_property name="ObjectShortName">i_controller_clk</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/calibration_state">
<obj_property name="ElementShortName">calibration_state[319:0]</obj_property>
<obj_property name="ObjectShortName">calibration_state[319:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/i_wb_cyc">
<obj_property name="ElementShortName">i_wb_cyc</obj_property>
<obj_property name="ObjectShortName">i_wb_cyc</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/i_wb_stb">
<obj_property name="ElementShortName">i_wb_stb</obj_property>
<obj_property name="ObjectShortName">i_wb_stb</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/i_wb_we">
<obj_property name="ElementShortName">i_wb_we</obj_property>
<obj_property name="ObjectShortName">i_wb_we</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/i_wb_addr">
<obj_property name="ElementShortName">i_wb_addr[25:0]</obj_property>
<obj_property name="ObjectShortName">i_wb_addr[25:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/i_wb_data">
<obj_property name="ElementShortName">i_wb_data[127:0]</obj_property>
<obj_property name="ObjectShortName">i_wb_data[127:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/i_wb_sel">
<obj_property name="ElementShortName">i_wb_sel[15:0]</obj_property>
<obj_property name="ObjectShortName">i_wb_sel[15:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_wb_stall">
<obj_property name="ElementShortName">o_wb_stall</obj_property>
<obj_property name="ObjectShortName">o_wb_stall</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_wb_ack">
<obj_property name="ElementShortName">o_wb_ack</obj_property>
<obj_property name="ObjectShortName">o_wb_ack</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_wb_data">
<obj_property name="ElementShortName">o_wb_data[127:0]</obj_property>
<obj_property name="ObjectShortName">o_wb_data[127:0]</obj_property>
</wvobject>
<wvobject fp_name="divider869" type="divider">
<obj_property name="label">DDR3 Interface</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_cke">
<obj_property name="ElementShortName">o_ddr3_cke</obj_property>
<obj_property name="ObjectShortName">o_ddr3_cke</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_cs_n">
<obj_property name="ElementShortName">o_ddr3_cs_n</obj_property>
<obj_property name="ObjectShortName">o_ddr3_cs_n</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_ras_n">
<obj_property name="ElementShortName">o_ddr3_ras_n</obj_property>
<obj_property name="ObjectShortName">o_ddr3_ras_n</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_cas_n">
<obj_property name="ElementShortName">o_ddr3_cas_n</obj_property>
<obj_property name="ObjectShortName">o_ddr3_cas_n</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_we_n">
<obj_property name="ElementShortName">o_ddr3_we_n</obj_property>
<obj_property name="ObjectShortName">o_ddr3_we_n</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_addr">
<obj_property name="ElementShortName">o_ddr3_addr[15:0]</obj_property>
<obj_property name="ObjectShortName">o_ddr3_addr[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_ba_addr">
<obj_property name="ElementShortName">o_ddr3_ba_addr[2:0]</obj_property>
<obj_property name="ObjectShortName">o_ddr3_ba_addr[2:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dq">
<obj_property name="ElementShortName">io_ddr3_dq[15:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dq[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs">
<obj_property name="ElementShortName">io_ddr3_dqs[1:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dqs[1:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs_n">
<obj_property name="ElementShortName">io_ddr3_dqs_n[1:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dqs_n[1:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_dm">
<obj_property name="ElementShortName">o_ddr3_dm[1:0]</obj_property>
<obj_property name="ObjectShortName">o_ddr3_dm[1:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_odt">
<obj_property name="ElementShortName">o_ddr3_odt</obj_property>
<obj_property name="ObjectShortName">o_ddr3_odt</obj_property>
</wvobject>
</wave_config>