859 lines
40 KiB
Systemverilog
859 lines
40 KiB
Systemverilog
//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 06/01/2023 08:50:24 AM
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// Design Name:
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// Module Name: ddr3_dimm_micron_sim
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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`timescale 1ps / 1ps
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`define den8192Mb
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`define sg125
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`define x16
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//`define USE_CLOCK_WIZARD
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`define TWO_LANES_x8
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//`define EIGHT_LANES_x8
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`define RAM_8Gb
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module ddr3_dimm_micron_sim;
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`ifdef den1024Mb
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`include "1024Mb_ddr3_parameters.vh"
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`elsif den2048Mb
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`include "2048Mb_ddr3_parameters.vh"
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`elsif den4096Mb
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`include "4096Mb_ddr3_parameters.vh"
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`elsif den8192Mb
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`include "8192Mb_ddr3_parameters.vh"
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`else
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// NOTE: Intentionally cause a compile fail here to force the users
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// to select the correct component density before continuing
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ERROR: You must specify component density with +define+den____Mb.
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`endif
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`ifdef TWO_LANES_x8
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localparam BYTE_LANES = 2,
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ODELAY_SUPPORTED = 0;
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`endif
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`ifdef EIGHT_LANES_x8
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localparam BYTE_LANES = 8,
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ODELAY_SUPPORTED = 1;;
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`endif
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localparam CONTROLLER_CLK_PERIOD = 10_000, //ps, period of clock input to this DDR3 controller module
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DDR3_CLK_PERIOD = 2500, //ps, period of clock input to DDR3 RAM device
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AUX_WIDTH = 16; // AUX lines
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reg i_controller_clk, i_ddr3_clk, i_ref_clk, i_ddr3_clk_90;
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reg i_rst_n;
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// Wishbone Interface
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reg i_wb_cyc; //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
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reg i_wb_stb; //request a transfer
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reg i_wb_we; //write-enable (1 = write, 0 = read)
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reg[$bits(ddr3_top.i_wb_addr)-1:0] i_wb_addr; //burst-addressable {row,bank,col}
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reg[$bits(ddr3_top.i_wb_data)-1:0] i_wb_data; //write data, for a 4:1 controller data width is 8 times the number of pins on the device
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reg[ddr3_top.wb_sel_bits - 1:0] i_wb_sel; //byte strobe for write (1 = write the byte)
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wire o_wb_stall; //1 = busy, cannot accept requests
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wire o_wb_ack; //1 = read/write request has completed
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wire[$bits(ddr3_top.o_wb_data)-1:0] o_wb_data; //read data, for a 4:1 controller data width is 8 times the number of pins on the device
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reg[$bits(ddr3_top.i_aux)-1:0] i_aux;
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wire[$bits(ddr3_top.o_aux)-1:0] o_aux;
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// PHY Interface to DDR3 Device
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wire[1:0] ck_en; // CKE
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wire[1:0] cs_n; // chip select signal
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wire[1:0] odt; // on-die termination
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wire ras_n; // RAS#
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wire cas_n; // CAS#
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wire we_n; // WE#
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wire reset_n;
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wire[$bits(ddr3_top.o_ddr3_addr)-1:0] addr;
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wire[$bits(ddr3_top.o_ddr3_ba_addr)-1:0] ba_addr;
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wire[$bits(ddr3_top.o_ddr3_dm)-1:0] ddr3_dm;
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wire[$bits(ddr3_top.io_ddr3_dq)-1:0] dq;
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wire[$bits(ddr3_top.io_ddr3_dqs)-1:0] dqs;
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wire[$bits(ddr3_top.io_ddr3_dqs_n)-1:0] dqs_n;
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wire o_ddr3_clk_p, o_ddr3_clk_n;
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integer index;
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// Wishbone 2 (PHY) inputs
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reg i_wb2_cyc; //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
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reg i_wb2_stb; //request a transfer
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reg i_wb2_we; //write-enable (1 = write, 0 = read)
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reg[$bits(ddr3_top.i_wb2_addr)-1:0] i_wb2_addr; //memory-mapped register to be accessed
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reg[$bits(ddr3_top.i_wb2_data)-1:0] i_wb2_data; //write data
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reg[$bits(ddr3_top.i_wb2_sel)-1:0] i_wb2_sel; //byte strobe for write (1 = write the byte)
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// Wishbone 2 (Controller) outputs
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wire o_wb2_stall; //1 = busy, cannot accept requests
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wire o_wb2_ack; //1 = read/write request has completed
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wire[$bits(ddr3_top.o_wb2_data)-1:0] o_wb2_data; //read data
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wire clk_locked;
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`ifdef USE_CLOCK_WIZARD
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// Use clock wizard
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reg i_clk;
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always #5_000 i_clk = !i_clk;
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initial begin
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i_clk = 0;
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end
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clk_wiz_0 mod1
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(
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// Clock out ports
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.clk_out1(i_controller_clk),
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.clk_out2(i_ddr3_clk),
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.clk_out3(i_ref_clk),
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.clk_out4(i_ddr3_clk_90),
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// Status and control signals
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.reset(!i_rst_n),
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.locked(clk_locked),
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// Clock in ports
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.clk_in1(i_clk)
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);
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`else
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assign clk_locked = 1;
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always #(CONTROLLER_CLK_PERIOD/2) i_controller_clk = !i_controller_clk;
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always #(DDR3_CLK_PERIOD/2) i_ddr3_clk = !i_ddr3_clk;
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always #2500 i_ref_clk = !i_ref_clk;
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initial begin //90 degree phase shifted ddr3_clk
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#(DDR3_CLK_PERIOD/4);
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while(1) begin
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#(DDR3_CLK_PERIOD/2) i_ddr3_clk_90 = !i_ddr3_clk_90;
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end
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end
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initial begin
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i_controller_clk = 1;
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i_ddr3_clk = 1;
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i_ref_clk = 1;
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i_ddr3_clk_90 = 1;
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end
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`endif
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// DDR3 Controller
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ddr3_top #(
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.CONTROLLER_CLK_PERIOD(CONTROLLER_CLK_PERIOD), //ps, clock period of the controller interface
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.DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
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.ROW_BITS(ROW_BITS), //width of row address
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.COL_BITS(COL_BITS), //width of column address
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.BA_BITS(BA_BITS), //width of bank address
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.BYTE_LANES(BYTE_LANES), //number of byte lanes of DDR3 RAM
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.AUX_WIDTH(AUX_WIDTH), //width of aux line (must be >= 4)
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.MICRON_SIM(1), //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
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.ODELAY_SUPPORTED(ODELAY_SUPPORTED), //set to 1 if ODELAYE2 is supported
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.SECOND_WISHBONE(0) //set to 1 if 2nd wishbone for debugging is needed
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) ddr3_top
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(
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//clock and reset
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.i_controller_clk(i_controller_clk),
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.i_ddr3_clk(i_ddr3_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD, i_ddr3_clk has period of DDR3_CLK_PERIOD
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.i_ref_clk(i_ref_clk),
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.i_ddr3_clk_90(i_ddr3_clk_90),
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.i_rst_n(i_rst_n && clk_locked),
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// Wishbone inputs
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.i_wb_cyc(i_wb_cyc), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
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.i_wb_stb(i_wb_stb), //request a transfer
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.i_wb_we(i_wb_we), //write-enable (1 = write, 0 = read)
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.i_wb_addr(i_wb_addr), //burst-addressable {row,bank,col}
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.i_wb_data(i_wb_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
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.i_wb_sel(i_wb_sel), //byte strobe for write (1 = write the byte)
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.i_aux(i_aux), //for AXI-interface compatibility (given upon strobe)
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// Wishbone outputs
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.o_wb_stall(o_wb_stall), //1 = busy, cannot accept requests
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.o_wb_ack(o_wb_ack), //1 = read/write request has completed
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.o_wb_data(o_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
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.o_aux(o_aux),
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// Wishbone 2 (PHY) inputs
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.i_wb2_cyc(i_wb2_cyc), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
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.i_wb2_stb(i_wb2_stb), //request a transfer
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.i_wb2_we(i_wb2_we), //write-enable (1 = write, 0 = read)
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.i_wb2_addr(i_wb2_addr), //burst-addressable {row,bank,col}
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.i_wb2_data(i_wb2_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
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.i_wb2_sel(i_wb2_sel), //byte strobe for write (1 = write the byte)
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// Wishbone 2 (Controller) outputs
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.o_wb2_stall(o_wb2_stall), //1 = busy, cannot accept requests
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.o_wb2_ack(o_wb2_ack), //1 = read/write request has completed
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.o_wb2_data(o_wb2_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
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// PHY Interface (to be added later)
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.o_ddr3_clk_p(o_ddr3_clk_p),
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.o_ddr3_clk_n(o_ddr3_clk_n),
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.o_ddr3_cke(ck_en[0]), // CKE
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.o_ddr3_cs_n(cs_n[0]), // chip select signal
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.o_ddr3_odt(odt[0]), // on-die termination
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.o_ddr3_ras_n(ras_n), // RAS#
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.o_ddr3_cas_n(cas_n), // CAS#
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.o_ddr3_we_n(we_n), // WE#
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.o_ddr3_reset_n(reset_n),
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.o_ddr3_addr(addr),
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.o_ddr3_ba_addr(ba_addr),
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.io_ddr3_dq(dq),
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.io_ddr3_dqs(dqs),
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.io_ddr3_dqs_n(dqs_n),
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.o_ddr3_dm(ddr3_dm)
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////////////////////////////////////
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);
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`ifdef TWO_LANES_x8
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// 1 lane DDR3
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ddr3 ddr3_0(
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.rst_n(reset_n),
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.ck(o_ddr3_clk_p),
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.ck_n(o_ddr3_clk_n),
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.cke(ck_en[0]),
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.cs_n(cs_n[0]),
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.ras_n(ras_n),
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.cas_n(cas_n),
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.we_n(we_n),
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.dm_tdqs(ddr3_dm),
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.ba(ba_addr),
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.addr(addr),
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.dq(dq),
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.dqs(dqs),
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.dqs_n(dqs_n),
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.tdqs_n(),
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.odt(odt[0])
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);
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assign ck_en[1]=0,
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cs_n[1]=1,
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odt[1]=0;
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`endif
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`ifdef EIGHT_LANES_x8
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// DDR3 Device
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ddr3_module ddr3_module(
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.reset_n(reset_n),
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.ck(o_ddr3_clk_p),
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.ck_n(o_ddr3_clk_n),
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.cke(ck_en),
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.s_n(cs_n),
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.ras_n(ras_n),
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.cas_n(cas_n),
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.we_n(we_n),
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.ba(ba_addr),
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.addr(addr),
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.odt(odt),
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.dqs({ddr3_dm[0], ddr3_dm,ddr3_dm[0],dqs}), //ddr3_module uses last 8 MSB [16:9] as datamask
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.dqs_n(dqs_n),
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.dq(dq)
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);
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`endif
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reg[511:0] write_data = 0, expected_read_data = 0;
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integer address = 0, read_address = 0, address_inner = 0;
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integer start_address = 0, start_read_address;
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integer number_of_writes=0, number_of_reads=0, number_of_successful=0, number_of_failed=0;
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integer random_start = $random; //starting seed for random accesss
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integer number_of_injected_errors = 0;
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integer number_of_op = 0;
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integer time_started = 0;
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localparam MAX_READS = (2**COL_BITS)*(2**BA_BITS + 1)/8; //1 row = 2**(COL_BITS) addresses/8 burst = 128 words per row. Times 8 to pass all 8 banks
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initial begin
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//toggle reset for 1 slow clk
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@(posedge i_controller_clk) begin
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i_rst_n <= 0;
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// Wishbone 1
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i_wb_cyc <= 1;
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i_wb_stb <= 0;
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i_wb_we <= 0;
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i_wb_sel <= -1; //write to all lanes
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i_aux <= 0;
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i_wb_addr <= 0;
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i_wb_data <= 0;
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// Wishbone 2
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i_wb2_cyc <= 0; //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
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i_wb2_stb <= 0; //request a transfer
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i_wb2_we <= 0; //write-enable (1 = write, 0 = read)
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i_wb2_addr <= 0; //memory-mapped register to be accessed
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i_wb2_data <= 0; //write data
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i_wb2_sel <= 0;
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end
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@(posedge i_controller_clk) begin
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i_rst_n <= 1;
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end
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wait(ddr3_top.ddr3_controller_inst.state_calibrate == ddr3_top.ddr3_controller_inst.DONE_CALIBRATE);
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// test 1 phase 1: Write random word sequentially
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// write to row 1
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number_of_op <= 0;
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time_started <= $time;
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number_of_injected_errors <= 0;
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start_address <= 0;
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#1; //just to make sure the non-blocking are assignments are all over
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address <= start_address;
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#1; //just to make sure the non-blocking are assignments are all over
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while(address < start_address + MAX_READS*($bits(ddr3_top.i_wb_data)/32)) begin
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@(posedge i_controller_clk) begin
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if(!i_wb_stb || !o_wb_stall) begin
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for (index = 0; index < $bits(ddr3_top.i_wb_data)/32; index = index + 1) begin
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i_wb_data[index*32 +: 32] <= $random(address + index); //each $random only has 32 bits
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end
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i_wb_cyc <= 1;
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i_wb_stb <= 1;
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i_wb_we <= 1;
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i_aux <= 1;
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i_wb_addr <= address/ ($bits(ddr3_top.i_wb_data)/32);
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if(address == start_address + ($bits(ddr3_top.i_wb_data)/32)*(MAX_READS-1)) begin //inject error at last row
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number_of_injected_errors <= number_of_injected_errors + 1;
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i_wb_data <= 64'h123456789;
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end
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//$display("Write: Address = %0d, Data = %h", i_wb_addr, i_wb_data);
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number_of_writes <= number_of_writes + 1;
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number_of_op <= number_of_op + 1;
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address <= address + ($bits(ddr3_top.i_wb_data)/32);
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end
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end
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#1; //just to make sure the non-blocking are assignments are all over
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end
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//Read sequentially
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address <= start_address;
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#1; //just to make sure the non-blocking are assignments are all over
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while(address < start_address + MAX_READS*($bits(ddr3_top.i_wb_data)/32)) begin
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@(posedge i_controller_clk) begin
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if(!i_wb_stb || !o_wb_stall) begin
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i_wb_cyc <= 1;
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i_wb_stb <= 1;
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i_wb_we <= 0;
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i_aux <= 0;
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i_wb_addr <= address/ ($bits(ddr3_top.i_wb_data)/32);
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//$display("Read: Address = %0d", i_wb_addr);
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number_of_reads <= number_of_reads + 1;
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number_of_op <= number_of_op + 1;
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address <= address + ($bits(ddr3_top.i_wb_data)/32);
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end
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end
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#1; //just to make sure the non-blocking are assignments are all over
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end
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/*while(i_wb_stb) begin
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@(posedge i_controller_clk) begin
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if (!o_wb_stall) i_wb_stb <= 1'b0;
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end
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end*/
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$display("\n--------------------------------\nDONE TEST 1: FIRST ROW\nNumber of Operations: %0d\nTime Started: %0d ns\nTime Done: %0d ns\nAverage Rate: %0d ns/request\n--------------------------------\n\n",
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number_of_op,time_started/1000, $time/1000, ($time-time_started)/(number_of_op*1000));
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// #100_000;
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/*@(posedge i_controller_clk) begin
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// write to middle row
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start_address <= ((2**COL_BITS)*(2**ROW_BITS)*(2**BA_BITS)/2)*($bits(ddr3_top.i_wb_data)/32)/8; //start at the middle row
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end*/
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#1; //just to make sure the non-blocking are assignments are all over
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start_address <= ((2**COL_BITS)*(2**ROW_BITS)*(2**BA_BITS)/2)*($bits(ddr3_top.i_wb_data)/32)/8; //start at the middle row
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#1;
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address <= start_address;
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number_of_op <= 0;
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time_started <= $time;
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#1; //just to make sure the non-blocking are assignments are all over
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while(address < start_address + MAX_READS*($bits(ddr3_top.i_wb_data)/32)) begin
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@(posedge i_controller_clk) begin
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if(!i_wb_stb || !o_wb_stall) begin
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for (index = 0; index < $bits(ddr3_top.i_wb_data)/32; index = index + 1) begin
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i_wb_data[index*32 +: 32] <= $random(address + index); //each $random only has 32 bits
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end
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i_wb_cyc <= 1;
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i_wb_stb <= 1;
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i_wb_we <= 1;
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i_aux <= 1;
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i_wb_addr <= address/ ($bits(ddr3_top.i_wb_data)/32);
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if(address == start_address + ($bits(ddr3_top.i_wb_data)/32)*(MAX_READS-1)) begin //inject error at last row
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number_of_injected_errors <= number_of_injected_errors + 1;
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i_wb_data <= 64'h123456789;
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end
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//$display("Write: Address = %0d, Data = %h", i_wb_addr, i_wb_data);
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number_of_writes <= number_of_writes + 1;
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number_of_op <= number_of_op + 1;
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address <= address + ($bits(ddr3_top.i_wb_data)/32);
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end
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end
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#1; //just to make sure the non-blocking are assignments are all over
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end
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// Read sequentially
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address <= start_address;
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#1; //just to make sure the non-blocking are assignments are all over
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while(address < start_address + MAX_READS*($bits(ddr3_top.i_wb_data)/32)) begin
|
|
@(posedge i_controller_clk) begin
|
|
if(!i_wb_stb || !o_wb_stall) begin
|
|
i_wb_cyc <= 1;
|
|
i_wb_stb <= 1;
|
|
i_wb_we <= 0;
|
|
i_aux <= 0;
|
|
i_wb_addr <= address/ ($bits(ddr3_top.i_wb_data)/32);
|
|
//$display("Read: Address = %0d", i_wb_addr);
|
|
number_of_reads <= number_of_reads + 1;
|
|
number_of_op <= number_of_op + 1;
|
|
address <= address + ($bits(ddr3_top.i_wb_data)/32);
|
|
end
|
|
end
|
|
#1; //just to make sure the non-blocking are assignments are all over
|
|
end
|
|
/*while(i_wb_stb) begin
|
|
@(posedge i_controller_clk) begin
|
|
if (!o_wb_stall) i_wb_stb <= 1'b0;
|
|
end
|
|
end*/
|
|
$display("\n--------------------------------\nDONE TEST 1: MIDDLE ROW\nNumber of Operations: %0d\nTime Started: %0d ns\nTime Done: %0d ns\nAverage Rate: %0d ns/request\n--------------------------------\n\n",
|
|
number_of_op,time_started/1000, $time/1000, ($time-time_started)/(number_of_op*1000));
|
|
//#100_000;
|
|
|
|
|
|
// write to last row (then go back to first row)
|
|
start_address <= ((2**COL_BITS)*(2**ROW_BITS)*(2**BA_BITS) - (2**COL_BITS)*(2**BA_BITS))*($bits(ddr3_top.i_wb_data)/32)/8; //start at the last row
|
|
#1; //just to make sure the non-blocking are assignments are all over
|
|
address <= start_address;
|
|
number_of_op <= 0;
|
|
time_started <= $time;
|
|
#1; //just to make sure the non-blocking are assignments are all over
|
|
while(address < start_address + MAX_READS*($bits(ddr3_top.i_wb_data)/32)) begin
|
|
@(posedge i_controller_clk) begin
|
|
if(!i_wb_stb || !o_wb_stall) begin
|
|
for (index = 0; index < $bits(ddr3_top.i_wb_data)/32; index = index + 1) begin
|
|
i_wb_data[index*32 +: 32] <= $random(address + index); //each $random only has 32 bits
|
|
end
|
|
i_wb_cyc <= 1;
|
|
i_wb_stb <= 1;
|
|
i_wb_we <= 1;
|
|
i_aux <= 1;
|
|
i_wb_addr <= address/ ($bits(ddr3_top.i_wb_data)/32);
|
|
if(address == start_address + ($bits(ddr3_top.i_wb_data)/32)*(MAX_READS-1)) begin//inject error at last row
|
|
number_of_injected_errors <= number_of_injected_errors + 1;
|
|
i_wb_data <= 64'h123456789;
|
|
end
|
|
//$display("Write: Address = %0d, Data = %h", i_wb_addr, i_wb_data);
|
|
number_of_writes <= number_of_writes + 1;
|
|
number_of_op <= number_of_op + 1;
|
|
address <= address + ($bits(ddr3_top.i_wb_data)/32);
|
|
end
|
|
end
|
|
#1; //just to make sure the non-blocking are assignments are all over
|
|
end
|
|
|
|
// Read sequentially
|
|
address <= start_address;
|
|
#1; //just to make sure the non-blocking are assignments are all over
|
|
while(address < start_address + MAX_READS*($bits(ddr3_top.i_wb_data)/32)) begin
|
|
@(posedge i_controller_clk) begin
|
|
if(!i_wb_stb || !o_wb_stall) begin
|
|
i_wb_cyc <= 1;
|
|
i_wb_stb <= 1;
|
|
i_wb_we <= 0;
|
|
i_aux <= 0;
|
|
i_wb_addr <= address/ ($bits(ddr3_top.i_wb_data)/32);
|
|
//$display("Read: Address = %0d", i_wb_addr);
|
|
number_of_reads <= number_of_reads + 1;
|
|
number_of_op <= number_of_op + 1;
|
|
address <= address + ($bits(ddr3_top.i_wb_data)/32);
|
|
end
|
|
end
|
|
#1; //just to make sure the non-blocking are assignments are all over
|
|
end
|
|
/*while(i_wb_stb) begin
|
|
@(posedge i_controller_clk) begin
|
|
if (!o_wb_stall) i_wb_stb <= 1'b0;
|
|
end
|
|
end*/
|
|
$display("\n--------------------------------\nDONE TEST 1: LAST ROW\nNumber of Operations: %0d\nTime Started: %0d ns\nTime Done: %0d ns\nAverage Rate: %0d ns/request\n--------------------------------\n\n",
|
|
number_of_op,time_started/1000, $time/1000, ($time-time_started)/(number_of_op*1000));
|
|
//#100_000;
|
|
|
|
|
|
|
|
// Test 2:Random Access
|
|
// write randomly
|
|
address <= random_start; //this will just be used as the seed to generate a random number
|
|
number_of_op <= 0;
|
|
time_started <= $time;
|
|
#1; //just to make sure the non-blocking are assignments are all over
|
|
while(address < random_start + MAX_READS*($bits(ddr3_top.i_wb_data)/32)) begin
|
|
@(posedge i_controller_clk) begin
|
|
if(!i_wb_stb || !o_wb_stall) begin
|
|
for (index = 0; index < $bits(ddr3_top.i_wb_data)/32; index = index + 1) begin
|
|
i_wb_data[index*32 +: 32] <= $random(address + index); //each $random only has 32 bits
|
|
end
|
|
i_wb_cyc <= 1;
|
|
i_wb_stb <= 1;
|
|
i_wb_we <= 1;
|
|
i_aux <= 1;
|
|
i_wb_addr <= $random(~address); //write at random address
|
|
if(address == random_start + ($bits(ddr3_top.i_wb_data)/32)*(MAX_READS-1)) begin //inject error at last row
|
|
number_of_injected_errors <= number_of_injected_errors + 1;
|
|
i_wb_data <= 64'h123456789;
|
|
end
|
|
//$display("Write: Address = %0d, Data = %h", i_wb_addr, i_wb_data);
|
|
number_of_writes <= number_of_writes + 1;
|
|
number_of_op <= number_of_op + 1;
|
|
address <= address + ($bits(ddr3_top.i_wb_data)/32);
|
|
end
|
|
end
|
|
#1; //just to make sure the non-blocking are assignments are all over
|
|
end
|
|
|
|
// Read sequentially
|
|
// Read the random words written at the random addresses
|
|
address <= random_start;
|
|
#1; //just to make sure the non-blocking are assignments are all over
|
|
while(address < random_start + MAX_READS*($bits(ddr3_top.i_wb_data)/32)) begin
|
|
@(posedge i_controller_clk) begin
|
|
if(!i_wb_stb || !o_wb_stall) begin
|
|
i_wb_cyc <= 1;
|
|
i_wb_stb <= 1;
|
|
i_wb_we <= 0;
|
|
i_aux <= 0;
|
|
i_wb_addr <= $random(~address);
|
|
//$display("Read: Address = %0d", i_wb_addr);
|
|
number_of_reads <= number_of_reads + 1;
|
|
number_of_op <= number_of_op + 1;
|
|
address <= address + ($bits(ddr3_top.i_wb_data)/32);
|
|
end
|
|
end
|
|
end
|
|
while(i_wb_stb) begin
|
|
@(posedge i_controller_clk) begin
|
|
if (!o_wb_stall) i_wb_stb <= 1'b0;
|
|
end
|
|
end
|
|
$display("\n--------------------------------\nDONE TEST 2: RANDOM\nNumber of Operations: %0d\nTime Started: %0d ns\nTime Done: %0d ns\nAverage Rate: %0d ns/request\n--------------------------------\n\n",
|
|
number_of_op,time_started/1000, $time/1000, ($time-time_started)/(number_of_op*1000));
|
|
|
|
#100_000;
|
|
// Test 3: Read from wishbone 2 (PHY)
|
|
// Wishbone 2
|
|
i_wb2_cyc <= 0; //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
|
|
i_wb2_stb <= 0; //request a transfer
|
|
i_wb2_we <= 0; //write-enable (1 = write, 0 = read)
|
|
i_wb2_addr <= 0; //memory-mapped register to be accessed
|
|
i_wb2_data <= 0; //write data
|
|
i_wb2_sel <= 0;
|
|
address <= 0;
|
|
address_inner <= 0;
|
|
#1; //just to make sure the non-blocking are assignments are all over
|
|
while(address < 9 ) begin
|
|
if(address <= 3) begin
|
|
while(address_inner < 7) begin
|
|
@(posedge i_controller_clk) begin
|
|
if(!i_wb2_stb || !o_wb2_stall) begin
|
|
i_wb2_cyc <= 1;
|
|
i_wb2_stb <= 1; //0,1,2,3,4,5,6,7,8
|
|
i_wb2_we <= 0;
|
|
i_wb2_addr <= address | address_inner << 4;
|
|
address_inner <= address_inner + 1;
|
|
end
|
|
end
|
|
#1;
|
|
end //end of while
|
|
|
|
@(posedge i_controller_clk) begin
|
|
if(!i_wb2_stb || !o_wb2_stall) begin
|
|
i_wb2_cyc <= 1;
|
|
i_wb2_stb <= 1; //0,1,2,3,4,5,6,7,8
|
|
i_wb2_we <= 0;
|
|
i_wb2_addr <= address | address_inner << 4;
|
|
address <= address + 1;
|
|
address_inner <= 0;
|
|
end
|
|
end //end of @posedge
|
|
end //end of if(address <= 3)
|
|
|
|
else begin
|
|
@(posedge i_controller_clk) begin
|
|
if(!i_wb2_stb || !o_wb2_stall) begin
|
|
i_wb2_cyc <= 1;
|
|
i_wb2_stb <= 1;
|
|
i_wb2_we <= 0;
|
|
i_wb2_addr <= address;
|
|
address <= address + 1;
|
|
end
|
|
end
|
|
end
|
|
|
|
#1; //just to make sure the non-blocking are assignments are all over
|
|
end
|
|
while(i_wb2_stb) begin
|
|
@(posedge i_controller_clk) begin
|
|
if (!o_wb2_stall) i_wb2_stb <= 1'b0;
|
|
end
|
|
end
|
|
|
|
#1000_000;
|
|
$display("\n\n------- SUMMARY -------\nNumber of Writes = %0d\nNumber of Reads = %0d\nNumber of Success = %0d\nNumber of Fails = %0d\nNumber of Injected Errors = %0d\n",
|
|
number_of_writes, number_of_reads,number_of_successful, number_of_failed, number_of_injected_errors);
|
|
$display("\n\nTEST CALIBRATION\n[-]: write_test_address_counter = %0d", ddr3_top.ddr3_controller_inst.write_test_address_counter);
|
|
$display("[-]: read_test_address_counter = %0d", ddr3_top.ddr3_controller_inst.read_test_address_counter);
|
|
$display("[-]: correct_read_data = %0d", ddr3_top.ddr3_controller_inst.correct_read_data);
|
|
$display("[-]: wrong_read_data = %0d", ddr3_top.ddr3_controller_inst.wrong_read_data);
|
|
$stop;
|
|
end
|
|
|
|
//check read data
|
|
initial begin
|
|
start_read_address = 0; //start at first row
|
|
read_address = start_read_address;
|
|
|
|
while(read_address < start_read_address + MAX_READS*($bits(ddr3_top.i_wb_data)/32)) begin
|
|
@(posedge i_controller_clk);
|
|
if(o_wb_ack && ddr3_top.ddr3_controller_inst.state_calibrate == ddr3_top.ddr3_controller_inst.DONE_CALIBRATE && o_aux == 0) begin
|
|
for (index = 0; index < $bits(ddr3_top.i_wb_data)/32; index = index + 1) begin
|
|
expected_read_data[index*32 +: 32] = $random(read_address + index); //each $random only has 32 bits
|
|
end
|
|
if(expected_read_data == o_wb_data) begin
|
|
//$display("SUCCESSFUL: Address = %0d, expected data = %h, read data = %h", (read_address/($bits(ddr3_top.i_wb_data)/32)), expected_read_data, o_wb_data);
|
|
number_of_successful = number_of_successful + 1;
|
|
end
|
|
else begin
|
|
$display("FAILED: Address = %0d, expected data = %h, read data = %h @ %t", (read_address/($bits(ddr3_top.i_wb_data)/32)), expected_read_data, o_wb_data, $time);
|
|
number_of_failed = number_of_failed + 1;
|
|
end
|
|
read_address = read_address + ($bits(ddr3_top.i_wb_data)/32);
|
|
end
|
|
end
|
|
|
|
start_read_address = ((2**COL_BITS)*(2**ROW_BITS)*(2**BA_BITS)/2)*($bits(ddr3_top.i_wb_data)/32)/8; //start at the middle row
|
|
read_address = start_read_address;
|
|
while(read_address < start_read_address + MAX_READS*($bits(ddr3_top.i_wb_data)/32)) begin
|
|
@(posedge i_controller_clk);
|
|
if(o_wb_ack && ddr3_top.ddr3_controller_inst.state_calibrate == ddr3_top.ddr3_controller_inst.DONE_CALIBRATE && o_aux == 0) begin
|
|
for (index = 0; index < $bits(ddr3_top.i_wb_data)/32; index = index + 1) begin
|
|
expected_read_data[index*32 +: 32] = $random(read_address + index); //each $random only has 32 bits
|
|
end
|
|
if(expected_read_data == o_wb_data) begin
|
|
//$display("SUCCESSFUL: Address = %0d, expected data = %h, read data = %h", (read_address/($bits(ddr3_top.i_wb_data)/32)), expected_read_data, o_wb_data);
|
|
number_of_successful = number_of_successful + 1;
|
|
end
|
|
else begin
|
|
$display("FAILED: Address = %0d, expected data = %h, read data = %h @ %t", (read_address/($bits(ddr3_top.i_wb_data)/32)), expected_read_data, o_wb_data, $time);
|
|
number_of_failed = number_of_failed + 1;
|
|
end
|
|
read_address = read_address + ($bits(ddr3_top.i_wb_data)/32);
|
|
end
|
|
end
|
|
|
|
start_read_address = ((2**COL_BITS)*(2**ROW_BITS)*(2**BA_BITS) - (2**COL_BITS)*(2**BA_BITS))*($bits(ddr3_top.i_wb_data)/32)/8; //start at the last row
|
|
read_address = start_read_address;
|
|
while(read_address < start_read_address + MAX_READS*($bits(ddr3_top.i_wb_data)/32)) begin
|
|
@(posedge i_controller_clk);
|
|
if(o_wb_ack && ddr3_top.ddr3_controller_inst.state_calibrate == ddr3_top.ddr3_controller_inst.DONE_CALIBRATE && o_aux == 0) begin
|
|
for (index = 0; index < $bits(ddr3_top.i_wb_data)/32; index = index + 1) begin
|
|
expected_read_data[index*32 +: 32] = $random(read_address + index); //each $random only has 32 bits
|
|
end
|
|
if(expected_read_data == o_wb_data) begin
|
|
//$display("SUCCESSFUL: Address = %0d, expected data = %h, read data = %h", (read_address/($bits(ddr3_top.i_wb_data)/32)), expected_read_data, o_wb_data);
|
|
number_of_successful = number_of_successful + 1;
|
|
end
|
|
else begin
|
|
$display("FAILED: Address = %0d, expected data = %h, read data = %h @ %t", (read_address/($bits(ddr3_top.i_wb_data)/32)), expected_read_data, o_wb_data, $time);
|
|
number_of_failed = number_of_failed + 1;
|
|
end
|
|
read_address = read_address + ($bits(ddr3_top.i_wb_data)/32);
|
|
end
|
|
end
|
|
|
|
// Read the random words written at the random addresses//read the random words at random addresses
|
|
read_address = random_start;
|
|
while(read_address < random_start + MAX_READS*($bits(ddr3_top.i_wb_data)/32)) begin
|
|
@(posedge i_controller_clk);
|
|
if(o_wb_ack && ddr3_top.ddr3_controller_inst.state_calibrate == ddr3_top.ddr3_controller_inst.DONE_CALIBRATE && o_aux == 0) begin
|
|
for (index = 0; index < $bits(ddr3_top.i_wb_data)/32; index = index + 1) begin
|
|
expected_read_data[index*32 +: 32] = $random(read_address + index); //each $random only has 32 bits
|
|
end
|
|
if(expected_read_data == o_wb_data) begin
|
|
//$display("SUCCESSFUL: Address = %0d, expected data = %h, read data = %h", (read_address/($bits(ddr3_top.i_wb_data)/32)), expected_read_data, o_wb_data);
|
|
number_of_successful = number_of_successful + 1;
|
|
end
|
|
else begin
|
|
$display("FAILED: Address = %0d, expected data = %h, read data = %h @ %t", (read_address/($bits(ddr3_top.i_wb_data)/32)), expected_read_data, o_wb_data, $time);
|
|
number_of_failed = number_of_failed + 1;
|
|
end
|
|
read_address = read_address + ($bits(ddr3_top.i_wb_data)/32);
|
|
end
|
|
end
|
|
end
|
|
|
|
//receive wb2 data
|
|
integer wb2_addr=0, wb2_addr_lane=0;
|
|
initial begin
|
|
while(wb2_addr <= 9) begin
|
|
@(posedge i_controller_clk);
|
|
if(o_wb2_ack) begin
|
|
case(wb2_addr)
|
|
0: begin
|
|
if(wb2_addr_lane == 0) $display("\n\nWishbone 2 (PHY) Test:");
|
|
$display("[0]: odelay_data_cntvaluein[%0d] = %0d", wb2_addr_lane, o_wb2_data);
|
|
if(wb2_addr_lane < 7) begin
|
|
wb2_addr_lane = wb2_addr_lane + 1;
|
|
end
|
|
else begin
|
|
wb2_addr = wb2_addr + 1;
|
|
wb2_addr_lane = 0;
|
|
end
|
|
end
|
|
1: begin
|
|
$display("[1]: odelay_dqs_cntvaluein[%0d] = %0d", wb2_addr_lane, o_wb2_data);
|
|
if(wb2_addr_lane < 7) begin
|
|
wb2_addr_lane = wb2_addr_lane + 1;
|
|
end
|
|
else begin
|
|
wb2_addr = wb2_addr + 1;
|
|
wb2_addr_lane = 0;
|
|
end
|
|
end
|
|
2: begin
|
|
$display("[2]: idelay_data_cntvaluein[%0d] = %0d", wb2_addr_lane, o_wb2_data);
|
|
if(wb2_addr_lane < 7) begin
|
|
wb2_addr_lane = wb2_addr_lane + 1;
|
|
end
|
|
else begin
|
|
wb2_addr = wb2_addr + 1;
|
|
wb2_addr_lane = 0;
|
|
end
|
|
end
|
|
3: begin
|
|
$display("[3]: idelay_dqs_cntvaluein[%0d] = %0d", wb2_addr_lane, o_wb2_data);
|
|
if(wb2_addr_lane < 7) begin
|
|
wb2_addr_lane = wb2_addr_lane + 1;
|
|
end
|
|
else begin
|
|
wb2_addr = wb2_addr + 1;
|
|
wb2_addr_lane = 0;
|
|
end
|
|
end
|
|
4: begin
|
|
$display("[4]: i_phy_idelayctrl_rdy = %0d", o_wb2_data[0]);
|
|
$display("[4]: state_calibrate = %0d", o_wb2_data[5:1]);
|
|
$display("[4]: instruction_address = %0d", o_wb2_data[10:6]);
|
|
$display("[4]: added_read_pipe_max = %0d", o_wb2_data[14:11]);
|
|
wb2_addr = wb2_addr + 1;
|
|
end
|
|
5: begin
|
|
$display("[5]: added_read_pipe[0] = %0d", o_wb2_data[3:0]);
|
|
$display("[5]: added_read_pipe[1] = %0d", o_wb2_data[7:4]);
|
|
$display("[5]: added_read_pipe[2] = %0d", o_wb2_data[11:8]);
|
|
$display("[5]: added_read_pipe[3] = %0d", o_wb2_data[15:12]);
|
|
$display("[5]: added_read_pipe[4] = %0d", o_wb2_data[19:16]);
|
|
$display("[5]: added_read_pipe[5] = %0d", o_wb2_data[23:20]);
|
|
$display("[5]: added_read_pipe[6] = %0d", o_wb2_data[27:24]);
|
|
$display("[5]: added_read_pipe[7] = %0d", o_wb2_data[31:28]);
|
|
wb2_addr = wb2_addr + 1;
|
|
end
|
|
6: begin
|
|
$display("[6]: dqs_store = %b_%b_%b_%b", o_wb2_data[31:24], o_wb2_data[23:16], o_wb2_data[15:8], o_wb2_data[7:0]);
|
|
wb2_addr = wb2_addr + 1;
|
|
end
|
|
7: begin
|
|
$display("[7]: i_phy_iserdes_bitslip_reference = %b_%b_%b_%b", o_wb2_data[31:24], o_wb2_data[23:16], o_wb2_data[15:8], o_wb2_data[7:0]);
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|
wb2_addr = wb2_addr + 1;
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|
end
|
|
8: begin
|
|
$display("[8]: read_data_store = %h", o_wb2_data);
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|
wb2_addr = wb2_addr + 1;
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|
end
|
|
9: begin
|
|
$display("[9]: write_pattern = %h", o_wb2_data);
|
|
wb2_addr = wb2_addr + 1;
|
|
end
|
|
endcase
|
|
|
|
end
|
|
end
|
|
|
|
end
|
|
|
|
reg[8*40-1:0] calibration_state; //store command in ASCII
|
|
reg[8*3-1:0] command_used; //store command in ASCII
|
|
reg[3*8*2-1:0] prev_cmd; //stores previous 2 commands
|
|
reg[32*2-1:0] prev_time;
|
|
reg[31:0] time_now;
|
|
reg[3:0] repeats = 0;
|
|
//display commands issued
|
|
always @(posedge o_ddr3_clk_p) begin
|
|
if(!cs_n[0]) begin //command is center-aligned to positive edge of clock, a valid command always has low cs_n
|
|
case({cs_n[0], ras_n, cas_n, we_n})
|
|
4'b0000: command_used = "MRS";
|
|
4'b0001: command_used = "REF";
|
|
4'b0010: command_used = "PRE";
|
|
4'b0011: command_used = "ACT";
|
|
4'b0100: command_used = " WR";
|
|
4'b0101: command_used = " RD";
|
|
4'b0111: command_used = "NOP";
|
|
4'b1000: command_used = "DES";
|
|
4'b0110: command_used = "ZQC";
|
|
default: command_used = "???";
|
|
endcase
|
|
|
|
case(ddr3_top.ddr3_controller_inst.state_calibrate)
|
|
0 : calibration_state = " IDLE ";
|
|
1,6 : calibration_state = " BITSLIP TRAINING ";
|
|
2,3,4,5 : calibration_state = " READ CALIBRATION ";
|
|
7,8 : calibration_state = " WRITE CALIBRATION ";
|
|
9,10,11,12,13,14,15 : calibration_state = " WRITE ALIGNMENT ";
|
|
16,17,18: calibration_state = " Test: BURST ";
|
|
19,20: calibration_state = " Test: RANDOM ";
|
|
21: calibration_state = " Test: ALTERNATING ";
|
|
22,23: calibration_state = " DONE CALIBRATION ";
|
|
default: calibration_state = " ??? ";
|
|
endcase
|
|
|
|
|
|
|
|
// //WRITE_ZERO = 16,
|
|
// BURST_WRITE = 17,
|
|
// BURST_READ = 18,
|
|
// RANDOM_WRITE = 19,
|
|
// RANDOM_READ = 20,
|
|
// ALTERNATE_WRITE_READ = 21,
|
|
// FINISH_READ = 22,
|
|
// DONE_CALIBRATE = 23;
|
|
|
|
|
|
time_now = $time;
|
|
if(command_used == " WR" || command_used == " RD") begin
|
|
$write("[%5d ps] %s @ (%0d, %5d) -> ",(time_now-prev_time[0 +: 32]), command_used, ba_addr, addr); //show bank and column address of being read/write
|
|
end
|
|
else if(command_used == "ACT")
|
|
$write("[%5d ps] %s @ (%0d, %5d) -> ",(time_now-prev_time[0 +: 32]), command_used, ba_addr, addr); //show bank and row address of being activated
|
|
else if(command_used == "PRE")
|
|
$write("[%5d ps] %s @ (%0d) -> ",(time_now-prev_time[0 +: 32]), command_used, ba_addr); //show bank that is being precharged
|
|
else
|
|
$write("[%5d ps] %s -> ",(time_now-prev_time[0 +: 32]), command_used); //show bank that is being precharged
|
|
prev_cmd <= {prev_cmd[0 +: 3*8], command_used[0 +: 3*8]};
|
|
prev_time <= {prev_time[0 +: 32], time_now};
|
|
repeats <= repeats + 1;
|
|
if(repeats == 4) begin
|
|
$write("\n");
|
|
repeats <= 0;
|
|
end
|
|
end
|
|
end
|
|
/*
|
|
// check delays between command if just enough
|
|
always @* begin
|
|
case({command_used, prev_cmd[0 +: 3*8]})
|
|
{"PRE","ACT"};
|
|
{"ACT"," RD"};
|
|
{"ACT"," WR"};
|
|
{" WR"," WR"}:
|
|
{" WR"," RD"}:
|
|
{" RD"," RD"};
|
|
{" RD"," WR"};
|
|
endcase
|
|
end
|
|
*/
|
|
endmodule
|
|
|
|
|