98 lines
3.0 KiB
Verilog
98 lines
3.0 KiB
Verilog
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: spd_reader_top.v
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// Project: Top-level file for SPD reader (intended for AX7325B FPGA board)
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//
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// Engineer: Angelo C. Jacobo
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2023-2025 Angelo Jacobo
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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//
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////////////////////////////////////////////////////////////////////////////////
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`default_nettype none
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`timescale 1ns / 1ps
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module spd_reader_top (
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// clock and reset
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input wire sys_clk_p,
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input wire sys_clk_n,
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input wire i_rst_n,
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// i2c interface
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inout wire i2c_scl,
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inout wire i2c_sda,
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// uart tx interface
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output wire uart_tx,
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// fan
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output wire fan_pwm,
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//Debug LEDs
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output wire[3:0] led
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);
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wire clk_locked;
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wire main_clk_100;
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wire find_i2c_address_done, read_spd_done;
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assign fan_pwm = 1'b0; // turn on fan from the start
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assign led[0] = find_i2c_address_done; // lights up once done
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assign led[1] = find_i2c_address_done;
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assign led[2] = read_spd_done;
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assign led[3] = read_spd_done;
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//===========================================================================
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//Differentia system clock to single end clock
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//===========================================================================
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wire sys_clk; // 200MHz
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IBUFGDS u_ibufg_sys_clk
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(
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.I (sys_clk_p),
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.IB (sys_clk_n),
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.O (sys_clk)
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);
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//===========================================================================
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// Generate 100MHz
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//===========================================================================
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clk_wiz clk_wiz_inst
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(
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// Clock out ports
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.clk_out1(main_clk_100),
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// Status and control signals
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.reset(!i_rst_n),
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.locked(clk_locked),
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// Clock in ports
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.clk_in1(sys_clk)
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);
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//===========================================================================
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// Instantiate SPD reader
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//===========================================================================
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spd_reader spd_reader_inst (
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.i_clk(main_clk_100),
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.i_rst_n(i_rst_n && clk_locked),
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.i2c_scl(i2c_scl),
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.i2c_sda(i2c_sda),
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.uart_tx(uart_tx),
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.find_i2c_address_done(find_i2c_address_done),
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.read_spd_done(read_spd_done)
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);
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endmodule
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