114 lines
2.7 KiB
Verilog
114 lines
2.7 KiB
Verilog
/*
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Copyright (c) 2014-2017 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream UART
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*/
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module uart #
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(
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parameter DATA_WIDTH = 8
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input
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*/
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input wire [DATA_WIDTH-1:0] s_axis_tdata,
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input wire s_axis_tvalid,
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output wire s_axis_tready,
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/*
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* AXI output
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*/
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output wire [DATA_WIDTH-1:0] m_axis_tdata,
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output wire m_axis_tvalid,
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input wire m_axis_tready,
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/*
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* UART interface
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*/
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input wire rxd,
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output wire txd,
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/*
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* Status
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*/
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output wire tx_busy,
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output wire rx_busy,
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output wire rx_overrun_error,
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output wire rx_frame_error,
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/*
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* Configuration
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*/
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input wire [15:0] prescale
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);
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uart_tx #(
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.DATA_WIDTH(DATA_WIDTH)
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)
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uart_tx_inst (
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.clk(clk),
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.rst(rst),
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// axi input
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.s_axis_tdata(s_axis_tdata),
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.s_axis_tvalid(s_axis_tvalid),
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.s_axis_tready(s_axis_tready),
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// output
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.txd(txd),
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// status
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.busy(tx_busy),
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// configuration
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.prescale(prescale)
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);
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uart_rx #(
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.DATA_WIDTH(DATA_WIDTH)
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)
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uart_rx_inst (
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.clk(clk),
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.rst(rst),
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// axi output
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.m_axis_tdata(m_axis_tdata),
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.m_axis_tvalid(m_axis_tvalid),
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.m_axis_tready(m_axis_tready),
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// input
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.rxd(rxd),
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// status
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.busy(rx_busy),
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.overrun_error(rx_overrun_error),
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.frame_error(rx_frame_error),
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// configuration
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.prescale(prescale)
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);
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endmodule
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