UberDDR3/rtl
AngeloJacobo 60e40f9d35 less simulation warning 2023-07-19 18:48:31 +08:00
..
ddr3_controller.v added more registers and formal assertions to wb2 2023-07-19 18:46:36 +08:00
ddr3_phy.v resolved warning from vivado on IOBDELAY 2023-07-19 18:47:24 +08:00
ddr3_top.v less simulation warning 2023-07-19 18:48:31 +08:00
fwb_slave.v make stall and accessible outside, removed added assumptions with i_slave_busy 2023-07-13 18:48:34 +08:00