104 lines
3.7 KiB
Verilog
Executable File
104 lines
3.7 KiB
Verilog
Executable File
`timescale 1 ps / 1 ps
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module IDELAYE2_model (
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output reg DATAOUT,
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input wire C,
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input wire[4:0] CNTVALUEIN,
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input wire LD,
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input wire IDATAIN,
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// NOT MODELLED
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input wire[4:0] CNTVALUEOUT,
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input wire CE,
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input wire CINVCTRL,
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input wire DATAIN,
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input wire INC,
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input wire LDPIPEEN,
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input wire REGRST
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);
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parameter CINVCTRL_SEL = "FALSE";
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parameter DELAY_SRC = "IDATAIN";
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parameter HIGH_PERFORMANCE_MODE = "FALSE";
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parameter IDELAY_TYPE = "FIXED";
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parameter integer IDELAY_VALUE = 0;
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parameter PIPE_SEL = "FALSE";
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parameter real REFCLK_FREQUENCY = 200.0;
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parameter SIGNAL_PATTERN = "DATA";
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`ifdef NO_TEST_MODEL
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parameter TEST_MODEL = 0;
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`else
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parameter TEST_MODEL = 1;
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`endif
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// stop simulation if this modelfile does not support the settings
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initial begin
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if(DELAY_SRC != "IDATAIN") begin
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$display("DELAY_SRC must be IDATAIN!");
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$stop;
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end
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if(IDELAY_TYPE != "VAR_LOAD") begin
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$display("IDELAY_TYPE must be VAR_LOAD!");
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$stop;
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end
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if(REFCLK_FREQUENCY != 200) begin
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$display("REFCLK_FREQUENCY must be 200!");
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$stop;
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end
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end
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integer delay_value;
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initial DATAOUT = 0;
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always @(IDATAIN) DATAOUT <= #(delay_value) IDATAIN;
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initial delay_value = 600;
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always @(posedge C) begin
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if(LD) begin
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delay_value <= 600 + 78*CNTVALUEIN;
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end
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end
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generate
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if(TEST_MODEL == 1) begin
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wire DATAOUT_test;
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reg unequal = 0;
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IDELAYE2 #(
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.DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
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.HIGH_PERFORMANCE_MODE("TRUE"), //Reduced jitter ("TRUE"), Reduced power ("FALSE")
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.IDELAY_TYPE("VAR_LOAD"), //FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
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.IDELAY_VALUE(0), //Input delay tap setting (0-31)
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.PIPE_SEL("FALSE"), //Select pipelined mode, FALSE, TRUE
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.REFCLK_FREQUENCY(200.0), //IDELAYCTRL clock input frequency in MHz (190.0-210.0).
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.SIGNAL_PATTERN("CLOCK") //DATA, CLOCK input signal
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)
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IDELAYE2_test_model (
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.CNTVALUEOUT(), // 5-bit output: Counter value output
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.DATAOUT(DATAOUT_test), // 1-bit output: Delayed data output
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.C(C), // 1-bit input: Clock input
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.CE(1'b0), // 1-bit input: Active high enable increment/decrement input
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.CINVCTRL(1'b0),// 1-bit input: Dynamic clock inversion input
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.CNTVALUEIN(CNTVALUEIN), // 5-bit input: Counter value input
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.DATAIN(), //1-bit input: Internal delay data input
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.IDATAIN(IDATAIN), // 1-bit input: Data input from the I/O
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.INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
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.LD(LD), // 1-bit input: Load IDELAY_VALUE input
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.LDPIPEEN(1'b0), // 1-bit input: Enable PIPELINE register to load data input
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.REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
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);
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// check if delayed signal matches with the actual IDELAY primitive, if not then stop simulation
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always @* begin
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#100;
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if((DATAOUT_test !== DATAOUT) && ($time > 500_000)) begin
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$display("IDELAYE2 MODEL does not match: time = %t", $time);
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unequal <= 1;
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$stop;
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end
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end
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initial begin
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$display("---------------------------------------- TESTING IDELAYE2 Model ----------------------------------------");
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end
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end
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endgenerate
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endmodule
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