32554 lines
3.8 MiB
32554 lines
3.8 MiB
relaunch_sim
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INFO: xsimkernel Simulation Memory Usage: 235040 KB (Peak: 292836 KB), Simulation CPU Usage: 480920 ms
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Command: launch_simulation -step compile -simset sim_1 -mode behavioral
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INFO: [Vivado 12-12493] Simulation top is 'ddr3_dimm_micron_sim'
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WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
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INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/angelo/Desktop/switch_fpga/switch_fpga.sim/sim_1/behav/xsim'
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INFO: [SIM-utils-51] Simulation object is 'sim_1'
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INFO: [USF-XSim-2] XSim::Compile design
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INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/angelo/Desktop/switch_fpga/switch_fpga.sim/sim_1/behav/xsim'
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xvlog --incr --relax -L uvm -prj ddr3_dimm_micron_sim_vlog.prj
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ddr3
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INFO: [VRFC 10-2458] undeclared symbol TZQCS, assumed default net type wire [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3.v:549]
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INFO: [VRFC 10-2458] undeclared symbol TZQINIT, assumed default net type wire [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3.v:550]
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INFO: [VRFC 10-2458] undeclared symbol TZQOPER, assumed default net type wire [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3.v:551]
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3_dimm.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ddr3_dimm
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/new/ddr3_dimm_micron_sim.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ddr3_dimm_micron_sim
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Waiting for jobs to finish...
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No pending jobs, compilation finished.
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INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
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Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral
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INFO: [Vivado 12-12493] Simulation top is 'ddr3_dimm_micron_sim'
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WARNING: [Vivado 12-12986] Compiled library path does not exist: ''
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INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/angelo/Desktop/switch_fpga/switch_fpga.sim/sim_1/behav/xsim'
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INFO: [SIM-utils-51] Simulation object is 'sim_1'
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INFO: [USF-XSim-3] XSim::Elaborate design
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INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/angelo/Desktop/switch_fpga/switch_fpga.sim/sim_1/behav/xsim'
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xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim_behav xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
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Vivado Simulator v2021.2
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Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
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Running: /tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim_behav xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
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Using 8 slave threads.
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Starting static elaboration
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Pass Through NonSizing Optimizer
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:172]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:103]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:124]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:125]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:126]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:127]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:128]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:129]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:131]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:133]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:218]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:246]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:247]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:248]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:250]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:252]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:254]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:290]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:291]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:295]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:296]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:297]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:349]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:350]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:396]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:397]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:398]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:400]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:402]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:404]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:434]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:473]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:474]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:478]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:479]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:480]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:528]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:529]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:597]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:598]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:644]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/new/ddr3_dimm_micron_sim.v:151]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck_n' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/new/ddr3_dimm_micron_sim.v:152]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cke' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/new/ddr3_dimm_micron_sim.v:153]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 's_n' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/new/ddr3_dimm_micron_sim.v:154]
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WARNING: [VRFC 10-3091] actual bit length 14 differs from formal bit length 16 for port 'addr' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/new/ddr3_dimm_micron_sim.v:159]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'odt' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/new/ddr3_dimm_micron_sim.v:160]
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WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/new/ddr3_dimm_micron_sim.v:161]
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WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs_n' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/new/ddr3_dimm_micron_sim.v:162]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3_dimm.v:203]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3_dimm.v:204]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3_dimm.v:205]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3_dimm.v:206]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3_dimm.v:207]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3_dimm.v:208]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3_dimm.v:209]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3_dimm.v:210]
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WARNING: [VRFC 10-5021] port 'scl' is not connected on this instance [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/new/ddr3_dimm_micron_sim.v:149]
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Completed static elaboration
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Starting simulation data flow analysis
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WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
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WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_controller.v" Line 27. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
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WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
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WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
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WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_controller.v" Line 27. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
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WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale.
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Completed simulation data flow analysis
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Time Resolution for simulation is 1ps
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Compiling module xil_defaultlib.ddr3_controller(CONTROLLER_CLK_P...
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Compiling module unisims_ver.OSERDESE2(DATA_RATE_OQ="SDR",DAT...
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Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
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Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="SDR",DAT...
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Compiling module unisims_ver.OBUFDS
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Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT...
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Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="...
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Compiling module unisims_ver.IOBUF(IOSTANDARD="SSTL15",SLEW="...
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Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="...
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Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE...
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Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT...
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Compiling module unisims_ver.IOBUFDS(IOSTANDARD="DIFF_SSTL15"...
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Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE...
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Compiling module unisims_ver.IDELAYCTRL_default
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Compiling module xil_defaultlib.ddr3_phy(CONTROLLER_CLK_PERIOD=1...
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Compiling module xil_defaultlib.ddr3_top(CONTROLLER_CLK_PERIOD=1...
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Compiling module xil_defaultlib.ddr3_default
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Compiling module xil_defaultlib.ddr3_dimm_default
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Compiling module xil_defaultlib.ddr3_dimm_micron_sim
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Compiling module xil_defaultlib.glbl
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Built simulation snapshot ddr3_dimm_micron_sim_behav
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run_program: Time (s): cpu = 00:02:40 ; elapsed = 00:01:38 . Memory (MB): peak = 10214.414 ; gain = 0.000 ; free physical = 1336 ; free virtual = 23265
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INFO: [USF-XSim-69] 'elaborate' step finished in '97' seconds
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launch_simulation: Time (s): cpu = 00:02:40 ; elapsed = 00:01:38 . Memory (MB): peak = 10214.414 ; gain = 0.000 ; free physical = 1336 ; free virtual = 23265
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Time resolution is 1 ps
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Test ns_to_cycles() function:
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ns_to_cycles(15) = 3 = 2 [exact]
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ns_to_cycles(14.5) = 3 = 2 [round-off]
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ns_to_cycles(11) = 3 = 2 [round-up]
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Test nCK_to_cycles() function:
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ns_to_cycles(16) = 4 = 4 [exact]
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ns_to_cycles(15) = 4 = 4 [round-off]
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ns_to_cycles(13) = 4 = 4 [round-up]
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Test ns_to_nCK() function:
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ns_to_cycles(15) = 12 = 6 [exact]
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ns_to_cycles(14.875) = 12 = 6 [round-off]
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ns_to_cycles(13.875) = 12 = 6 [round-up]
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ns_to_nCK(tRCD) = 11 = 6 [WRONG]
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tRTP = 7.5 = 10.000000
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ns_to_nCK(tRTP) = 6= 4.000000 [WRONG]
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Test nCK_to_ns() function:
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ns_to_cycles(4) = 5 = 10 [exact]
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ns_to_cycles(14.875) = 4 = 8 [round-off]
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ns_to_cycles(13.875) = 7 = 13 [round-up]
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Test nCK_to_ns() function:
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ns_to_cycles(4) = 5 = 10 [exact]
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ns_to_cycles(14.875) = 4 = 8 [round-off]
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ns_to_cycles(13.875) = 7 = 13 [round-up]
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|
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Test $floor() function:
|
|
$floor(5/2) = 2.5 = 2
|
|
$floor(9/4) = 2.25 = 2
|
|
$floor(9/4) = 2 = 2
|
|
$floor(9/5) = 1.8 = 1
|
|
|
|
|
|
DELAY_COUNTER_WIDTH = 16
|
|
DELAY_SLOT_WIDTH = 19
|
|
serdes_ratio = 4
|
|
wb_addr_bits = 24
|
|
wb_data_bits = 512
|
|
wb_sel_bits = 64
|
|
|
|
|
|
READ_SLOT = 2
|
|
WRITE_SLOT = 3
|
|
ACTIVATE_SLOT = 0
|
|
PRECHARGE_SLOT = 1
|
|
|
|
|
|
DELAYS:
|
|
ns_to_nCK(tRCD): 6
|
|
ns_to_nCK(tRP): 6
|
|
ns_to_nCK(tRTP): 4
|
|
tCCD: 4
|
|
(CL_nCK + tCCD + 3'd2 - CWL_nCK): 7
|
|
(CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15
|
|
(CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13
|
|
$signed(4'b1100)>>>4: 1111
|
|
|
|
|
|
PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1
|
|
ACTIVATE_TO_WRITE_DELAY = 3 = 0
|
|
ACTIVATE_TO_READ_DELAY = 2 = 0
|
|
READ_TO_WRITE_DELAY = 2 = 1
|
|
READ_TO_READ_DELAY = 0 = 0
|
|
READ_TO_PRECHARGE_DELAY = 1 =1
|
|
WRITE_TO_WRITE_DELAY = 0 = 0
|
|
WRITE_TO_READ_DELAY = 4 = 3
|
|
WRITE_TO_PRECHARGE_DELAY = 5 = 4
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file: at time 0 INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file.0.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file: at time 0 INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file.1.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file: at time 0 INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file.2.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file: at time 0 INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file.3.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file: at time 0 INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file.4.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file: at time 0 INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file.5.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file: at time 0 INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file.6.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file: at time 0 INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file.7.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file.0.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file.1.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file.2.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file.3.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file.4.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file.5.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file.6.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file.7.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file.0.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file.1.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file.2.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file.3.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file.4.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file.5.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file.6.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file.7.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file.0.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file.1.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file.2.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file.3.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file.4.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file.5.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file.6.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file.7.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file.0.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file.1.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file.2.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file.3.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file.4.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file.5.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file.6.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file.7.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file.0.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file.1.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file.2.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file.3.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file.4.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file.5.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file.6.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file.7.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file.0.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file.1.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file.2.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file.3.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file.4.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file.5.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file.6.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file.7.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file.0.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file.1.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file.2.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file.3.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file.4.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file.5.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file.6.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file.7.
|
|
ddr3_dimm_micron_sim.ddr3_dimm: Single Rank
|
|
ddr3_dimm_micron_sim.ddr3_dimm: non ECC
|
|
ddr3_dimm_micron_sim.ddr3_dimm: Unbuffered DIMM
|
|
ddr3_dimm_micron_sim.ddr3_dimm: Component Width = x8
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 291400.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 291400.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 291400.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 291400.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 291400.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 291400.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 291400.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 291400.0 ps WARNING: 200 us is required before RST_N goes inactive.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 803300.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 803300.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 803300.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 803300.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 803300.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 803300.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 803300.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 803300.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
|
|
run: Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 10217.297 ; gain = 0.000 ; free physical = 1219 ; free virtual = 23150
|
|
relaunch_xsim_kernel: Time (s): cpu = 00:00:02 ; elapsed = 00:00:10 . Memory (MB): peak = 10217.297 ; gain = 2.883 ; free physical = 1219 ; free virtual = 23150
|
|
relaunch_sim: Time (s): cpu = 00:10:43 ; elapsed = 00:01:52 . Memory (MB): peak = 10217.297 ; gain = 2.883 ; free physical = 1219 ; free virtual = 23150
|
|
run all
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1175800.0 ps INFO: Load Mode 2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 CAS Write Latency = 5
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Auto Self Refresh = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1175800.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Dynamic ODT = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1175800.0 ps INFO: Load Mode 2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 CAS Write Latency = 5
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Auto Self Refresh = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1175800.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Dynamic ODT = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1175800.0 ps INFO: Load Mode 2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 CAS Write Latency = 5
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Auto Self Refresh = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1175800.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Dynamic ODT = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1175800.0 ps INFO: Load Mode 2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 CAS Write Latency = 5
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Auto Self Refresh = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1175800.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Dynamic ODT = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1175800.0 ps INFO: Load Mode 2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 CAS Write Latency = 5
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Auto Self Refresh = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1175800.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Dynamic ODT = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1175800.0 ps INFO: Load Mode 2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 CAS Write Latency = 5
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Auto Self Refresh = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1175800.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Dynamic ODT = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1175800.0 ps INFO: Load Mode 2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 CAS Write Latency = 5
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Auto Self Refresh = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1175800.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Dynamic ODT = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1175800.0 ps INFO: Load Mode 2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 CAS Write Latency = 5
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Auto Self Refresh = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1175800.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Dynamic ODT = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1185800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1185800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1185800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1185800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1185800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1185800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1185800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1185800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1195800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Write Levelization = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1195800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Write Levelization = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1195800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Write Levelization = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1195800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Write Levelization = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1195800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Write Levelization = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1195800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Write Levelization = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1195800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Write Levelization = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1195800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Write Levelization = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1205800.0 ps INFO: Load Mode 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Length = 8
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Order = Sequential
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 CAS Latency = 6
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Write Recovery = 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Power Down Mode = DLL off
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1205800.0 ps INFO: Load Mode 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Length = 8
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Order = Sequential
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 CAS Latency = 6
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Write Recovery = 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Power Down Mode = DLL off
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1205800.0 ps INFO: Load Mode 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Length = 8
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Order = Sequential
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 CAS Latency = 6
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Write Recovery = 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Power Down Mode = DLL off
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1205800.0 ps INFO: Load Mode 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Length = 8
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Order = Sequential
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 CAS Latency = 6
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Write Recovery = 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Power Down Mode = DLL off
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1205800.0 ps INFO: Load Mode 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Length = 8
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Order = Sequential
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 CAS Latency = 6
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Write Recovery = 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Power Down Mode = DLL off
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1205800.0 ps INFO: Load Mode 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Length = 8
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Order = Sequential
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 CAS Latency = 6
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Write Recovery = 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Power Down Mode = DLL off
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1205800.0 ps INFO: Load Mode 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Length = 8
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Order = Sequential
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 CAS Latency = 6
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Write Recovery = 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Power Down Mode = DLL off
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1205800.0 ps INFO: Load Mode 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Length = 8
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Order = Sequential
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 CAS Latency = 6
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Write Recovery = 7
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Power Down Mode = DLL off
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1255800.0 ps INFO: ZQ long = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1255800.0 ps INFO: Initialization Sequence is complete
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1255800.0 ps INFO: ZQ long = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1255800.0 ps INFO: Initialization Sequence is complete
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1255800.0 ps INFO: ZQ long = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1255800.0 ps INFO: Initialization Sequence is complete
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1255800.0 ps INFO: ZQ long = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1255800.0 ps INFO: Initialization Sequence is complete
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1255800.0 ps INFO: ZQ long = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1255800.0 ps INFO: Initialization Sequence is complete
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1255800.0 ps INFO: ZQ long = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1255800.0 ps INFO: Initialization Sequence is complete
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1255800.0 ps INFO: ZQ long = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1255800.0 ps INFO: Initialization Sequence is complete
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1255800.0 ps INFO: ZQ long = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1255800.0 ps INFO: Initialization Sequence is complete
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 2545800.0 ps INFO: Precharge All
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 2545800.0 ps INFO: Precharge All
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 2545800.0 ps INFO: Precharge All
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 2545800.0 ps INFO: Precharge All
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 2545800.0 ps INFO: Precharge All
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 2545800.0 ps INFO: Precharge All
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 2545800.0 ps INFO: Precharge All
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 2545800.0 ps INFO: Precharge All
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 2575800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 2575800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 2575800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 2575800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 2575800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 2575800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 2575800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 2575800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 2888300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd= , prev_time=x ps, difference=x ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 2888300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd= , prev_time=x ps, difference=x ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 2888300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd= , prev_time=x ps, difference=x ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 2888300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd= , prev_time=x ps, difference=x ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 2888300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd= , prev_time=x ps, difference=x ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 2888300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd= , prev_time=x ps, difference=x ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 2888300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd= , prev_time=x ps, difference=x ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 2888300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd= , prev_time=x ps, difference=x ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 2902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 2902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 2902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 2902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 2902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 2902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 2902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 2902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 2903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 2903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 2903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 2903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 2903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 2903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 2903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 2903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 2904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 2904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 2904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 2904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 2904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 2904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 2904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 2904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 2905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 2905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 2905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 2905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 2905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 2905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 2905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 2905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 2907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 2907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 2907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 2907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 2907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 2907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 2907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 2907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 2908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 2908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 2908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 2908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 2908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 2908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 2908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 2908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 2909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 2909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 2909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 2909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 2909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 2909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 2909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 2909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 2910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 2910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 2910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 2910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 2910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 2910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 2910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 2910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 3008300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=2888300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 3008300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=2888300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 3008300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=2888300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 3008300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=2888300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 3008300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=2888300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 3008300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=2888300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 3008300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=2888300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 3008300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=2888300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 3138300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3008300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 3138300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3008300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 3138300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3008300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 3138300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3008300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 3138300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3008300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 3138300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3008300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 3138300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3008300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 3138300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3008300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 3258300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3138300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 3258300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3138300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 3258300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3138300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 3258300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3138300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 3258300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3138300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 3258300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3138300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 3258300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3138300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 3258300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3138300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 3388300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3258300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 3388300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3258300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 3388300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3258300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 3388300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3258300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 3388300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3258300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 3388300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3258300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 3388300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3258300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 3388300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3258300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 3508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3388300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 3508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3388300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 3508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3388300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 3508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3388300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 3508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3388300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 3508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3388300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 3508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3388300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 3508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3388300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 3638300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3508300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 3638300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3508300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 3638300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3508300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 3638300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3508300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 3638300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3508300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 3638300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3508300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 3638300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3508300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 3638300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3508300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 3758300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3638300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 3758300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3638300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 3758300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3638300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 3758300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3638300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 3758300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3638300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 3758300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3638300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 3758300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3638300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 3758300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3638300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3772050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3772050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3772050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3772050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3772050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3772050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3772050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3772050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3773300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3773300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3773300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3773300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3773300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3773300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3773300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3773300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3774550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3774550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3774550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3774550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3774550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3774550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3774550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3774550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3775800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3775800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3775800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3775800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3775800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3775800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3775800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3775800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3777050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3777050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3777050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3777050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3777050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3777050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3777050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3777050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3778300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3778300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3778300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3778300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3778300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3778300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3778300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3778300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3779550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3779550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3779550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3779550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3779550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3779550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3779550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3779550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3780800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3780800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3780800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3780800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3780800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3780800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3780800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3780800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 3888300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3758300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 3888300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3758300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 3888300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3758300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 3888300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3758300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 3888300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3758300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 3888300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3758300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 3888300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3758300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 3888300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3758300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 4008300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3888300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 4008300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3888300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 4008300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3888300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 4008300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3888300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 4008300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3888300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 4008300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3888300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 4008300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3888300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 4008300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=3888300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 4138300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4008300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 4138300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4008300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 4138300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4008300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 4138300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4008300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 4138300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4008300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 4138300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4008300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 4138300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4008300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 4138300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4008300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 4258300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4138300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 4258300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4138300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 4258300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4138300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 4258300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4138300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 4258300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4138300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 4258300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4138300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 4258300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4138300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 4258300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4138300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 4388300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4258300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 4388300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4258300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 4388300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4258300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 4388300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4258300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 4388300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4258300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 4388300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4258300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 4388300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4258300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 4388300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4258300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 4508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4388300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 4508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4388300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 4508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4388300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 4508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4388300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 4508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4388300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 4508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4388300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 4508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4388300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 4508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4388300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 4638300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4508300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 4638300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4508300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 4638300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4508300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 4638300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4508300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 4638300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4508300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 4638300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4508300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 4638300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4508300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 4638300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4508300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 4768300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4638300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 4768300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4638300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 4768300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4638300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 4768300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4638300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 4768300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4638300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 4768300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4638300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 4768300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4638300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 4768300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4638300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4782050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4782050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4782050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4782050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4782050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4782050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4782050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4782050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4783300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4783300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4783300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4783300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4783300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4783300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4783300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4783300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4784550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4784550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4784550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4784550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4784550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4784550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4784550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4784550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4785800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4785800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4785800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4785800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4785800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4785800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4785800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4785800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4787050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4787050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4787050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4787050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4787050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4787050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4787050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4787050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4788300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4788300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4788300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4788300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4788300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4788300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4788300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4788300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4789550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4789550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4789550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4789550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4789550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4789550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4789550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4789550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4790800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4790800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4790800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4790800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4790800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4790800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4790800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4790800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 4898300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4768300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 4898300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4768300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 4898300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4768300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 4898300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4768300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 4898300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4768300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 4898300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4768300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 4898300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4768300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 4898300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4768300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4912050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4912050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4912050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4912050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4912050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4912050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4912050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4912050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4913300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4913300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4913300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4913300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4913300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4913300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4913300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4913300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4914550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4914550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4914550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4914550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4914550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4914550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4914550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4914550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4915800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4915800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4915800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4915800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4915800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4915800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4915800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4915800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4917050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4917050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4917050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4917050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4917050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4917050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4917050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4917050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4918300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4918300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4918300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4918300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4918300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4918300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4918300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4918300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4919550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4919550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4919550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4919550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4919550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4919550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4919550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4919550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4920800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4920800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4920800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4920800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4920800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4920800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4920800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4920800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 5378300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4898300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 5378300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4898300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 5378300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4898300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 5378300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4898300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 5378300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4898300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 5378300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4898300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 5378300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4898300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 5378300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=4898300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 5498300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5378300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 5498300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5378300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 5498300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5378300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 5498300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5378300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 5498300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5378300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 5498300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5378300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 5498300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5378300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 5498300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5378300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 5618300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5498300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 5618300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5498300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 5618300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5498300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 5618300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5498300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 5618300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5498300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 5618300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5498300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 5618300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5498300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 5618300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5498300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 5748300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5618300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 5748300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5618300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 5748300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5618300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 5748300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5618300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 5748300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5618300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 5748300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5618300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 5748300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5618300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 5748300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5618300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 5868300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5748300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 5868300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5748300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 5868300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5748300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 5868300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5748300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 5868300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5748300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 5868300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5748300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 5868300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5748300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 5868300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5748300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 5998300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5868300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 5998300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5868300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 5998300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5868300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 5998300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5868300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 5998300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5868300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 5998300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5868300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 5998300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5868300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 5998300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5868300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 6118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5998300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 6118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5998300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 6118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5998300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 6118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5998300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 6118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5998300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 6118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5998300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 6118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5998300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 6118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=5998300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 6248300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6118300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 6248300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6118300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 6248300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6118300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 6248300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6118300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 6248300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6118300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 6248300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6118300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 6248300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6118300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 6248300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6118300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 6368300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6248300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 6368300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6248300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 6368300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6248300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 6368300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6248300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 6368300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6248300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 6368300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6248300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 6368300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6248300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 6368300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6248300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6382050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6382050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6382050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6382050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6382050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6382050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6382050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6382050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6383300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6383300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6383300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6383300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6383300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6383300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6383300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6383300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6384550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6384550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6384550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6384550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6384550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6384550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6384550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6384550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6385800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6385800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6385800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6385800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6385800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6385800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6385800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6385800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6387050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6387050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6387050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6387050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6387050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6387050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6387050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6387050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6388300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6388300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6388300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6388300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6388300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6388300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6388300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6388300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6389550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6389550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6389550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6389550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6389550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6389550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6389550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6389550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6390800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6390800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6390800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6390800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6390800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6390800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6390800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6390800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 6498300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6368300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 6498300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6368300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 6498300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6368300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 6498300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6368300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 6498300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6368300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 6498300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6368300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 6498300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6368300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 6498300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6368300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 6618300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6498300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 6618300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6498300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 6618300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6498300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 6618300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6498300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 6618300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6498300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 6618300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6498300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 6618300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6498300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 6618300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6498300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 6748300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6618300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 6748300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6618300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 6748300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6618300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 6748300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6618300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 6748300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6618300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 6748300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6618300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 6748300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6618300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 6748300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6618300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 6868300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6748300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 6868300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6748300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 6868300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6748300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 6868300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6748300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 6868300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6748300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 6868300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6748300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 6868300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6748300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 6868300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6748300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 6998300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6868300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 6998300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6868300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 6998300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6868300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 6998300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6868300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 6998300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6868300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 6998300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6868300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 6998300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6868300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 6998300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6868300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 7118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6998300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 7118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6998300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 7118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6998300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 7118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6998300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 7118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6998300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 7118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6998300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 7118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6998300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 7118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=6998300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 7248300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7118300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 7248300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7118300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 7248300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7118300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 7248300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7118300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 7248300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7118300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 7248300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7118300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 7248300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7118300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 7248300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7118300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 7378300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7248300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 7378300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7248300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 7378300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7248300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 7378300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7248300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 7378300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7248300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 7378300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7248300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 7378300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7248300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 7378300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7248300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 7508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7378300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 7508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7378300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 7508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7378300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 7508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7378300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 7508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7378300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 7508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7378300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 7508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7378300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 7508300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7378300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 7988300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7508300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 7988300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7508300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 7988300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7508300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 7988300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7508300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 7988300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7508300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 7988300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7508300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 7988300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7508300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 7988300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7508300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 8108300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7988300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 8108300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7988300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 8108300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7988300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 8108300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7988300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 8108300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7988300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 8108300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7988300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 8108300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7988300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 8108300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=7988300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 8228300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8108300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 8228300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8108300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 8228300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8108300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 8228300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8108300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 8228300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8108300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 8228300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8108300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 8228300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8108300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 8228300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8108300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 8358300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8228300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 8358300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8228300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 8358300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8228300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 8358300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8228300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 8358300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8228300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 8358300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8228300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 8358300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8228300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 8358300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8228300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 8478300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8358300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 8478300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8358300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 8478300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8358300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 8478300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8358300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 8478300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8358300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 8478300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8358300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 8478300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8358300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 8478300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8358300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 8608300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8478300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 8608300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8478300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 8608300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8478300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 8608300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8478300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 8608300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8478300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 8608300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8478300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 8608300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8478300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 8608300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8478300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 8728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8608300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 8728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8608300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 8728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8608300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 8728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8608300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 8728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8608300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 8728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8608300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 8728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8608300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 8728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8608300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 8858300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8728300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 8858300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8728300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 8858300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8728300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 8858300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8728300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 8858300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8728300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 8858300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8728300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 8858300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8728300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 8858300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8728300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 8978300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8858300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 8978300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8858300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 8978300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8858300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 8978300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8858300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 8978300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8858300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 8978300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8858300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 8978300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8858300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 8978300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8858300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8992050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8992050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8992050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8992050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8992050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8992050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8992050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8992050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8993300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8993300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8993300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8993300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8993300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8993300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8993300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8993300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8994550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8994550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8994550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8994550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8994550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8994550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8994550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8994550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8995800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8995800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8995800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8995800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8995800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8995800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8995800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8995800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8997050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8997050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8997050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8997050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8997050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8997050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8997050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8997050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8998300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8998300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8998300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8998300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8998300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8998300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8998300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8998300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8999550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8999550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8999550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8999550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8999550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8999550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8999550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8999550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9000800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9000800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9000800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9000800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9000800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9000800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9000800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9000800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 9108300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8978300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 9108300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8978300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 9108300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8978300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 9108300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8978300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 9108300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8978300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 9108300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8978300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 9108300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8978300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 9108300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=8978300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 9228300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9108300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 9228300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9108300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 9228300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9108300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 9228300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9108300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 9228300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9108300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 9228300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9108300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 9228300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9108300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 9228300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9108300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 9358300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9228300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 9358300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9228300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 9358300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9228300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 9358300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9228300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 9358300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9228300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 9358300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9228300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 9358300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9228300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 9358300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9228300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 9478300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9358300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 9478300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9358300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 9478300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9358300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 9478300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9358300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 9478300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9358300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 9478300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9358300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 9478300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9358300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 9478300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9358300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 9608300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9478300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 9608300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9478300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 9608300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9478300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 9608300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9478300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 9608300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9478300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 9608300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9478300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 9608300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9478300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 9608300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9478300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 9728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9608300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 9728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9608300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 9728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9608300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 9728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9608300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 9728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9608300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 9728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9608300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 9728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9608300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 9728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9608300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 9858300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9728300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 9858300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9728300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 9858300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9728300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 9858300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9728300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 9858300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9728300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 9858300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9728300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 9858300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9728300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 9858300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9728300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 9988300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9858300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 9988300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9858300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 9988300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9858300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 9988300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9858300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 9988300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9858300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 9988300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9858300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 9988300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9858300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 9988300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9858300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 10118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9988300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 10118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9988300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 10118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9988300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 10118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9988300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 10118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9988300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 10118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9988300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 10118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9988300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 10118300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=9988300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 10598300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10118300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 10598300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10118300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 10598300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10118300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 10598300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10118300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 10598300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10118300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 10598300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10118300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 10598300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10118300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 10598300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10118300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 10718300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10598300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 10718300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10598300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 10718300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10598300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 10718300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10598300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 10718300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10598300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 10718300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10598300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 10718300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10598300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 10718300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10598300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 10838300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10718300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 10838300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10718300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 10838300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10718300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 10838300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10718300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 10838300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10718300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 10838300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10718300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 10838300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10718300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 10838300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10718300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 10968300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10838300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 10968300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10838300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 10968300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10838300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 10968300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10838300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 10968300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10838300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 10968300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10838300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 10968300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10838300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 10968300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10838300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 11088300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10968300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 11088300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10968300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 11088300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10968300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 11088300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10968300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 11088300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10968300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 11088300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10968300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 11088300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10968300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 11088300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=10968300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 11218300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11088300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 11218300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11088300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 11218300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11088300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 11218300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11088300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 11218300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11088300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 11218300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11088300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 11218300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11088300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 11218300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11088300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 11338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11218300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 11338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11218300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 11338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11218300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 11338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11218300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 11338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11218300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 11338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11218300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 11338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11218300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 11338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11218300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 11468300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11338300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 11468300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11338300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 11468300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11338300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 11468300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11338300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 11468300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11338300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 11468300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11338300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 11468300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11338300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 11468300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11338300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 11588300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11468300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 11588300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11468300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 11588300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11468300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 11588300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11468300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 11588300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11468300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 11588300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11468300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 11588300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11468300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 11588300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11468300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11602050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11602050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11602050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11602050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11602050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11602050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11602050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11602050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11603300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11603300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11603300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11603300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11603300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11603300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11603300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11603300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11604550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11604550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11604550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11604550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11604550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11604550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11604550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11604550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11605800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11605800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11605800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11605800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11605800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11605800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11605800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11605800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11607050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11607050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11607050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11607050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11607050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11607050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11607050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11607050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11608300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11608300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11608300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11608300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11608300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11608300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11608300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11608300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11609550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11609550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11609550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11609550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11609550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11609550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11609550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11609550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11610800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11610800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11610800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11610800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11610800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11610800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11610800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11610800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 11718300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11588300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 11718300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11588300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 11718300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11588300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 11718300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11588300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 11718300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11588300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 11718300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11588300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 11718300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11588300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 11718300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11588300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 11838300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11718300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 11838300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11718300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 11838300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11718300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 11838300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11718300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 11838300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11718300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 11838300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11718300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 11838300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11718300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 11838300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11718300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 11968300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11838300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 11968300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11838300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 11968300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11838300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 11968300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11838300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 11968300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11838300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 11968300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11838300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 11968300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11838300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 11968300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11838300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 12088300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11968300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 12088300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11968300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 12088300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11968300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 12088300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11968300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 12088300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11968300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 12088300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11968300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 12088300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11968300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 12088300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=11968300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 12218300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12088300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 12218300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12088300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 12218300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12088300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 12218300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12088300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 12218300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12088300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 12218300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12088300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 12218300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12088300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 12218300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12088300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 12338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12218300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 12338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12218300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 12338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12218300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 12338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12218300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 12338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12218300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 12338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12218300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 12338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12218300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 12338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12218300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 12468300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12338300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 12468300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12338300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 12468300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12338300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 12468300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12338300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 12468300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12338300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 12468300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12338300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 12468300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12338300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 12468300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12338300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 12598300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12468300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 12598300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12468300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 12598300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12468300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 12598300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12468300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 12598300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12468300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 12598300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12468300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 12598300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12468300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 12598300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12468300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 12728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12598300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 12728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12598300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 12728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12598300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 12728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12598300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 12728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12598300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 12728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12598300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 12728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12598300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 12728300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12598300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 13208300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12728300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 13208300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12728300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 13208300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12728300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 13208300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12728300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 13208300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12728300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 13208300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12728300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 13208300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12728300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 13208300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=12728300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 13328300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13208300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 13328300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13208300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 13328300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13208300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 13328300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13208300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 13328300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13208300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 13328300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13208300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 13328300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13208300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 13328300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13208300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 13448300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13328300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 13448300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13328300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 13448300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13328300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 13448300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13328300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 13448300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13328300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 13448300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13328300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 13448300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13328300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 13448300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13328300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 13578300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13448300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 13578300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13448300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 13578300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13448300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 13578300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13448300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 13578300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13448300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 13578300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13448300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 13578300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13448300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 13578300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13448300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 13698300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13578300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 13698300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13578300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 13698300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13578300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 13698300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13578300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 13698300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13578300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 13698300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13578300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 13698300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13578300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 13698300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13578300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 13828300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13698300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 13828300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13698300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 13828300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13698300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 13828300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13698300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 13828300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13698300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 13828300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13698300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 13828300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13698300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 13828300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13698300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 13948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13828300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 13948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13828300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 13948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13828300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 13948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13828300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 13948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13828300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 13948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13828300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 13948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13828300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 13948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13828300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 14078300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13948300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 14078300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13948300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 14078300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13948300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 14078300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13948300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 14078300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13948300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 14078300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13948300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 14078300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13948300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 14078300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=13948300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 14198300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14078300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 14198300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14078300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 14198300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14078300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 14198300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14078300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 14198300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14078300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 14198300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14078300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 14198300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14078300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 14198300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14078300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14212050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14212050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14212050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14212050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14212050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14212050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14212050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14212050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14213300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14213300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14213300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14213300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14213300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14213300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14213300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14213300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14214550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14214550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14214550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14214550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14214550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14214550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14214550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14214550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14215800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14215800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14215800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14215800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14215800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14215800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14215800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14215800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14217050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14217050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14217050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14217050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14217050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14217050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14217050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14217050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14218300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14218300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14218300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14218300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14218300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14218300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14218300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14218300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14219550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14219550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14219550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14219550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14219550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14219550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14219550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14219550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14220800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14220800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14220800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14220800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14220800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14220800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14220800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14220800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 14328300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14198300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 14328300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14198300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 14328300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14198300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 14328300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14198300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 14328300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14198300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 14328300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14198300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 14328300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14198300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 14328300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14198300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 14448300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14328300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 14448300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14328300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 14448300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14328300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 14448300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14328300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 14448300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14328300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 14448300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14328300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 14448300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14328300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 14448300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14328300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 14578300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14448300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 14578300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14448300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 14578300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14448300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 14578300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14448300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 14578300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14448300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 14578300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14448300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 14578300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14448300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 14578300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14448300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 14698300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14578300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 14698300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14578300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 14698300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14578300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 14698300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14578300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 14698300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14578300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 14698300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14578300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 14698300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14578300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 14698300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14578300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 14828300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14698300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 14828300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14698300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 14828300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14698300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 14828300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14698300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 14828300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14698300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 14828300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14698300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 14828300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14698300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 14828300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14698300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 14948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14828300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 14948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14828300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 14948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14828300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 14948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14828300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 14948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14828300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 14948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14828300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 14948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14828300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 14948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14828300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 15078300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14948300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 15078300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14948300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 15078300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14948300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 15078300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14948300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 15078300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14948300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 15078300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14948300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 15078300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14948300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 15078300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=14948300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 15208300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15078300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 15208300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15078300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 15208300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15078300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 15208300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15078300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 15208300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15078300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 15208300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15078300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 15208300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15078300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 15208300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15078300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 15338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15208300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 15338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15208300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 15338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15208300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 15338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15208300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 15338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15208300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 15338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15208300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 15338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15208300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 15338300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15208300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 15818300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15338300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 15818300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15338300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 15818300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15338300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 15818300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15338300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 15818300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15338300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 15818300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15338300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 15818300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15338300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 15818300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15338300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 15938300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15818300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 15938300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15818300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 15938300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15818300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 15938300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15818300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 15938300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15818300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 15938300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15818300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 15938300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15818300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 15938300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15818300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 16058300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15938300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 16058300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15938300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 16058300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15938300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 16058300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15938300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 16058300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15938300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 16058300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15938300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 16058300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15938300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 16058300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=15938300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 16188300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16058300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 16188300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16058300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 16188300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16058300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 16188300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16058300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 16188300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16058300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 16188300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16058300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 16188300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16058300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 16188300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16058300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 16308300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16188300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 16308300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16188300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 16308300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16188300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 16308300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16188300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 16308300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16188300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 16308300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16188300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 16308300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16188300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 16308300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16188300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 16438300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16308300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 16438300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16308300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 16438300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16308300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 16438300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16308300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 16438300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16308300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 16438300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16308300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 16438300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16308300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 16438300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16308300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 16558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16438300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 16558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16438300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 16558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16438300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 16558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16438300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 16558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16438300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 16558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16438300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 16558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16438300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 16558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16438300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 16688300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16558300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 16688300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16558300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 16688300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16558300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 16688300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16558300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 16688300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16558300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 16688300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16558300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 16688300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16558300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 16688300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16558300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 16808300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16688300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 16808300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16688300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 16808300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16688300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 16808300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16688300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 16808300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16688300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 16808300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16688300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 16808300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16688300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 16808300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16688300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16822050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16822050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16822050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16822050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16822050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16822050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16822050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16822050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16823300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16823300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16823300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16823300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16823300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16823300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16823300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16823300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16824550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16824550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16824550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16824550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16824550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16824550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16824550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16824550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16825800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16825800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16825800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16825800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16825800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16825800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16825800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16825800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16827050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16827050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16827050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16827050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16827050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16827050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16827050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16827050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16828300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16828300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16828300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16828300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16828300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16828300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16828300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16828300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16829550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16829550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16829550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16829550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16829550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16829550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16829550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16829550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16830800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16830800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16830800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16830800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16830800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16830800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16830800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16830800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 16938300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16808300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 16938300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16808300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 16938300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16808300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 16938300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16808300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 16938300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16808300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 16938300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16808300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 16938300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16808300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 16938300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16808300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 17058300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16938300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 17058300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16938300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 17058300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16938300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 17058300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16938300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 17058300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16938300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 17058300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16938300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 17058300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16938300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 17058300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=16938300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 17188300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17058300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 17188300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17058300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 17188300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17058300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 17188300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17058300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 17188300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17058300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 17188300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17058300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 17188300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17058300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 17188300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17058300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 17308300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17188300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 17308300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17188300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 17308300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17188300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 17308300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17188300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 17308300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17188300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 17308300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17188300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 17308300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17188300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 17308300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17188300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 17438300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17308300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 17438300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17308300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 17438300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17308300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 17438300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17308300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 17438300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17308300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 17438300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17308300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 17438300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17308300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 17438300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17308300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 17558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17438300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 17558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17438300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 17558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17438300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 17558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17438300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 17558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17438300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 17558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17438300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 17558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17438300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 17558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17438300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 17688300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17558300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 17688300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17558300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 17688300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17558300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 17688300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17558300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 17688300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17558300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 17688300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17558300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 17688300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17558300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 17688300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17558300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 17818300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17688300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 17818300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17688300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 17818300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17688300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 17818300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17688300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 17818300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17688300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 17818300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17688300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 17818300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17688300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 17818300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17688300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 17948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17818300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 17948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17818300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 17948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17818300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 17948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17818300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 17948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17818300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 17948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17818300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 17948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17818300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 17948300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17818300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 18428300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17948300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 18428300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17948300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 18428300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17948300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 18428300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17948300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 18428300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17948300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 18428300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17948300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 18428300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17948300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 18428300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=17948300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 18548300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18428300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 18548300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18428300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 18548300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18428300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 18548300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18428300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 18548300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18428300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 18548300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18428300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 18548300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18428300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 18548300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18428300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 18668300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18548300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 18668300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18548300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 18668300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18548300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 18668300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18548300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 18668300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18548300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 18668300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18548300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 18668300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18548300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 18668300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18548300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 18798300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18668300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 18798300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18668300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 18798300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18668300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 18798300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18668300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 18798300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18668300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 18798300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18668300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 18798300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18668300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 18798300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18668300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 18918300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18798300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 18918300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18798300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 18918300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18798300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 18918300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18798300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 18918300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18798300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 18918300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18798300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 18918300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18798300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 18918300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18798300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 19048300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18918300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 19048300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18918300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 19048300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18918300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 19048300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18918300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 19048300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18918300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 19048300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18918300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 19048300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18918300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 19048300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=18918300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 19168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19048300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 19168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19048300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 19168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19048300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 19168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19048300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 19168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19048300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 19168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19048300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 19168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19048300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 19168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19048300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 19298300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19168300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 19298300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19168300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 19298300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19168300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 19298300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19168300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 19298300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19168300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 19298300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19168300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 19298300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19168300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 19298300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19168300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 19418300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19298300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 19418300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19298300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 19418300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19298300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 19418300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19298300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 19418300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19298300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 19418300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19298300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 19418300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19298300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 19418300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19298300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19432050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19432050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19432050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19432050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19432050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19432050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19432050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19432050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19433300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19433300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19433300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19433300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19433300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19433300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19433300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19433300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19434550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19434550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19434550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19434550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19434550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19434550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19434550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19434550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19435800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19435800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19435800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19435800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19435800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19435800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19435800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19435800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19437050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19437050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19437050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19437050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19437050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19437050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19437050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19437050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19438300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19438300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19438300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19438300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19438300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19438300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19438300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19438300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19439550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19439550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19439550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19439550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19439550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19439550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19439550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19439550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19440800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19440800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19440800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19440800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19440800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19440800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19440800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19440800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 19548300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19418300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 19548300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19418300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 19548300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19418300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 19548300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19418300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 19548300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19418300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 19548300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19418300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 19548300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19418300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 19548300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19418300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 19668300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19548300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 19668300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19548300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 19668300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19548300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 19668300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19548300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 19668300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19548300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 19668300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19548300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 19668300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19548300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 19668300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19548300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 19798300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19668300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 19798300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19668300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 19798300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19668300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 19798300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19668300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 19798300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19668300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 19798300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19668300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 19798300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19668300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 19798300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19668300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 19918300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19798300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 19918300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19798300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 19918300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19798300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 19918300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19798300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 19918300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19798300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 19918300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19798300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 19918300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19798300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 19918300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19798300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 20048300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19918300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 20048300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19918300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 20048300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19918300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 20048300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19918300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 20048300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19918300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 20048300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19918300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 20048300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19918300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 20048300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=19918300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 20168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20048300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 20168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20048300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 20168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20048300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 20168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20048300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 20168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20048300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 20168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20048300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 20168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20048300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 20168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20048300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 20298300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20168300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 20298300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20168300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 20298300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20168300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 20298300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20168300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 20298300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20168300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 20298300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20168300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 20298300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20168300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 20298300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20168300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 20428300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20298300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 20428300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20298300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 20428300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20298300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 20428300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20298300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 20428300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20298300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 20428300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20298300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 20428300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20298300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 20428300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20298300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 20558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20428300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 20558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20428300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 20558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20428300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 20558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20428300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 20558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20428300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 20558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20428300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 20558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20428300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 20558300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20428300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 21038300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20558300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 21038300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20558300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 21038300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20558300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 21038300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20558300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 21038300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20558300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 21038300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20558300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 21038300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20558300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 21038300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=20558300 ps, difference=480000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 21158300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21038300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 21158300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21038300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 21158300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21038300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 21158300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21038300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 21158300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21038300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 21158300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21038300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 21158300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21038300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 21158300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21038300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 21278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21158300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 21278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21158300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 21278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21158300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 21278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21158300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 21278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21158300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 21278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21158300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 21278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21158300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 21278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21158300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
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|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
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|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 21408300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21278300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 21408300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21278300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 21408300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21278300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 21408300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21278300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 21408300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21278300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 21408300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21278300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 21408300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21278300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 21408300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21278300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 21528300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21408300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 21528300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21408300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 21528300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21408300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 21528300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21408300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 21528300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21408300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 21528300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21408300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 21528300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21408300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 21528300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21408300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 21658300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21528300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 21658300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21528300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 21658300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21528300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 21658300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21528300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 21658300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21528300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 21658300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21528300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 21658300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21528300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 21658300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21528300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 21778300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21658300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 21778300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21658300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 21778300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21658300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 21778300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21658300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 21778300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21658300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 21778300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21658300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 21778300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21658300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 21778300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21658300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 21908300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21778300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 21908300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21778300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 21908300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21778300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 21908300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21778300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 21908300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21778300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 21908300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21778300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 21908300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21778300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 21908300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21778300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 22028300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21908300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 22028300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21908300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 22028300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21908300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 22028300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21908300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 22028300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21908300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 22028300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21908300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 22028300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21908300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 22028300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=21908300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22042050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22042050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22042050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22042050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22042050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22042050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22042050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22042050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22043300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22043300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22043300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22043300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22043300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22043300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22043300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22043300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22044550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22044550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22044550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22044550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22044550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22044550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22044550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22044550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22045800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22045800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22045800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22045800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22045800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22045800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22045800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22045800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22047050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22047050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22047050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22047050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22047050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22047050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22047050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22047050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22048300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22048300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22048300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22048300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22048300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22048300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22048300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22048300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22049550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22049550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22049550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22049550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22049550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22049550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22049550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22049550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22050800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22050800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22050800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22050800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22050800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22050800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22050800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22050800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 22158300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22028300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 22158300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22028300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 22158300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22028300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 22158300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22028300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 22158300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22028300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 22158300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22028300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 22158300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22028300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 22158300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22028300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 22278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22158300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 22278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22158300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 22278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22158300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 22278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22158300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 22278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22158300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 22278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22158300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 22278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22158300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 22278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22158300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 22408300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22278300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 22408300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22278300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 22408300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22278300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 22408300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22278300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 22408300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22278300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 22408300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22278300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 22408300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22278300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 22408300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22278300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 22528300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22408300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 22528300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22408300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 22528300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22408300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 22528300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22408300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 22528300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22408300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 22528300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22408300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 22528300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22408300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 22528300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22408300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 22658300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22528300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 22658300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22528300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 22658300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22528300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 22658300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22528300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 22658300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22528300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 22658300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22528300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 22658300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22528300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 22658300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22528300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 22778300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22658300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 22778300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22658300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 22778300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22658300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 22778300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22658300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 22778300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22658300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 22778300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22658300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 22778300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22658300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 22778300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22658300 ps, difference=120000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 22908300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22778300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 22908300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22778300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 22908300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22778300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 22908300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22778300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 22908300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22778300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 22908300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22778300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 22908300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22778300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 22908300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22778300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23038300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22908300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23038300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22908300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23038300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22908300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23038300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22908300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23038300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22908300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23038300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22908300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23038300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22908300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23038300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=22908300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=23038300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=23038300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=23038300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=23038300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=23038300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=23038300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=23038300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23168300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=23038300 ps, difference=130000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23405800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23405800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23405800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23405800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23405800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23405800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23405800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23405800.0 ps INFO: Load Mode 3
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23415800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Write Levelization = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23415800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Write Levelization = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23415800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Write Levelization = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23415800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Write Levelization = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23415800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Write Levelization = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23415800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Write Levelization = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23415800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Write Levelization = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23415800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Write Levelization = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 23550800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 23550800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 23550800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 23550800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 23550800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 23550800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 23550800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 23550800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23701502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23704002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23706502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23709002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23711502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23714002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23716502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23719002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23851580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23854080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23856580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23859080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23861580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23864080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23866580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23869080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24001658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24004158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24006658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24009158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24011658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24014158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24016658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24019158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24151736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24154236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24156736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24159236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24161736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24164236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24166736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24169236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24301814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24304314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24306814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24309314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24311814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24314314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24316814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24319314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24451892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24452050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24454392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24454550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24456892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24457050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24459392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24459550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24461892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24462050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24464392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24464550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24466892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24467050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24469392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24469550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24601970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24602050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24604470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24604550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24606970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24607050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24609470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24609550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24611970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24612050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24614470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24614550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24616970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24617050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24619470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24619550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24752048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24752050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24754548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24754550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24757048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24757050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24759548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24759550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24762048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24762050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24764548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24764550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24767048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24767050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24769548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24769550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24902126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24902126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24904626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24904626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24907126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24907126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24909626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24909626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24912126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24912126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24914626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24914626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24917126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24917126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24919626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24919626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25052204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25052204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25054704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25054704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25057204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25057204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25059704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25059704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25062204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25062204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25064704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25064704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25067204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25067204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25069704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25069704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25202282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25204782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25207282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25209782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25212282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25214782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25217282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25219782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25352360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25354860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25357360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25359860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25362360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25364860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25367360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25369860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25502438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25504938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25507438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25509938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25512438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25514938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25517438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25519938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25652516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25655016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25657516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25660016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25662516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25665016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25667516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25670016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25802594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25805094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25807594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25810094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25812594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25815094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25817594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25820094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25952672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25955172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25957672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25960172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25962672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25965172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25967672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25970172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26102750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26105250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26107750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26110250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26112750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26115250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26117750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26120250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26252828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26255328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26257828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26260328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26262828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26265328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26267828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26270328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26402906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26405406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26407906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26410406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26412906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26415406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26417906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26420406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26552984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26555484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26557984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26560484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26562984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26565484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26567984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26570484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26703062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26705562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26708062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26710562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26713062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26715562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26718062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26720562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26853140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 26853300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26855640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 26855800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26858140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 26858300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26860640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 26860800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26863140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 26863300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26865640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 26865800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26868140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 26868300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26870640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 26870800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27003218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27003300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27005718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27005800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27008218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27008300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27010718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27010800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27013218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27013300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27015718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27015800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27018218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27018300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27020718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27020800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27150800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27150800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27153300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27153300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27155800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27155800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27158300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27158300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27160800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27160800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27163300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27163300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27165800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27165800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27168300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27168300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27601502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27604002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27606502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27609002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27611502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27614002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27616502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27619002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27751580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27754080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27756580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27759080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27761580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27764080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27766580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27769080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27901658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27904158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27906658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27909158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27911658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27914158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27916658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27919158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28051736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28054236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28056736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28059236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28061736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28064236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28066736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28069236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28201814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28204314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28206814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28209314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28211814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28214314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28216814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28219314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28351892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28352050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28354392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28354550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28356892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28357050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28359392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28359550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28361892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28362050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28364392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28364550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28366892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28367050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28369392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28369550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28501970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28502050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28504470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28504550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28506970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28507050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28509470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28509550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28511970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28512050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28514470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28514550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28516970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28517050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28519470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28519550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28652048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28652050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28654548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28654550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28657048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28657050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28659548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28659550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28662048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28662050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28664548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28664550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28667048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28667050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28669548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28669550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28802126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28802126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28804626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28804626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28807126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28807126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28809626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28809626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28812126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28812126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28814626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28814626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28817126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28817126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28819626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28819626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28952204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28952204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28954704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28954704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28957204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28957204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28959704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28959704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28962204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28962204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28964704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28964704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28967204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28967204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28969704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28969704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29102282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29104782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29107282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29109782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29112282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29114782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29117282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29119782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29252360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29254860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29257360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29259860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29262360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29264860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29267360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29269860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29402438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29404938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29407438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29409938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29412438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29414938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29417438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29419938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29552516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29555016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29557516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29560016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29562516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29565016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29567516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29570016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29702594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29705094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29707594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29710094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29712594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29715094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29717594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29720094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29852672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29855172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29857672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29860172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29862672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29865172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29867672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29870172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30002750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30005250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30007750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30010250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30012750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30015250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30017750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30020250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30152828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30155328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30157828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30160328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30162828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30165328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30167828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30170328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30302906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30305406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30307906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30310406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30312906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30315406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30317906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30320406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30452984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30455484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30457984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30460484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30462984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30465484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30467984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30470484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30603062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30605562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30608062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30610562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30613062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30615562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30618062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30620562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30753140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30753300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30755640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30755800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30758140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30758300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30760640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30760800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30763140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30763300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30765640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30765800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30768140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30768300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30770640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30770800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30903218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30903300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30905718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30905800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30908218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30908300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30910718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30910800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30913218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30913300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30915718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30915800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30918218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30918300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30920718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30920800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31050800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 31050800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31053300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 31053300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31055800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 31055800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31058300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 31058300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31060800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 31060800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31063300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 31063300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31065800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 31065800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31068300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 31068300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31501502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31504002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31506502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31509002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31511502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31514002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31516502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31519002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31651580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31654080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31656580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31659080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31661580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31664080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31666580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31669080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31801658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31804158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31806658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31809158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31811658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31814158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31816658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31819158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31951736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31954236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31956736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31959236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31961736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31964236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31966736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31969236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32101814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32104314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32106814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32109314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32111814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32114314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32116814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32119314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32251892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32252050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32254392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32254550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32256892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32257050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32259392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32259550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32261892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32262050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32264392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32264550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32266892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32267050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32269392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32269550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32401970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32402050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32404470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32404550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32406970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32407050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32409470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32409550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32411970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32412050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32414470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32414550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32416970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32417050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32419470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32419550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32552048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32552050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32554548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32554550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32557048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32557050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32559548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32559550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32562048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32562050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32564548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32564550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32567048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32567050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32569548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32569550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32702126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32702126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32704626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32704626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32707126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32707126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32709626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32709626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32712126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32712126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32714626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32714626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32717126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32717126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32719626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32719626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32852204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32852204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32854704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32854704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32857204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32857204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32859704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32859704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32862204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32862204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32864704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32864704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32867204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32867204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32869704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32869704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33002282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33004782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33007282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33009782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33012282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33014782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33017282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33019782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33152360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33154860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33157360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33159860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33162360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33164860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33167360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33169860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33302438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33304938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33307438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33309938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33312438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33314938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33317438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33319938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33452516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33455016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33457516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33460016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33462516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33465016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33467516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33470016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33602594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33605094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33607594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33610094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33612594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33615094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33617594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33620094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33752672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33755172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33757672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33760172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33762672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33765172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33767672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33770172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33902750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33905250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33907750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33910250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33912750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33915250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33917750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33920250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34052828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34055328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34057828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34060328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34062828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34065328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34067828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34070328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34202906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34205406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34207906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34210406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34212906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34215406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34217906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34220406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34352984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34355484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34357984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34360484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34362984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34365484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34367984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34370484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34503062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34505562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34508062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34510562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34513062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34515562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34518062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34520562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34653140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34653300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34655640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34655800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34658140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34658300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34660640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34660800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34663140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34663300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34665640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34665800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34668140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34668300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34670640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34670800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34803218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34803300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34805718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34805800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34808218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34808300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34810718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34810800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34813218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34813300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34815718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34815800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34818218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34818300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34820718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34820800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34950800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34950800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34953300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34953300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34955800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34955800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34958300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34958300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34960800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34960800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34963300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34963300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34965800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34965800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34968300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34968300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35401502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35404002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35406502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35409002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35411502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35414002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35416502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35419002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35551580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35554080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35556580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35559080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35561580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35564080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35566580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35569080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35701658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35704158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35706658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35709158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35711658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35714158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35716658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35719158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35851736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35854236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35856736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35859236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35861736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35864236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35866736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35869236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36001814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36004314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36006814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36009314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36011814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36014314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36016814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36019314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36151892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36152050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36154392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36154550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36156892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36157050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36159392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36159550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36161892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36162050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36164392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36164550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36166892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36167050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36169392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36169550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36301970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36302050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36304470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36304550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36306970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36307050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36309470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36309550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36311970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36312050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36314470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36314550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36316970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36317050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36319470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36319550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36452048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36452050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36454548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36454550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36457048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36457050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36459548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36459550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36462048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36462050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36464548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36464550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36467048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36467050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36469548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36469550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36602126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36602126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36604626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36604626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36607126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36607126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36609626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36609626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36612126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36612126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36614626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36614626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36617126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36617126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36619626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36619626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36752204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36752204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36754704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36754704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36757204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36757204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36759704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36759704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36762204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36762204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36764704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36764704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36767204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36767204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36769704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36769704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36902282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36904782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36907282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36909782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36912282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36914782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36917282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36919782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37052360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37054860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37057360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37059860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37062360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37064860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37067360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37069860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37202438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37204938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37207438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37209938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37212438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37214938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37217438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37219938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37352516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37355016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37357516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37360016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37362516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37365016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37367516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37370016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37502594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37505094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37507594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37510094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37512594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37515094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37517594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37520094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37652672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37655172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37657672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37660172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37662672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37665172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37667672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37670172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37802750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37805250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37807750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37810250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37812750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37815250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37817750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37820250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37952828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37955328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37957828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37960328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37962828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37965328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37967828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37970328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38102906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38105406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38107906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38110406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38112906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38115406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38117906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38120406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38252984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38255484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38257984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38260484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38262984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38265484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38267984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38270484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38403062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38405562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38408062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38410562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38413062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38415562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38418062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38420562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38553140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38553300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38555640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38555800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38558140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38558300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38560640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38560800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38563140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38563300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38565640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38565800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38568140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38568300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38570640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38570800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38703218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38703300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38705718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38705800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38708218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38708300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38710718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38710800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38713218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38713300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38715718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38715800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38718218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38718300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38720718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38720800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38850800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38850800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38853300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38853300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38855800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38855800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38858300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38858300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38860800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38860800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38863300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38863300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38865800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38865800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38868300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38868300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39301502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39304002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39306502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39309002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39311502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39314002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39316502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39319002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39451580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39454080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39456580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39459080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39461580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39464080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39466580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39469080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39601658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39604158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39606658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39609158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39611658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39614158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39616658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39619158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39751736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39754236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39756736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39759236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39761736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39764236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39766736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39769236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39901814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39904314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39906814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39909314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39911814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39914314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39916814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39919314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40051892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40052050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40054392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40054550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40056892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40057050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40059392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40059550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40061892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40062050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40064392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40064550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40066892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40067050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40069392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40069550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40201970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40202050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40204470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40204550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40206970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40207050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40209470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40209550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40211970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40212050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40214470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40214550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40216970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40217050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40219470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40219550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40352048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40352050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40354548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40354550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40357048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40357050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40359548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40359550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40362048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40362050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40364548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40364550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40367048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40367050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40369548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40369550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40502126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40502126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40504626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40504626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40507126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40507126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40509626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40509626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40512126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40512126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40514626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40514626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40517126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40517126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40519626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40519626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40652204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40652204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40654704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40654704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40657204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40657204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40659704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40659704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40662204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40662204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40664704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40664704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40667204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40667204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40669704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40669704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40802282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40804782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40807282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40809782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40812282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40814782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40817282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40819782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40952360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40954860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40957360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40959860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40962360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40964860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40967360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40969860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41102438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41104938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41107438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41109938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41112438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41114938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41117438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41119938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41252516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41255016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41257516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41260016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41262516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41265016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41267516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41270016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41402594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41405094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41407594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41410094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41412594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41415094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41417594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41420094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41552672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41555172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41557672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41560172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41562672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41565172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41567672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41570172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41702750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41705250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41707750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41710250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41712750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41715250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41717750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41720250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41852828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41855328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41857828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41860328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41862828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41865328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41867828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41870328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42002906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42005406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42007906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42010406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42012906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42015406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42017906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42020406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42152984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42155484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42157984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42160484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42162984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42165484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42167984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42170484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42303062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42305562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42308062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42310562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42313062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42315562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42318062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42320562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42453140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42453300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42455640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42455800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42458140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42458300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42460640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42460800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42463140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42463300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42465640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42465800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42468140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42468300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42470640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42470800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42603218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42603300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42605718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42605800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42608218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42608300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42610718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42610800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42613218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42613300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42615718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42615800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42618218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42618300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42620718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42620800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42750800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42750800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42753300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42753300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42755800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42755800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42758300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42758300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42760800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42760800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42763300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42763300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42765800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42765800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42768300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42768300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43201502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43204002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43206502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43209002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43211502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43214002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43216502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43219002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43351580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43354080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43356580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43359080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43361580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43364080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43366580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43369080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43501658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43504158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43506658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43509158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43511658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43514158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43516658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43519158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43651736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43654236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43656736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43659236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43661736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43664236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43666736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43669236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43801814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43804314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43806814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43809314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43811814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43814314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43816814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43819314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43951892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43952050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43954392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43954550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43956892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43957050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43959392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43959550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43961892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43962050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43964392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43964550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43966892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43967050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43969392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43969550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44101970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44102050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44104470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44104550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44106970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44107050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44109470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44109550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44111970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44112050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44114470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44114550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44116970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44117050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44119470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44119550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44252048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44252050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44254548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44254550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44257048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44257050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44259548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44259550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44262048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44262050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44264548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44264550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44267048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44267050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44269548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44269550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44402126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44402126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44404626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44404626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44407126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44407126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44409626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44409626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44412126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44412126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44414626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44414626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44417126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44417126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44419626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44419626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44552204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44552204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44554704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44554704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44557204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44557204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44559704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44559704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44562204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44562204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44564704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44564704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44567204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44567204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44569704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44569704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44702282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44704782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44707282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44709782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44712282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44714782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44717282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44719782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44852360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44854860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44857360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44859860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44862360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44864860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44867360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44869860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45002438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45004938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45007438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45009938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45012438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45014938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45017438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45019938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45152516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45155016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45157516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45160016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45162516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45165016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45167516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45170016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45302594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45305094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45307594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45310094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45312594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45315094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45317594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45320094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45452672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45455172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45457672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45460172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45462672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45465172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45467672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45470172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45602750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45605250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45607750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45610250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45612750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45615250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45617750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45620250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45752828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45755328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45757828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45760328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45762828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45765328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45767828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45770328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45902906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45905406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45907906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45910406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45912906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45915406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45917906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45920406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46052984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46055484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46057984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46060484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46062984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46065484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46067984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46070484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46203062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46205562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46208062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46210562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46213062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46215562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46218062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46220562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46353140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46353300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46355640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46355800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46358140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46358300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46360640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46360800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46363140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46363300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46365640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46365800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46368140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46368300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46370640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46370800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46503218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46503300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46505718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46505800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46508218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46508300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46510718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46510800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46513218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46513300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46515718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46515800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46518218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46518300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46520718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46520800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46650800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46650800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46653300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46653300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46655800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46655800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46658300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46658300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46660800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46660800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46663300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46663300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46665800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46665800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46668300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46668300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47101502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47104002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47106502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47109002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47111502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47114002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47116502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47119002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47251580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47254080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47256580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47259080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47261580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47264080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47266580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47269080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47401658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47404158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47406658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47409158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47411658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47414158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47416658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47419158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47551736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47554236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47556736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47559236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47561736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47564236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47566736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47569236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47701814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47704314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47706814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47709314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47711814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47714314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47716814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47719314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47851892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47852050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47854392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47854550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47856892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47857050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47859392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47859550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47861892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47862050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47864392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47864550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47866892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47867050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47869392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47869550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48001424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48001970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48002050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48003924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48004470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48004550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48006424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48006970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48007050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48008924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48009470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48009550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48011424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48011970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48012050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48013924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48014470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48014550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48016424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48016970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48017050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48018924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48019470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48019550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48151424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48152048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48152050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48153924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48154548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48154550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48156424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48157048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48157050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48158924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48159548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48159550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48161424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48162048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48162050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48163924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48164548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48164550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48166424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48167048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48167050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48168924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48169548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48169550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48301424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48302126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48302126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48303924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48304626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48304626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48306424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48307126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48307126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48308924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48309626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48309626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48311424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48312126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48312126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48313924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48314626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48314626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48316424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48317126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48317126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48318924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48319626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48319626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48451424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48452204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48452204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48453924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48454704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48454704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48456424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48457204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48457204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48458924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48459704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48459704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48461424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48462204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48462204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48463924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48464704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48464704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48466424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48467204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48467204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48468924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48469704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48469704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48601424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48602282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48603924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48604782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48606424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48607282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48608924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48609782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48611424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48612282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48613924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48614782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48616424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48617282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48618924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48619782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48751424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48752360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48753924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48754860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48756424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48757360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48758924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48759860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48761424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48762360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48763924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48764860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48766424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48767360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48768924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48769860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48901424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48902438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48903924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48904938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48906424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48907438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48908924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48909938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48911424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48912438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48913924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48914938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48916424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48917438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48918924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48919938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49051424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49052516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49053924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49055016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49056424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49057516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49058924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49060016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49061424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49062516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49063924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49065016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49066424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49067516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49068924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49070016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49201424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49202594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49203924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49205094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49206424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49207594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49208924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49210094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49211424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49212594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49213924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49215094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49216424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49217594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49218924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49220094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49351424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49352672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49353924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49355172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49356424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49357672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49358924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49360172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49361424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49362672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49363924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49365172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49366424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49367672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49368924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49370172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49501424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49502750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49503924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49505250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49506424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49507750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49508924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49510250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49511424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49512750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49513924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49515250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49516424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49517750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49518924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49520250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49651424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49652828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49653924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49655328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49656424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49657828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49658924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49660328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49661424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49662828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49663924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49665328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49666424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49667828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49668924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49670328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49801424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49802906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49803924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49805406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49806424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49807906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49808924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49810406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49811424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49812906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49813924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49815406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49816424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49817906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49818924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49820406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49951424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49952984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49953924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49955484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49956424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49957984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49958924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49960484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49961424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49962984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49963924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49965484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49966424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49967984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49968924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49970484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50101424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50103062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50103924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50105562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50106424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50108062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50108924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50110562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50111424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50113062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50113924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50115562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50116424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50118062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50118924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50120562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50251424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50253140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50253300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50253924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50255640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50255800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50256424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50258140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50258300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50258924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50260640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50260800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50261424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50263140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50263300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50263924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50265640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50265800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50266424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50268140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50268300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50268924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50270640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50270800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50401424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50403218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50403300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50403924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50405718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50405800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50406424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50408218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50408300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50408924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50410718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50410800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50411424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50413218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50413300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50413924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50415718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50415800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50416424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50418218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50418300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50418924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50420718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50420800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50550800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50550800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50551424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50553300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50553300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50553924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50555800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50555800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50556424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50558300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50558300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50558924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50560800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50560800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50561424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50563300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50563300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50563924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50565800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50565800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50566424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50568300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50568300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50568924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50701424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50703924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50706424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50708924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50711424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50713924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50716424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50718924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50851424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50853924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50856424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50858924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50861424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50863924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50866424.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50868924.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51001502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51004002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51006502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51009002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51011502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51014002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51016502.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51019002.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51151580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51154080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51156580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51159080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51161580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51164080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51166580.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51169080.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51301658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51304158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51306658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51309158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51311658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51314158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51316658.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51319158.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51451736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51454236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51456736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51459236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51461736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51464236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51466736.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51469236.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51601814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51604314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51606814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51609314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51611814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51614314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51616814.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51619314.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51750878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51751892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51752050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51753378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51754392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51754550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51755878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51756892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51757050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51758378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51759392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51759550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51760878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51761892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51762050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51763378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51764392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51764550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51765878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51766892.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51767050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51768378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51769392.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51769550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51900878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51901970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51902050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51903378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51904470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51904550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51905878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51906970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51907050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51908378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51909470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51909550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51910878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51911970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51912050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51913378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51914470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51914550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51915878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51916970.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51917050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51918378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51919470.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51919550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52050878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52052048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52052050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52053378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52054548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52054550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52055878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52057048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52057050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52058378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52059548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52059550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52060878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52062048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52062050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52063378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52064548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52064550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52065878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52067048.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52067050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52068378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52069548.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52069550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52200878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52202126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52202126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52203378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52204626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52204626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52205878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52207126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52207126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52208378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52209626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52209626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52210878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52212126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52212126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52213378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52214626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52214626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52215878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52217126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52217126.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52218378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52219626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52219626.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52350878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52352204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52352204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52353378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52354704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52354704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52355878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52357204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52357204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52358378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52359704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52359704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52360878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52362204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52362204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52363378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52364704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52364704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52365878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52367204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52367204.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52368378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52369704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52369704.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52500878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52502282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52503378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52504782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52505878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52507282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52508378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52509782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52510878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52512282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52513378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52514782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52515878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52517282.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52518378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52519782.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52650878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52652360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52653378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52654860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52655878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52657360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52658378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52659860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52660878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52662360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52663378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52664860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52665878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52667360.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52668378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52669860.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52800878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52802438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52803378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52804938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52805878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52807438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52808378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52809938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52810878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52812438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52813378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52814938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52815878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52817438.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52818378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52819938.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52950878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52952516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52953378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52955016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52955878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52957516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52958378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52960016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52960878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52962516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52963378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52965016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52965878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52967516.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52968378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52970016.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53100878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53102594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53103378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53105094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53105878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53107594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53108378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53110094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53110878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53112594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53113378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53115094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53115878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53117594.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53118378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53120094.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53250878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53252672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53253378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53255172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53255878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53257672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53258378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53260172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53260878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53262672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53263378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53265172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53265878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53267672.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53268378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53270172.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53400878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53402750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53403378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53405250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53405878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53407750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53408378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53410250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53410878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53412750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53413378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53415250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53415878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53417750.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53418378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53420250.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53550878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53552828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53553378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53555328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53555878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53557828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53558378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53560328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53560878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53562828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53563378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53565328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53565878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53567828.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53568378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53570328.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53700878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53702906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53703378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53705406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53705878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53707906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53708378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53710406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53710878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53712906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53713378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53715406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53715878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53717906.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53718378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53720406.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53850878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53852984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53853378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53855484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53855878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53857984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53858378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53860484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53860878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53862984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53863378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53865484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53865878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53867984.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53868378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53870484.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54000878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54003062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54003378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54005562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54005878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54008062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54008378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54010562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54010878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54013062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54013378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54015562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54015878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54018062.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54018378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54020562.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54150878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54153140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54153300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54153378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54155640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54155800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54155878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54158140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54158300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54158378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54160640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54160800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54160878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54163140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54163300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54163378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54165640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54165800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54165878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54168140.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54168300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54168378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54170640.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54170800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54300878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54303218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54303300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54303378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54305718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54305800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54305878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54308218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54308300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54308378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54310718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54310800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54310878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54313218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54313300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54313378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54315718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54315800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54315878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54318218.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54318300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54318378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54320718.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54320800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54450800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54450800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54450878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54453300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54453300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54453378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54455800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54455800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54455878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54458300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54458300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54458378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54460800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54460800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54460878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54463300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54463300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54463378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54465800.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54465800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54465878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54468300.0 ps Write Leveling @ DQS ck = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54468300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54468378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54600878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54603378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54605878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54608378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54610878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54613378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54615878.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54618378.0 ps Write Leveling @ DQS ck = 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 54740800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 54740800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 54740800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54740800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54740800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54740800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54740800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54740800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 54745800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Write Levelization = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 54745800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Write Levelization = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 54745800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Write Levelization = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 54745800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Write Levelization = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 54745800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Write Levelization = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 54745800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Write Levelization = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 54745800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Write Levelization = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 54745800.0 ps INFO: Load Mode 1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 DLL Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Additive Latency = 0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Write Levelization = Disabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Qoff = Enabled
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 54795800.0 ps INFO: Precharge All
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 54795800.0 ps INFO: Precharge All
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 54795800.0 ps INFO: Precharge All
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 54795800.0 ps INFO: Precharge All
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 54795800.0 ps INFO: Precharge All
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 54795800.0 ps INFO: Precharge All
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 54795800.0 ps INFO: Precharge All
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 54795800.0 ps INFO: Precharge All
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 54825800.0 ps INFO: Refresh
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 54825800.0 ps INFO: Refresh
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 54825800.0 ps INFO: Refresh
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 54825800.0 ps INFO: Refresh
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 54825800.0 ps INFO: Refresh
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 54825800.0 ps INFO: Refresh
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 54825800.0 ps INFO: Refresh
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 54825800.0 ps INFO: Refresh
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 55213300.0 ps INFO: Activate bank 0 row 0000
|
|
prev_cmd=Read , prev_time=23168300 ps, difference=32045000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 55213300.0 ps INFO: Activate bank 0 row 0000
|
|
prev_cmd=Read , prev_time=23168300 ps, difference=32045000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 55213300.0 ps INFO: Activate bank 0 row 0000
|
|
prev_cmd=Read , prev_time=23168300 ps, difference=32045000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 55213300.0 ps INFO: Activate bank 0 row 0000
|
|
prev_cmd=Read , prev_time=23168300 ps, difference=32045000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 55213300.0 ps INFO: Activate bank 0 row 0000
|
|
prev_cmd=Read , prev_time=23168300 ps, difference=32045000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 55213300.0 ps INFO: Activate bank 0 row 0000
|
|
prev_cmd=Read , prev_time=23168300 ps, difference=32045000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 55213300.0 ps INFO: Activate bank 0 row 0000
|
|
prev_cmd=Read , prev_time=23168300 ps, difference=32045000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 55213300.0 ps INFO: Activate bank 0 row 0000
|
|
prev_cmd=Read , prev_time=23168300 ps, difference=32045000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 55230800.0 ps INFO: Write bank 0 col 000, auto precharge 0
|
|
prev_cmd=Activate , prev_time=55213300 ps, difference=17500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 55230800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 55230800.0 ps INFO: Write bank 0 col 000, auto precharge 0
|
|
prev_cmd=Activate , prev_time=55213300 ps, difference=17500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 55230800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 55230800.0 ps INFO: Write bank 0 col 000, auto precharge 0
|
|
prev_cmd=Activate , prev_time=55213300 ps, difference=17500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 55230800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 55230800.0 ps INFO: Write bank 0 col 000, auto precharge 0
|
|
prev_cmd=Activate , prev_time=55213300 ps, difference=17500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 55230800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 55230800.0 ps INFO: Write bank 0 col 000, auto precharge 0
|
|
prev_cmd=Activate , prev_time=55213300 ps, difference=17500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 55230800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 55230800.0 ps INFO: Write bank 0 col 000, auto precharge 0
|
|
prev_cmd=Activate , prev_time=55213300 ps, difference=17500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55230800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 55230800.0 ps INFO: Write bank 0 col 000, auto precharge 0
|
|
prev_cmd=Activate , prev_time=55213300 ps, difference=17500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55230800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 55230800.0 ps INFO: Write bank 0 col 000, auto precharge 0
|
|
prev_cmd=Activate , prev_time=55213300 ps, difference=17500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55230800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 55240800.0 ps INFO: Write bank 0 col 008, auto precharge 0
|
|
prev_cmd=Write , prev_time=55230800 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 55240800.0 ps INFO: Write bank 0 col 008, auto precharge 0
|
|
prev_cmd=Write , prev_time=55230800 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 55240800.0 ps INFO: Write bank 0 col 008, auto precharge 0
|
|
prev_cmd=Write , prev_time=55230800 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 55240800.0 ps INFO: Write bank 0 col 008, auto precharge 0
|
|
prev_cmd=Write , prev_time=55230800 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 55240800.0 ps INFO: Write bank 0 col 008, auto precharge 0
|
|
prev_cmd=Write , prev_time=55230800 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 55240800.0 ps INFO: Write bank 0 col 008, auto precharge 0
|
|
prev_cmd=Write , prev_time=55230800 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 55240800.0 ps INFO: Write bank 0 col 008, auto precharge 0
|
|
prev_cmd=Write , prev_time=55230800 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 55240800.0 ps INFO: Write bank 0 col 008, auto precharge 0
|
|
prev_cmd=Write , prev_time=55230800 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55244550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = c1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55244550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = c1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55244550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = c1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55244550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = c1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55244550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = c1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55244550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = c1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55244550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = c1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55244550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = c1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55245800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 51
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55245800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 51
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55245800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 51
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55245800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 51
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55245800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 51
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55245800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 51
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55245800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 51
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55245800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 51
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55247050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = ad
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55247050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = ad
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55247050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = ad
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55247050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = ad
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55247050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = ad
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55247050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = ad
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55247050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = ad
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55247050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = ad
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55248300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = d0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55248300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = d0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55248300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = d0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55248300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = d0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55248300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = d0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55248300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = d0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55248300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = d0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55248300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = d0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55249550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55249550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55249550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55249550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55249550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55249550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55249550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55249550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55250800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 29
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55250800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 29
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55250800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 29
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55250800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 29
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55250800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 29
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55250800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 29
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55250800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 29
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55250800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 29
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55252050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55252050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55252050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55252050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55252050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55252050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55252050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55252050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55253300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 91
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55253300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 91
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55253300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 91
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55253300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 91
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55253300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 91
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55253300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 91
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55253300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 91
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55253300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 91
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55254550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 3d
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55254550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 3d
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55254550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 3d
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55254550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 3d
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55254550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 3d
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55254550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 3d
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55254550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 3d
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55254550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 3d
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55255800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 2c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55255800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 2c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55255800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 2c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55255800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 2c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55255800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 2c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55255800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 2c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55255800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 2c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55255800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 2c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55257050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = f1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55257050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = f1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55257050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = f1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55257050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = f1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55257050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = f1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55257050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = f1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55257050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = f1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55257050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = f1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55258300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 75
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55258300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 75
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55258300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 75
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55258300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 75
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55258300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 75
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55258300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 75
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55258300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 75
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55258300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 75
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55259550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = d2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55259550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = d2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55259550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = d2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55259550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = d2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55259550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = d2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55259550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = d2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55259550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = d2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55259550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = d2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55260800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = cf
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55260800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = cf
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55260800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = cf
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55260800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = cf
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55260800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = cf
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55260800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = cf
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55260800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = cf
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55260800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = cf
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55262050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55262050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55262050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = d2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55262050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55262050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55262050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = d2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55262050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55262050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55262050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = d2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55262050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55262050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55262050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = d2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55262050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55262050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55262050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = d2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55262050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55262050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55262050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = d2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55262050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55262050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55262050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = d2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55262050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55262050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55262050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = d2
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55263300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55263300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55263300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = cf
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55263300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55263300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55263300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = cf
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55263300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55263300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55263300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = cf
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55263300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55263300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55263300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = cf
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55263300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55263300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55263300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = cf
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55263300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55263300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55263300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = cf
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55263300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55263300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55263300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = cf
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55263300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55263300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55263300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = cf
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 55278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Write , prev_time=55240800 ps, difference=37500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 55278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Write , prev_time=55240800 ps, difference=37500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 55278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Write , prev_time=55240800 ps, difference=37500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 55278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Write , prev_time=55240800 ps, difference=37500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 55278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Write , prev_time=55240800 ps, difference=37500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 55278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Write , prev_time=55240800 ps, difference=37500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 55278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Write , prev_time=55240800 ps, difference=37500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 55278300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Write , prev_time=55240800 ps, difference=37500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 55280800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 55280800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 55280800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 55280800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 55280800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55280800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55280800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55280800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55292050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = c1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55292050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = c1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55292050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = c1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55292050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = c1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55292050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = c1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55292050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = c1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55292050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = c1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55292050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = c1
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55293300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 51
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55293300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 51
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55293300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 51
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55293300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 51
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55293300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 51
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55293300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 51
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55293300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 51
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55293300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 51
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55294550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = ad
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55294550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = ad
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55294550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = ad
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55294550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = ad
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55294550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = ad
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55294550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = ad
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55294550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = ad
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55294550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = ad
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55295800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = d0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55295800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = d0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55295800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = d0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55295800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = d0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55295800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = d0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55295800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = d0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55295800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = d0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55295800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = d0
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55297050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55297050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55297050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55297050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55297050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55297050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55297050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55297050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55298300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 29
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55298300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 29
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55298300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 29
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55298300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 29
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55298300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 29
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55298300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 29
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55298300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 29
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55298300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 29
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55299550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55299550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55299550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55299550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55299550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55299550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55299550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55299550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55300800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 91
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55300800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 91
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55300800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 91
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55300800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 91
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55300800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 91
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55300800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 91
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55300800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 91
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55300800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 91
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 55470800.0 ps INFO: Write bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=55278300 ps, difference=192500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 55470800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 55470800.0 ps INFO: Write bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=55278300 ps, difference=192500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 55470800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 55470800.0 ps INFO: Write bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=55278300 ps, difference=192500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 55470800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 55470800.0 ps INFO: Write bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=55278300 ps, difference=192500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 55470800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 55470800.0 ps INFO: Write bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=55278300 ps, difference=192500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 55470800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 55470800.0 ps INFO: Write bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=55278300 ps, difference=192500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55470800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 55470800.0 ps INFO: Write bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=55278300 ps, difference=192500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55470800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 55470800.0 ps INFO: Write bank 0 col 000, auto precharge 0
|
|
prev_cmd=Read , prev_time=55278300 ps, difference=192500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55470800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 55480800.0 ps INFO: Write bank 0 col 008, auto precharge 0
|
|
prev_cmd=Write , prev_time=55470800 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 55480800.0 ps INFO: Write bank 0 col 008, auto precharge 0
|
|
prev_cmd=Write , prev_time=55470800 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 55480800.0 ps INFO: Write bank 0 col 008, auto precharge 0
|
|
prev_cmd=Write , prev_time=55470800 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 55480800.0 ps INFO: Write bank 0 col 008, auto precharge 0
|
|
prev_cmd=Write , prev_time=55470800 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 55480800.0 ps INFO: Write bank 0 col 008, auto precharge 0
|
|
prev_cmd=Write , prev_time=55470800 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 55480800.0 ps INFO: Write bank 0 col 008, auto precharge 0
|
|
prev_cmd=Write , prev_time=55470800 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 55480800.0 ps INFO: Write bank 0 col 008, auto precharge 0
|
|
prev_cmd=Write , prev_time=55470800 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 55480800.0 ps INFO: Write bank 0 col 008, auto precharge 0
|
|
prev_cmd=Write , prev_time=55470800 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55484550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55484550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55484550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55484550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55484550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55484550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55484550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55484550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55485800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55485800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55485800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55485800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55485800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55485800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55485800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55485800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55487050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55487050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55487050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55487050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55487050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55487050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55487050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55487050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55488300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55488300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55488300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55488300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55488300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55488300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55488300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55488300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55489550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55489550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55489550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55489550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55489550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55489550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55489550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55489550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55490800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55490800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55490800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55490800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55490800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55490800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55490800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55490800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55492050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55492050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55492050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55492050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55492050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55492050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55492050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55492050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55493300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55493300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55493300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55493300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55493300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55493300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55493300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55493300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55494550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55494550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55494550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55494550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55494550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55494550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55494550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55494550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55495800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55495800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55495800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55495800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55495800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55495800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55495800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55495800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55497050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55497050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55497050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55497050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55497050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55497050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55497050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55497050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55498300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55498300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55498300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55498300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55498300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55498300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55498300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55498300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55499550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55499550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55499550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55499550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55499550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55499550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55499550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55499550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55500800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55500800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55500800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55500800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55500800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55500800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55500800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55500800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55502050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55502050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55502050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55502050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55502050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55502050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55502050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55502050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55502050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55502050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55502050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55502050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55502050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55502050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55502050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55502050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55502050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55502050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55502050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55502050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55502050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55502050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55502050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55502050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55503300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55503300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55503300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55503300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55503300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55503300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55503300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55503300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55503300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55503300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55503300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55503300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55503300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55503300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55503300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55503300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55503300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55503300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55503300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55503300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55503300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55503300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55503300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period.
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55503300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 55518300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Write , prev_time=55480800 ps, difference=37500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 55518300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Write , prev_time=55480800 ps, difference=37500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 55518300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Write , prev_time=55480800 ps, difference=37500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 55518300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Write , prev_time=55480800 ps, difference=37500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 55518300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Write , prev_time=55480800 ps, difference=37500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 55518300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Write , prev_time=55480800 ps, difference=37500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 55518300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Write , prev_time=55480800 ps, difference=37500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 55518300.0 ps INFO: Read bank 0 col 000, auto precharge 0
|
|
prev_cmd=Write , prev_time=55480800 ps, difference=37500 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 55520800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 55520800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 55520800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 55520800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 55520800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55520800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55520800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55520800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 55528300.0 ps INFO: Read bank 0 col 008, auto precharge 0
|
|
prev_cmd=Read , prev_time=55518300 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 55528300.0 ps INFO: Read bank 0 col 008, auto precharge 0
|
|
prev_cmd=Read , prev_time=55518300 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 55528300.0 ps INFO: Read bank 0 col 008, auto precharge 0
|
|
prev_cmd=Read , prev_time=55518300 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 55528300.0 ps INFO: Read bank 0 col 008, auto precharge 0
|
|
prev_cmd=Read , prev_time=55518300 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 55528300.0 ps INFO: Read bank 0 col 008, auto precharge 0
|
|
prev_cmd=Read , prev_time=55518300 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 55528300.0 ps INFO: Read bank 0 col 008, auto precharge 0
|
|
prev_cmd=Read , prev_time=55518300 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 55528300.0 ps INFO: Read bank 0 col 008, auto precharge 0
|
|
prev_cmd=Read , prev_time=55518300 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 55528300.0 ps INFO: Read bank 0 col 008, auto precharge 0
|
|
prev_cmd=Read , prev_time=55518300 ps, difference=10000 ps
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55532050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55532050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55532050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55532050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55532050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55532050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55532050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55532050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55533300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55533300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55533300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55533300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55533300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55533300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55533300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55533300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55534550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55534550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55534550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55534550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55534550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55534550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55534550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55534550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55535800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55535800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55535800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55535800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55535800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55535800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55535800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55535800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55537050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55537050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55537050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55537050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55537050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55537050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55537050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55537050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55538300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55538300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55538300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55538300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55538300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55538300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55538300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55538300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55539550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55539550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55539550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55539550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55539550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55539550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55539550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55539550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55540800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55540800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55540800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 77
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|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55540800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 77
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|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55540800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 77
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|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55540800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 77
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|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55540800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 77
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|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55540800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 77
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|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55542050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000008 data = 00
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|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55542050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000008 data = 11
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|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55542050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000008 data = 22
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|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55542050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000008 data = 33
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|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55542050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000008 data = 44
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|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55542050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000008 data = 55
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|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55542050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000008 data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55542050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000008 data = 77
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|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55543300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000009 data = 00
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|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55543300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000009 data = 11
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|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55543300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000009 data = 22
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|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55543300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000009 data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55543300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000009 data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55543300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000009 data = 55
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|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55543300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000009 data = 66
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|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55543300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000009 data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55544550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000a data = 00
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|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55544550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000a data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55544550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000a data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55544550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000a data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55544550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000a data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55544550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000a data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55544550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000a data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55544550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000a data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55545800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000b data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55545800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000b data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55545800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000b data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55545800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000b data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55545800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000b data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55545800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000b data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55545800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000b data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55545800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000b data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55547050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000c data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55547050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000c data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55547050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000c data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55547050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000c data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55547050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000c data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55547050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000c data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55547050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000c data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55547050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000c data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55548300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000d data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55548300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000d data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55548300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000d data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55548300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000d data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55548300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000d data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55548300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000d data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55548300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000d data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55548300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000d data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55549550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000e data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55549550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000e data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55549550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000e data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55549550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000e data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55549550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000e data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55549550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000e data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55549550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000e data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55549550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000e data = 77
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55550800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000f data = 00
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55550800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000f data = 11
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55550800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000f data = 22
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55550800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000f data = 33
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55550800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000f data = 44
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55550800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000f data = 55
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55550800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000f data = 66
|
|
ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55550800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000f data = 77
|
|
$stop called at time : 55575 ns : File "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/new/ddr3_dimm_micron_sim.v" Line 208
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run: Time (s): cpu = 00:05:23 ; elapsed = 00:09:28 . Memory (MB): peak = 10222.301 ; gain = 5.004 ; free physical = 573 ; free virtual = 22626
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save_wave_config {/home/angelo/Desktop/switch_fpga/ddr3_dimm_micron_sim_behav.wcfg}
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