UberDDR3/rtl
AngeloJacobo 10c290f9f8 temp newest version 2023-07-05 19:46:18 +08:00
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ddr3_controller.v pre-refresh delay is now flexible and not fixed. Separated formal properties for testing time parameters 2023-07-05 16:35:57 +08:00
ddr3_controller_copy.v temp newest version 2023-07-05 19:46:18 +08:00
ddr3_phy.v write dqs toggles for half slow clk cycle at the end, needed when DQ is set to be delayed (non-zero flyby delay) 2023-07-05 16:41:55 +08:00
ddr3_top.v add data mask port 2023-06-22 19:52:45 +08:00
fwb_slave.v assume no request when slave busy (calibration or at refresh) 2023-06-29 12:58:41 +08:00