5577 lines
176 KiB
Plaintext
Executable File
5577 lines
176 KiB
Plaintext
Executable File
#! /home/angelo/oss-cad-suite/bin/vvp
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:ivl_version "12.0 (devel)" "(s20150603-1319-g027c4828e)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision + 0;
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:vpi_module "/home/angelo/oss-cad-suite/lib/ivl/system.vpi";
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:vpi_module "/home/angelo/oss-cad-suite/lib/ivl/vhdl_sys.vpi";
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:vpi_module "/home/angelo/oss-cad-suite/lib/ivl/vhdl_textio.vpi";
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:vpi_module "/home/angelo/oss-cad-suite/lib/ivl/v2005_math.vpi";
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:vpi_module "/home/angelo/oss-cad-suite/lib/ivl/va_math.vpi";
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S_0x555555cfe490 .scope module, "ddr3_controller" "ddr3_controller" 2 37;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "i_controller_clk";
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.port_info 1 /INPUT 1 "i_rst_n";
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.port_info 2 /INPUT 1 "i_wb_cyc";
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.port_info 3 /INPUT 1 "i_wb_stb";
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.port_info 4 /INPUT 1 "i_wb_we";
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.port_info 5 /INPUT 26 "i_wb_addr";
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.port_info 6 /INPUT 512 "i_wb_data";
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.port_info 7 /INPUT 64 "i_wb_sel";
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.port_info 8 /INPUT 16 "i_aux";
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.port_info 9 /OUTPUT 1 "o_wb_stall";
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.port_info 10 /OUTPUT 1 "o_wb_ack";
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.port_info 11 /OUTPUT 512 "o_wb_data";
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.port_info 12 /OUTPUT 16 "o_aux";
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.port_info 13 /INPUT 1 "i_wb2_cyc";
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.port_info 14 /INPUT 1 "i_wb2_stb";
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.port_info 15 /INPUT 1 "i_wb2_we";
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.port_info 16 /INPUT 32 "i_wb2_addr";
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.port_info 17 /INPUT 4 "i_wb2_sel";
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.port_info 18 /INPUT 32 "i_wb2_data";
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.port_info 19 /OUTPUT 1 "o_wb2_stall";
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.port_info 20 /OUTPUT 1 "o_wb2_ack";
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.port_info 21 /OUTPUT 32 "o_wb2_data";
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.port_info 22 /INPUT 512 "i_phy_iserdes_data";
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.port_info 23 /INPUT 64 "i_phy_iserdes_dqs";
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.port_info 24 /INPUT 64 "i_phy_iserdes_bitslip_reference";
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.port_info 25 /INPUT 1 "i_phy_idelayctrl_rdy";
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.port_info 26 /OUTPUT 104 "o_phy_cmd";
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.port_info 27 /OUTPUT 1 "o_phy_dqs_tri_control";
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.port_info 28 /OUTPUT 1 "o_phy_dq_tri_control";
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.port_info 29 /OUTPUT 1 "o_phy_toggle_dqs";
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.port_info 30 /OUTPUT 512 "o_phy_data";
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.port_info 31 /OUTPUT 64 "o_phy_dm";
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.port_info 32 /OUTPUT 5 "o_phy_odelay_data_cntvaluein";
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.port_info 33 /OUTPUT 5 "o_phy_odelay_dqs_cntvaluein";
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.port_info 34 /OUTPUT 5 "o_phy_idelay_data_cntvaluein";
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.port_info 35 /OUTPUT 5 "o_phy_idelay_dqs_cntvaluein";
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.port_info 36 /OUTPUT 8 "o_phy_odelay_data_ld";
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.port_info 37 /OUTPUT 8 "o_phy_odelay_dqs_ld";
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.port_info 38 /OUTPUT 8 "o_phy_idelay_data_ld";
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.port_info 39 /OUTPUT 8 "o_phy_idelay_dqs_ld";
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.port_info 40 /OUTPUT 8 "o_phy_bitslip";
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P_0x555555d8d2e0 .param/l "A10_CONTROL" 1 2 122, +C4<00000000000000000000000000011001>;
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P_0x555555d8d320 .param/l "ACTIVATE_SLOT" 1 2 142, C4<00>;
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P_0x555555d8d360 .param/l "ACTIVATE_TO_PRECHARGE_DELAY" 1 2 215, C4<0011>;
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P_0x555555d8d3a0 .param/l "ACTIVATE_TO_READ_DELAY" 1 2 217, C4<0000>;
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P_0x555555d8d3e0 .param/l "ACTIVATE_TO_WRITE_DELAY" 1 2 216, C4<0000>;
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P_0x555555d8d420 .param/l "AL" 1 2 296, C4<00>;
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P_0x555555d8d460 .param/l "ANALYZE_DATA" 1 2 263, +C4<00000000000000000000000000001101>;
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P_0x555555d8d4a0 .param/l "ANALYZE_DQS" 1 2 254, +C4<00000000000000000000000000000100>;
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P_0x555555d8d4e0 .param/l "ASR" 1 2 275, C4<1>;
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P_0x555555d8d520 .param/l "AUX_WIDTH" 0 2 45, C4<00000000000000000000000000010000>;
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P_0x555555d8d560 .param/l "BA_BITS" 0 2 42, C4<00000000000000000000000000000011>;
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P_0x555555d8d5a0 .param/l "BITSLIP_DQS_TRAIN_1" 1 2 251, +C4<00000000000000000000000000000001>;
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P_0x555555d8d5e0 .param/l "BITSLIP_DQS_TRAIN_2" 1 2 256, +C4<00000000000000000000000000000110>;
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P_0x555555d8d620 .param/l "BL" 1 2 306, C4<00>;
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P_0x555555d8d660 .param/l "CALIBRATE_DQS" 1 2 255, +C4<00000000000000000000000000000101>;
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P_0x555555d8d6a0 .param/l "CALIBRATION_DELAY" 1 2 202, +C4<00000000000000000000000000000010>;
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P_0x555555d8d6e0 .param/l "CL" 1 2 307, C4<0100>;
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P_0x555555d8d720 .param/l "CLOCK_EN" 1 2 123, +C4<00000000000000000000000000011000>;
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P_0x555555d8d760 .param/l "CL_nCK" 1 2 198, +C4<00000000000000000000000000000110>;
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P_0x555555d8d7a0 .param/l "CMD_ACT" 1 2 112, C4<0011>;
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P_0x555555d8d7e0 .param/l "CMD_ADDRESS_START" 1 2 138, C4<000000000000000000000000000001111>;
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P_0x555555d8d820 .param/l "CMD_BANK_START" 1 2 137, C4<0000000000000000000000000000010010>;
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P_0x555555d8d860 .param/l "CMD_CAS_N" 1 2 132, C4<000000000000000000000000000000010111>;
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P_0x555555d8d8a0 .param/l "CMD_CKE" 1 2 135, C4<000000000000000000000000000000010100>;
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P_0x555555d8d8e0 .param/l "CMD_CS_N" 1 2 130, C4<000000000000000000000000000000011001>;
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P_0x555555d8d920 .param/l "CMD_DES" 1 2 116, C4<1000>;
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P_0x555555d8d960 .param/l "CMD_MRS" 1 2 109, C4<0000>;
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P_0x555555d8d9a0 .param/l "CMD_NOP" 1 2 115, C4<0111>;
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P_0x555555d8d9e0 .param/l "CMD_ODT" 1 2 134, C4<000000000000000000000000000000010101>;
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P_0x555555d8da20 .param/l "CMD_PRE" 1 2 111, C4<0010>;
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P_0x555555d8da60 .param/l "CMD_RAS_N" 1 2 131, C4<000000000000000000000000000000011000>;
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P_0x555555d8daa0 .param/l "CMD_RD" 1 2 114, C4<0101>;
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P_0x555555d8dae0 .param/l "CMD_REF" 1 2 110, C4<0001>;
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P_0x555555d8db20 .param/l "CMD_RESET_N" 1 2 136, C4<000000000000000000000000000000010011>;
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P_0x555555d8db60 .param/l "CMD_WE_N" 1 2 133, C4<000000000000000000000000000000010110>;
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P_0x555555d8dba0 .param/l "CMD_WR" 1 2 113, C4<0100>;
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P_0x555555d8dbe0 .param/l "CMD_ZQC" 1 2 117, C4<0110>;
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P_0x555555d8dc20 .param/l "COLLECT_DQS" 1 2 253, +C4<00000000000000000000000000000011>;
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P_0x555555d8dc60 .param/l "COL_BITS" 0 2 41, C4<00000000000000000000000000001010>;
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P_0x555555d8dca0 .param/real "CONTROLLER_CLK_PERIOD" 0 2 38, Cr<m5000000000000000gfc5>; value=10.0000
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P_0x555555d8dce0 .param/l "CWL" 1 2 274, C4<000>;
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P_0x555555d8dd20 .param/l "CWL_nCK" 1 2 199, +C4<00000000000000000000000000000101>;
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P_0x555555d8dd60 .param/l "DATA_INITIAL_IDELAY_TAP" 1 2 158, +C4<00000000000000000000000000000000>;
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P_0x555555d8dda0 .param/l "DATA_INITIAL_ODELAY_TAP" 1 2 147, +C4<00000000000000000000000000000000>;
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P_0x555555d8dde0 .param/real "DDR3_CLK_PERIOD" 0 2 39, Cr<m5000000000000000gfc3>; value=2.50000
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P_0x555555d8de20 .param/l "DDR3_CMD_END" 1 2 126, +C4<00000000000000000000000000010011>;
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P_0x555555d8de60 .param/l "DDR3_CMD_START" 1 2 125, +C4<00000000000000000000000000010110>;
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P_0x555555d8dea0 .param/l "DELAY_BEFORE_WRITE_LEVEL_FEEDBACK" 1 2 244, C4<00000000000000000000000000000000001101>;
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P_0x555555d8dee0 .param/l "DELAY_COUNTER_WIDTH" 1 2 201, +C4<00000000000000000000000000010000>;
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P_0x555555d8df20 .param/l "DELAY_MAX_VALUE" 1 2 200, C4<0001100001101010000>;
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P_0x555555d8df60 .param/l "DELAY_SLOT_WIDTH" 1 2 164, +C4<00000000000000000000000000010011>;
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P_0x555555d8dfa0 .param/l "DIC" 1 2 292, C4<00>;
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P_0x555555d8dfe0 .param/l "DLL_EN" 1 2 291, C4<0>;
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P_0x555555d8e020 .param/l "DLL_RST" 1 2 309, C4<1>;
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P_0x555555d8e060 .param/l "DONE_CALIBRATE" 1 2 264, +C4<00000000000000000000000000001110>;
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P_0x555555d8e0a0 .param/l "DQS_INITIAL_IDELAY_TAP" 1 2 159, +C4<00000000000000000000000000001000>;
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P_0x555555d8e0e0 .param/l "DQS_INITIAL_ODELAY_TAP" 1 2 155, +C4<00000000000000000000000000001000>;
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P_0x555555d8e120 .param/l "DQ_BITS" 0 2 43, C4<00000000000000000000000000001000>;
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P_0x555555d8e160 .param/l "IDLE" 1 2 250, +C4<00000000000000000000000000000000>;
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P_0x555555d8e1a0 .param/l "INITIAL_CKE_LOW" 1 2 166, +C4<00000000000001111010000100100000>;
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P_0x555555d8e1e0 .param/l "INITIAL_RESET_INSTRUCTION" 1 2 317, C4<0100001110000000000000000101>;
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P_0x555555d8e220 .param/l "ISSUE_READ" 1 2 261, +C4<00000000000000000000000000001011>;
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P_0x555555d8e260 .param/l "ISSUE_WRITE_1" 1 2 259, +C4<00000000000000000000000000001001>;
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P_0x555555d8e2a0 .param/l "ISSUE_WRITE_2" 1 2 260, +C4<00000000000000000000000000001010>;
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P_0x555555d8e2e0 .param/l "LANES" 0 2 44, C4<00000000000000000000000000001000>;
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P_0x555555d8e320 .param/l "MARGIN_BEFORE_ANTICIPATE" 1 2 231, C4<000101>;
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P_0x555555d8e360 .param/l "MAX_ADDED_READ_ACK_DELAY" 1 2 242, +C4<00000000000000000000000000010000>;
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P_0x555555d8e3a0 .param/l "MPR_DIS" 1 2 284, C4<0>;
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P_0x555555d8e3e0 .param/l "MPR_EN" 1 2 283, C4<1>;
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P_0x555555d8e420 .param/l "MPR_LOC" 1 2 282, C4<00>;
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P_0x555555d8e460 .param/l "MPR_READ" 1 2 252, +C4<00000000000000000000000000000010>;
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P_0x555555d8e4a0 .param/l "MR0" 1 2 315, C4<0000000011100100000>;
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P_0x555555d8e4e0 .param/l "MR0_SEL" 1 2 314, C4<000>;
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P_0x555555d8e520 .param/l "MR1_SEL" 1 2 301, C4<001>;
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P_0x555555d8e560 .param/l "MR1_WL_DIS" 1 2 303, C4<0010000100001000100>;
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P_0x555555d8e5a0 .param/l "MR1_WL_EN" 1 2 302, C4<0010000100011000100>;
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P_0x555555d8e5e0 .param/l "MR2" 1 2 279, C4<0100000000001000000>;
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P_0x555555d8e620 .param/l "MR2_SEL" 1 2 278, C4<010>;
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P_0x555555d8e660 .param/l "MR3_MPR_DIS" 1 2 287, C4<0110000000000000000>;
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P_0x555555d8e6a0 .param/l "MR3_MPR_EN" 1 2 286, C4<0110000000000000100>;
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P_0x555555d8e6e0 .param/l "MR3_RD_ADDR" 1 2 288, C4<0000000000000000000>;
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P_0x555555d8e720 .param/l "MR3_SEL" 1 2 285, C4<011>;
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P_0x555555d8e760 .param/l "MRS_BANK_START" 1 2 127, +C4<00000000000000000000000000010010>;
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P_0x555555d8e7a0 .param/l "OPT_BUS_ABORT" 0 2 49, C4<1>;
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P_0x555555d8e7e0 .param/l "OPT_LOWPOWER" 0 2 48, C4<1>;
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P_0x555555d8e820 .param/l "PASR" 1 2 273, C4<000>;
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P_0x555555d8e860 .param/l "POWER_ON_RESET_HIGH" 1 2 165, +C4<00000000000000110000110101000000>;
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P_0x555555d8e8a0 .param/l "PPD" 1 2 313, C4<0>;
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P_0x555555d8e8e0 .param/l "PRECHARGE_SLOT" 1 2 143, C4<01>;
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P_0x555555d8e920 .param/l "PRECHARGE_TO_ACTIVATE_DELAY" 1 2 214, C4<0001>;
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P_0x555555d8e960 .param/l "PRE_REFRESH_DELAY" 1 2 203, C4<000000000000000000000000000000101>;
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P_0x555555d8e9a0 .param/l "QOFF" 1 2 300, C4<0>;
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P_0x555555d8e9e0 .param/l "RBT" 1 2 308, C4<0>;
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P_0x555555d8ea20 .param/l "READ_ACK_PIPE_WIDTH" 1 2 241, +C4<000000000000000000000000000000000110>;
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P_0x555555d8ea60 .param/l "READ_DATA" 1 2 262, +C4<00000000000000000000000000001100>;
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P_0x555555d8eaa0 .param/l "READ_DELAY" 1 2 240, +C4<00000000000000000000000000000001>;
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P_0x555555d8eae0 .param/l "READ_SLOT" 1 2 140, C4<10>;
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P_0x555555d8eb20 .param/l "READ_TO_PRECHARGE_DELAY" 1 2 220, C4<0001>;
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P_0x555555d8eb60 .param/l "READ_TO_READ_DELAY" 1 2 219, C4<0000>;
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P_0x555555d8eba0 .param/l "READ_TO_WRITE_DELAY" 1 2 218, C4<0001>;
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P_0x555555d8ebe0 .param/l "REF_IDLE" 1 2 120, +C4<00000000000000000000000000011011>;
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P_0x555555d8ec20 .param/l "REPEAT_DQS_ANALYZE" 1 2 266, +C4<00000000000000000000000000000001>;
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P_0x555555d8ec60 .param/l "RESET_N" 1 2 124, +C4<00000000000000000000000000010111>;
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P_0x555555d8eca0 .param/l "ROW_BITS" 0 2 40, C4<00000000000000000000000000010000>;
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P_0x555555d8ece0 .param/l "RST_DONE" 1 2 119, +C4<00000000000000000000000000011011>;
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P_0x555555d8ed20 .param/l "RTT_NOM" 1 2 293, C4<011>;
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P_0x555555d8ed60 .param/l "RTT_WR" 1 2 277, C4<00>;
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P_0x555555d8eda0 .param/l "SRT" 1 2 276, C4<0>;
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P_0x555555d8ede0 .param/l "STAGE2_DATA_DEPTH" 1 2 232, C4<000000000000000000000000000000000010>;
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P_0x555555d8ee20 .param/l "START_WRITE_LEVEL" 1 2 257, +C4<00000000000000000000000000000111>;
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P_0x555555d8ee60 .param/l "STORED_DQS_SIZE" 1 2 265, +C4<00000000000000000000000000000101>;
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P_0x555555d8eea0 .param/l "TDQS" 1 2 297, C4<1>;
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P_0x555555d8eee0 .param/l "USE_TIMER" 1 2 121, +C4<00000000000000000000000000011010>;
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P_0x555555d8ef20 .param/l "WAIT_FOR_FEEDBACK" 1 2 258, +C4<00000000000000000000000000001000>;
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P_0x555555d8ef60 .param/l "WB2_ADDR_BITS" 0 2 46, C4<00000000000000000000000000100000>;
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P_0x555555d8efa0 .param/l "WB2_DATA_BITS" 0 2 47, C4<00000000000000000000000000100000>;
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P_0x555555d8efe0 .param/l "WL_DIS" 1 2 295, C4<0>;
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P_0x555555d8f020 .param/l "WL_EN" 1 2 294, C4<1>;
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P_0x555555d8f060 .param/l "WR" 1 2 311, C4<011>;
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P_0x555555d8f0a0 .param/l "WRITE_SLOT" 1 2 141, C4<11>;
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P_0x555555d8f0e0 .param/l "WRITE_TO_PRECHARGE_DELAY" 1 2 223, C4<0100>;
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P_0x555555d8f120 .param/l "WRITE_TO_READ_DELAY" 1 2 222, C4<0011>;
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P_0x555555d8f160 .param/l "WRITE_TO_WRITE_DELAY" 1 2 221, C4<0000>;
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P_0x555555d8f1a0 .param/l "cmd_len" 0 2 58, C4<00000000000000000000000000000011010>;
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P_0x555555d8f1e0 .param/l "serdes_ratio" 0 2 52, +C4<00000000000000000000000000000100>;
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P_0x555555d8f220 .param/l "tCCD" 1 2 193, +C4<00000000000000000000000000000100>;
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P_0x555555d8f260 .param/l "tMOD" 1 2 195, C4<0000000000000000011>;
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P_0x555555d8f2a0 .param/l "tMRD" 1 2 185, +C4<00000000000000000000000000000100>;
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P_0x555555d8f2e0 .param/l "tRAS" 1 2 170, +C4<00000000000000000000000000100011>;
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P_0x555555d8f320 .param/real "tRCD" 1 2 168, Cr<m6e00000000000000gfc5>; value=13.7500
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P_0x555555d8f360 .param/l "tREFI" 1 2 182, +C4<00000000000000000001111001111000>;
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P_0x555555d8f3a0 .param/real "tRFC" 1 2 180, Cr<m5780000000000000gfca>; value=350.000
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P_0x555555d8f3e0 .param/real "tRP" 1 2 169, Cr<m6e00000000000000gfc5>; value=13.7500
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P_0x555555d8f420 .param/l "tRTP" 1 2 191, +C4<00000000000000000000000000001010>;
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P_0x555555d8f460 .param/l "tWLMRD" 1 2 188, C4<0000000000000001010>;
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P_0x555555d8f4a0 .param/real "tWLO" 1 2 189, Cr<m7800000000000000gfc4>; value=7.50000
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P_0x555555d8f4e0 .param/l "tWLOE" 1 2 190, +C4<00000000000000000000000000000010>;
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P_0x555555d8f520 .param/real "tWR" 1 2 186, Cr<m7800000000000000gfc5>; value=15.0000
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P_0x555555d8f560 .param/l "tWTR" 1 2 187, +C4<00000000000000000000000000001010>;
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P_0x555555d8f5a0 .param/l "tXPR" 1 2 184, +C4<00000000000000000000000101101000>;
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P_0x555555d8f5e0 .param/l "tZQinit" 1 2 196, C4<0000000000010000000>;
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P_0x555555d8f620 .param/l "wb2_sel_bits" 0 2 56, C4<00000000000000000000000000000100>;
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P_0x555555d8f660 .param/l "wb_addr_bits" 0 2 53, C4<00000000000000000000000000000011010>;
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P_0x555555d8f6a0 .param/l "wb_data_bits" 0 2 54, C4<00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000>;
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P_0x555555d8f6e0 .param/l "wb_sel_bits" 0 2 55, C4<00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000>;
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v0x555555db2260_1 .array/port v0x555555db2260, 1;
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L_0x555555d13d90 .functor BUFZ 512, v0x555555db2260_1, C4<00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000>, C4<00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000>, C4<00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000>;
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v0x555555db2460_1 .array/port v0x555555db2460, 1;
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L_0x555555d211c0 .functor BUFZ 64, v0x555555db2460_1, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>;
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L_0x555555d539f0 .functor AND 1, L_0x555555db62a0, L_0x555555dc6540, C4<1>, C4<1>;
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L_0x555555d61dc0 .functor BUFZ 512, L_0x555555dc6880, C4<00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000>, C4<00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000>, C4<00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000>;
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L_0x555555dc6f20 .functor BUFZ 5, L_0x555555dc72e0, C4<00000>, C4<00000>, C4<00000>;
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L_0x555555d6eaf0 .functor BUFZ 5, L_0x555555dc7600, C4<00000>, C4<00000>, C4<00000>;
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L_0x555555dc7c20 .functor BUFZ 5, L_0x555555dc7990, C4<00000>, C4<00000>, C4<00000>;
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L_0x555555dc7e40 .functor BUFZ 5, L_0x555555dc7810, C4<00000>, C4<00000>, C4<00000>;
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v0x555555da9120_0 .net *"_ivl_15", 0 0, L_0x555555db62a0; 1 drivers
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v0x555555da9220_0 .net *"_ivl_16", 31 0, L_0x555555db63a0; 1 drivers
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L_0x7eff80b5c018 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
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v0x555555da9300_0 .net *"_ivl_19", 26 0, L_0x7eff80b5c018; 1 drivers
|
|
L_0x7eff80b5c060 .functor BUFT 1, C4<00000000000000000000000000001110>, C4<0>, C4<0>, C4<0>;
|
|
v0x555555da93c0_0 .net/2u *"_ivl_20", 31 0, L_0x7eff80b5c060; 1 drivers
|
|
v0x555555da94a0_0 .net *"_ivl_22", 0 0, L_0x555555dc6540; 1 drivers
|
|
v0x555555da95b0_0 .net *"_ivl_29", 511 0, L_0x555555dc6880; 1 drivers
|
|
v0x555555da9690_0 .net *"_ivl_31", 2 0, L_0x555555dc6920; 1 drivers
|
|
L_0x7eff80b5c0a8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
|
|
v0x555555da9770_0 .net *"_ivl_34", 1 0, L_0x7eff80b5c0a8; 1 drivers
|
|
v0x555555da9850_0 .net *"_ivl_38", 0 0, L_0x555555dc6b30; 1 drivers
|
|
v0x555555da99c0_0 .net *"_ivl_42", 0 0, L_0x555555dc6d80; 1 drivers
|
|
v0x555555da9aa0_0 .net *"_ivl_45", 31 0, L_0x555555dc6f90; 1 drivers
|
|
L_0x7eff80b5c0f0 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
|
|
v0x555555da9b80_0 .net *"_ivl_48", 26 0, L_0x7eff80b5c0f0; 1 drivers
|
|
L_0x7eff80b5c138 .functor BUFT 1, C4<00000000000000000000000000000010>, C4<0>, C4<0>, C4<0>;
|
|
v0x555555da9c60_0 .net/2u *"_ivl_49", 31 0, L_0x7eff80b5c138; 1 drivers
|
|
v0x555555da9d40_0 .net *"_ivl_55", 4 0, L_0x555555dc72e0; 1 drivers
|
|
v0x555555da9e20_0 .net *"_ivl_57", 4 0, L_0x555555dc73b0; 1 drivers
|
|
L_0x7eff80b5c1c8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
|
|
v0x555555da9f00_0 .net *"_ivl_60", 1 0, L_0x7eff80b5c1c8; 1 drivers
|
|
v0x555555da9fe0_0 .net *"_ivl_63", 4 0, L_0x555555dc7600; 1 drivers
|
|
v0x555555daa0c0_0 .net *"_ivl_65", 4 0, L_0x555555dc76d0; 1 drivers
|
|
L_0x7eff80b5c210 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
|
|
v0x555555daa1a0_0 .net *"_ivl_68", 1 0, L_0x7eff80b5c210; 1 drivers
|
|
v0x555555daa280_0 .net *"_ivl_71", 4 0, L_0x555555dc7990; 1 drivers
|
|
v0x555555daa360_0 .net *"_ivl_73", 4 0, L_0x555555dc7a30; 1 drivers
|
|
L_0x7eff80b5c258 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
|
|
v0x555555daa440_0 .net *"_ivl_76", 1 0, L_0x7eff80b5c258; 1 drivers
|
|
v0x555555daa520_0 .net *"_ivl_79", 4 0, L_0x555555dc7810; 1 drivers
|
|
v0x555555daa600_0 .net *"_ivl_81", 4 0, L_0x555555dc7c90; 1 drivers
|
|
L_0x7eff80b5c2a0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
|
|
v0x555555daa6e0_0 .net *"_ivl_84", 1 0, L_0x7eff80b5c2a0; 1 drivers
|
|
v0x555555daa7c0_0 .net *"_ivl_88", 0 0, L_0x555555dc7f50; 1 drivers
|
|
L_0x7eff80b5c2e8 .functor BUFT 1, C4<000010>, C4<0>, C4<0>, C4<0>;
|
|
v0x555555daa8a0_0 .net/2u *"_ivl_89", 5 0, L_0x7eff80b5c2e8; 1 drivers
|
|
v0x555555daa980_0 .net *"_ivl_91", 5 0, L_0x555555dc8050; 1 drivers
|
|
L_0x7eff80b5c330 .functor BUFT 1, C4<000001>, C4<0>, C4<0>, C4<0>;
|
|
v0x555555daaa60_0 .net/2u *"_ivl_93", 5 0, L_0x7eff80b5c330; 1 drivers
|
|
v0x555555daab40_0 .net *"_ivl_95", 5 0, L_0x555555dc8300; 1 drivers
|
|
v0x555555daac20_0 .var "activate_slot_busy", 0 0;
|
|
v0x555555daace0 .array "added_read_pipe", 0 7, 3 0;
|
|
v0x555555daada0_0 .var "added_read_pipe_max", 3 0;
|
|
v0x555555daae80 .array "bank_active_row_d", 0 7, 15 0;
|
|
v0x555555dab040 .array "bank_active_row_q", 0 7, 15 0;
|
|
v0x555555dab250_0 .var "bank_status_d", 7 0;
|
|
v0x555555dab330_0 .var "bank_status_q", 7 0;
|
|
v0x555555dab410_0 .var "cmd_ck_en", 0 0;
|
|
v0x555555dab4d0 .array "cmd_d", 0 3, 25 0;
|
|
v0x555555dab610_0 .var "cmd_odt", 0 0;
|
|
v0x555555dab6d0_0 .var "cmd_odt_q", 0 0;
|
|
v0x555555dab790 .array "cmd_q", 0 3, 25 0;
|
|
v0x555555dab850_0 .var "cmd_reset_n", 0 0;
|
|
v0x555555dab910 .array "data_start_index", 0 7, 6 0;
|
|
v0x555555dab9d0 .array "delay_before_activate_counter_d", 0 7, 3 0;
|
|
v0x555555daba90 .array "delay_before_activate_counter_q", 0 7, 3 0;
|
|
v0x555555dabca0 .array "delay_before_precharge_counter_d", 0 7, 3 0;
|
|
v0x555555dabd60 .array "delay_before_precharge_counter_q", 0 7, 3 0;
|
|
v0x555555dabf70 .array "delay_before_read_counter_d", 0 7, 3 0;
|
|
v0x555555dac180 .array "delay_before_read_counter_q", 0 7, 3 0;
|
|
v0x555555dac390_0 .var "delay_before_read_data", 3 0;
|
|
v0x555555dac470 .array "delay_before_write_counter_d", 0 7, 3 0;
|
|
v0x555555dac680 .array "delay_before_write_counter_q", 0 7, 3 0;
|
|
v0x555555dac890_0 .var "delay_before_write_level_feedback", 4 0;
|
|
v0x555555dac970_0 .var "delay_counter", 15 0;
|
|
v0x555555daca50_0 .var "delay_counter_is_zero", 0 0;
|
|
v0x555555dacb10 .array "delay_read_pipe", 0 1, 15 0;
|
|
v0x555555dacbd0_0 .var "dq_target_index", 5 0;
|
|
v0x555555daccb0_0 .var "dqs_bitslip_arrangement", 15 0;
|
|
v0x555555dacd90_0 .var "dqs_count_repeat", 3 0;
|
|
v0x555555dace70_0 .var "dqs_start_index", 5 0;
|
|
v0x555555dacf50_0 .var "dqs_start_index_repeat", 0 0;
|
|
v0x555555dad030_0 .var "dqs_start_index_stored", 5 0;
|
|
v0x555555dad110_0 .var "dqs_store", 39 0;
|
|
v0x555555dad1f0_0 .var "dqs_target_index", 5 0;
|
|
v0x555555dad2d0_0 .var "dqs_target_index_orig", 5 0;
|
|
v0x555555dad3b0_0 .net "dqs_target_index_value", 5 0, L_0x555555dc83f0; 1 drivers
|
|
o0x7eff80ba6c38 .functor BUFZ 16, C4<zzzzzzzzzzzzzzzz>; HiZ drive
|
|
v0x555555dad490_0 .net "i_aux", 15 0, o0x7eff80ba6c38; 0 drivers
|
|
o0x7eff80ba6c68 .functor BUFZ 1, C4<z>; HiZ drive
|
|
v0x555555dad570_0 .net "i_controller_clk", 0 0, o0x7eff80ba6c68; 0 drivers
|
|
o0x7eff80ba6c98 .functor BUFZ 1, C4<z>; HiZ drive
|
|
v0x555555dad630_0 .net "i_phy_idelayctrl_rdy", 0 0, o0x7eff80ba6c98; 0 drivers
|
|
o0x7eff80ba6cc8 .functor BUFZ 64, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
|
|
v0x555555dad6f0_0 .net "i_phy_iserdes_bitslip_reference", 63 0, o0x7eff80ba6cc8; 0 drivers
|
|
o0x7eff80ba6cf8 .functor BUFZ 512, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
|
|
v0x555555dad7d0_0 .net "i_phy_iserdes_data", 511 0, o0x7eff80ba6cf8; 0 drivers
|
|
o0x7eff80ba6d28 .functor BUFZ 64, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
|
|
v0x555555dad8b0_0 .net "i_phy_iserdes_dqs", 63 0, o0x7eff80ba6d28; 0 drivers
|
|
o0x7eff80ba6d58 .functor BUFZ 1, C4<z>; HiZ drive
|
|
v0x555555dad990_0 .net "i_rst_n", 0 0, o0x7eff80ba6d58; 0 drivers
|
|
o0x7eff80ba6d88 .functor BUFZ 32, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
|
|
v0x555555dada50_0 .net "i_wb2_addr", 31 0, o0x7eff80ba6d88; 0 drivers
|
|
o0x7eff80ba6db8 .functor BUFZ 1, C4<z>; HiZ drive
|
|
v0x555555dadb30_0 .net "i_wb2_cyc", 0 0, o0x7eff80ba6db8; 0 drivers
|
|
o0x7eff80ba6de8 .functor BUFZ 32, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
|
|
v0x555555dadbf0_0 .net "i_wb2_data", 31 0, o0x7eff80ba6de8; 0 drivers
|
|
o0x7eff80ba6e18 .functor BUFZ 4, C4<zzzz>; HiZ drive
|
|
v0x555555dadcd0_0 .net "i_wb2_sel", 3 0, o0x7eff80ba6e18; 0 drivers
|
|
o0x7eff80ba6e48 .functor BUFZ 1, C4<z>; HiZ drive
|
|
v0x555555daddb0_0 .net "i_wb2_stb", 0 0, o0x7eff80ba6e48; 0 drivers
|
|
o0x7eff80ba6e78 .functor BUFZ 1, C4<z>; HiZ drive
|
|
v0x555555dade70_0 .net "i_wb2_we", 0 0, o0x7eff80ba6e78; 0 drivers
|
|
o0x7eff80ba6ea8 .functor BUFZ 26, C4<zzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
|
|
v0x555555dadf30_0 .net "i_wb_addr", 25 0, o0x7eff80ba6ea8; 0 drivers
|
|
o0x7eff80ba6ed8 .functor BUFZ 1, C4<z>; HiZ drive
|
|
v0x555555dae010_0 .net "i_wb_cyc", 0 0, o0x7eff80ba6ed8; 0 drivers
|
|
o0x7eff80ba6f08 .functor BUFZ 512, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
|
|
v0x555555dae0d0_0 .net "i_wb_data", 511 0, o0x7eff80ba6f08; 0 drivers
|
|
o0x7eff80ba6f38 .functor BUFZ 64, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
|
|
v0x555555dae1b0_0 .net "i_wb_sel", 63 0, o0x7eff80ba6f38; 0 drivers
|
|
o0x7eff80ba6f68 .functor BUFZ 1, C4<z>; HiZ drive
|
|
v0x555555dae290_0 .net "i_wb_stb", 0 0, o0x7eff80ba6f68; 0 drivers
|
|
o0x7eff80ba6f98 .functor BUFZ 1, C4<z>; HiZ drive
|
|
v0x555555dae350_0 .net "i_wb_we", 0 0, o0x7eff80ba6f98; 0 drivers
|
|
v0x555555dae410 .array "idelay_data_cntvaluein", 0 7, 4 0;
|
|
v0x555555dae4d0_0 .var "idelay_data_cntvaluein_prev", 4 0;
|
|
v0x555555dae5b0 .array "idelay_dqs_cntvaluein", 0 7, 4 0;
|
|
v0x555555dae670_0 .var/i "index", 31 0;
|
|
v0x555555dae750_0 .var "index_read_pipe", 0 0;
|
|
v0x555555dae810_0 .var "index_wb_data", 0 0;
|
|
v0x555555dae8d0_0 .var "initial_dqs", 0 0;
|
|
v0x555555dae990_0 .var "instruction", 27 0;
|
|
v0x555555daea70_0 .var "instruction_address", 4 0;
|
|
v0x555555daeb50_0 .net "issue_read_command", 0 0, L_0x555555dc7120; 1 drivers
|
|
L_0x7eff80b5c180 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
|
v0x555555daec10_0 .net "issue_write_command", 0 0, L_0x7eff80b5c180; 1 drivers
|
|
v0x555555daecd0_0 .var "lane", 2 0;
|
|
v0x555555daedb0_0 .net "o_aux", 15 0, L_0x555555dc6750; 1 drivers
|
|
v0x555555daee90_0 .var "o_phy_bitslip", 7 0;
|
|
v0x555555daef70_0 .net "o_phy_cmd", 103 0, L_0x555555db60e0; 1 drivers
|
|
v0x555555daf050_0 .net "o_phy_data", 511 0, L_0x555555d13d90; 1 drivers
|
|
v0x555555daf130_0 .net "o_phy_dm", 63 0, L_0x555555d211c0; 1 drivers
|
|
v0x555555daf210_0 .net "o_phy_dq_tri_control", 0 0, L_0x555555dc6e50; 1 drivers
|
|
v0x555555daf2d0_0 .net "o_phy_dqs_tri_control", 0 0, L_0x555555dc6c00; 1 drivers
|
|
v0x555555daf390_0 .net "o_phy_idelay_data_cntvaluein", 4 0, L_0x555555dc7c20; 1 drivers
|
|
v0x555555daf470_0 .var "o_phy_idelay_data_ld", 7 0;
|
|
v0x555555daf550_0 .net "o_phy_idelay_dqs_cntvaluein", 4 0, L_0x555555dc7e40; 1 drivers
|
|
v0x555555daf630_0 .var "o_phy_idelay_dqs_ld", 7 0;
|
|
v0x555555daf710_0 .net "o_phy_odelay_data_cntvaluein", 4 0, L_0x555555dc6f20; 1 drivers
|
|
v0x555555daf7f0_0 .var "o_phy_odelay_data_ld", 7 0;
|
|
v0x555555daf8d0_0 .net "o_phy_odelay_dqs_cntvaluein", 4 0, L_0x555555d6eaf0; 1 drivers
|
|
v0x555555daf9b0_0 .var "o_phy_odelay_dqs_ld", 7 0;
|
|
v0x555555dafa90_0 .net "o_phy_toggle_dqs", 0 0, L_0x555555db5f50; 1 drivers
|
|
v0x555555dafb50_0 .var "o_wb2_ack", 0 0;
|
|
v0x555555dafc10_0 .var "o_wb2_data", 31 0;
|
|
v0x555555dafcf0_0 .var "o_wb2_stall", 0 0;
|
|
v0x555555dafdb0_0 .net "o_wb_ack", 0 0, L_0x555555d539f0; 1 drivers
|
|
v0x555555dafe70 .array "o_wb_ack_read_q", 0 15, 16 0;
|
|
v0x555555db0130_0 .net "o_wb_data", 511 0, L_0x555555d61dc0; 1 drivers
|
|
v0x555555db0210 .array "o_wb_data_q", 0 1, 511 0;
|
|
v0x555555db02d0_0 .var "o_wb_stall", 0 0;
|
|
v0x555555db0390_0 .var "o_wb_stall_d", 0 0;
|
|
v0x555555db0450_0 .var "o_wb_stall_q", 0 0;
|
|
v0x555555db0510 .array "odelay_data_cntvaluein", 0 7, 4 0;
|
|
v0x555555db05d0 .array "odelay_dqs_cntvaluein", 0 7, 4 0;
|
|
v0x555555db0690_0 .var "pause_counter", 0 0;
|
|
v0x555555db0750_0 .var "precharge_slot_busy", 0 0;
|
|
v0x555555db0810_0 .var "prev_write_level_feedback", 0 0;
|
|
v0x555555db10e0_0 .var "read_data_store", 511 0;
|
|
v0x555555db11c0_0 .var "reset_done", 0 0;
|
|
v0x555555db1280 .array "shift_reg_read_pipe_d", 0 5, 16 0;
|
|
v0x555555db1340 .array "shift_reg_read_pipe_q", 0 5, 16 0;
|
|
v0x555555db14c0_0 .var "stage1_aux", 15 0;
|
|
v0x555555db15a0_0 .var "stage1_bank", 2 0;
|
|
v0x555555db1680_0 .var "stage1_col", 9 0;
|
|
v0x555555db1760_0 .var "stage1_data", 511 0;
|
|
v0x555555db1840_0 .var "stage1_dm", 63 0;
|
|
v0x555555db1920_0 .var "stage1_issue_command", 0 0;
|
|
v0x555555db1a00_0 .var "stage1_next_bank", 2 0;
|
|
v0x555555db1ae0_0 .var "stage1_next_col", 9 0;
|
|
v0x555555db1bc0_0 .var "stage1_next_row", 15 0;
|
|
v0x555555db1ca0_0 .var "stage1_pending", 0 0;
|
|
v0x555555db1d60_0 .var "stage1_row", 15 0;
|
|
v0x555555db1e40_0 .var "stage1_stall", 0 0;
|
|
v0x555555db1f00_0 .var "stage1_we", 0 0;
|
|
v0x555555db1fc0_0 .var "stage2_aux", 15 0;
|
|
v0x555555db20a0_0 .var "stage2_bank", 2 0;
|
|
v0x555555db2180_0 .var "stage2_col", 9 0;
|
|
v0x555555db2260 .array "stage2_data", 0 1, 511 0;
|
|
v0x555555db2380_0 .var "stage2_data_unaligned", 511 0;
|
|
v0x555555db2460 .array "stage2_dm", 0 1, 63 0;
|
|
v0x555555db2580_0 .var "stage2_dm_unaligned", 63 0;
|
|
v0x555555db2660_0 .var "stage2_issue_command", 0 0;
|
|
v0x555555db2740_0 .var "stage2_pending", 0 0;
|
|
v0x555555db2800_0 .var "stage2_row", 15 0;
|
|
v0x555555db28e0_0 .var "stage2_stall", 0 0;
|
|
v0x555555db29a0_0 .var "stage2_update", 0 0;
|
|
v0x555555db2a60_0 .var "stage2_we", 0 0;
|
|
v0x555555db2b20_0 .var "state_calibrate", 4 0;
|
|
v0x555555db2c00_0 .var "train_delay", 1 0;
|
|
v0x555555db2ce0 .array "unaligned_data", 0 7, 63 0;
|
|
v0x555555db2da0 .array "unaligned_dm", 0 7, 7 0;
|
|
v0x555555db2e60_0 .var "wb2_addr", 31 0;
|
|
v0x555555db2f40_0 .var "wb2_data", 31 0;
|
|
v0x555555db3020_0 .var "wb2_phy_idelay_data_cntvaluein", 4 0;
|
|
v0x555555db3100_0 .var "wb2_phy_idelay_data_ld", 7 0;
|
|
v0x555555db31e0_0 .var "wb2_phy_idelay_dqs_cntvaluein", 4 0;
|
|
v0x555555db32c0_0 .var "wb2_phy_idelay_dqs_ld", 7 0;
|
|
v0x555555db33a0_0 .var "wb2_phy_odelay_data_cntvaluein", 4 0;
|
|
v0x555555db3480_0 .var "wb2_phy_odelay_data_ld", 7 0;
|
|
v0x555555db3560_0 .var "wb2_phy_odelay_dqs_cntvaluein", 4 0;
|
|
v0x555555db3640_0 .var "wb2_phy_odelay_dqs_ld", 7 0;
|
|
v0x555555db3720_0 .var "wb2_sel", 3 0;
|
|
v0x555555db3800_0 .var "wb2_stb", 0 0;
|
|
v0x555555db38c0_0 .var "wb2_update", 0 0;
|
|
v0x555555db3980_0 .var "wb2_we", 0 0;
|
|
v0x555555db3a40_0 .var "wb2_write_lane", 2 0;
|
|
v0x555555db3b20_0 .var "write_calib_aux", 15 0;
|
|
v0x555555db3c00_0 .var "write_calib_col", 9 0;
|
|
v0x555555db3ce0_0 .var "write_calib_data", 511 0;
|
|
v0x555555db3dc0_0 .var "write_calib_dq", 0 0;
|
|
v0x555555db3e80_0 .var "write_calib_dqs", 0 0;
|
|
v0x555555db3f40_0 .var "write_calib_odt", 0 0;
|
|
v0x555555db4000_0 .var "write_calib_stb", 0 0;
|
|
v0x555555db40c0_0 .var "write_calib_we", 0 0;
|
|
v0x555555db4180_0 .var "write_dq", 3 0;
|
|
v0x555555db4260_0 .var "write_dq_d", 0 0;
|
|
v0x555555db4320_0 .var "write_dq_q", 0 0;
|
|
v0x555555db43e0_0 .var "write_dqs", 2 0;
|
|
v0x555555db44c0_0 .var "write_dqs_d", 0 0;
|
|
v0x555555db4580_0 .var "write_dqs_q", 1 0;
|
|
v0x555555db4660_0 .var "write_dqs_val", 2 0;
|
|
v0x555555db4740_0 .var "write_pattern", 127 0;
|
|
E_0x555555cb9a50/0 .event negedge, v0x555555dad990_0;
|
|
E_0x555555cb9a50/1 .event posedge, v0x555555dad570_0;
|
|
E_0x555555cb9a50 .event/or E_0x555555cb9a50/0, E_0x555555cb9a50/1;
|
|
E_0x555555ba4230/0 .event anyedge, v0x555555dab6d0_0, v0x555555db3f40_0, v0x555555dae990_0, v0x555555db3e80_0;
|
|
v0x555555dab040_0 .array/port v0x555555dab040, 0;
|
|
v0x555555dab040_1 .array/port v0x555555dab040, 1;
|
|
E_0x555555ba4230/1 .event anyedge, v0x555555db3dc0_0, v0x555555dab330_0, v0x555555dab040_0, v0x555555dab040_1;
|
|
v0x555555dab040_2 .array/port v0x555555dab040, 2;
|
|
v0x555555dab040_3 .array/port v0x555555dab040, 3;
|
|
v0x555555dab040_4 .array/port v0x555555dab040, 4;
|
|
v0x555555dab040_5 .array/port v0x555555dab040, 5;
|
|
E_0x555555ba4230/2 .event anyedge, v0x555555dab040_2, v0x555555dab040_3, v0x555555dab040_4, v0x555555dab040_5;
|
|
v0x555555dab040_6 .array/port v0x555555dab040, 6;
|
|
v0x555555dab040_7 .array/port v0x555555dab040, 7;
|
|
E_0x555555ba4230/3 .event anyedge, v0x555555dab040_6, v0x555555dab040_7, v0x555555daca50_0, v0x555555dab610_0;
|
|
E_0x555555ba4230/4 .event anyedge, v0x555555daeb50_0, v0x555555dab410_0, v0x555555dab850_0, v0x555555daec10_0;
|
|
v0x555555dabd60_0 .array/port v0x555555dabd60, 0;
|
|
v0x555555dabd60_1 .array/port v0x555555dabd60, 1;
|
|
v0x555555dabd60_2 .array/port v0x555555dabd60, 2;
|
|
v0x555555dabd60_3 .array/port v0x555555dabd60, 3;
|
|
E_0x555555ba4230/5 .event anyedge, v0x555555dabd60_0, v0x555555dabd60_1, v0x555555dabd60_2, v0x555555dabd60_3;
|
|
v0x555555dabd60_4 .array/port v0x555555dabd60, 4;
|
|
v0x555555dabd60_5 .array/port v0x555555dabd60, 5;
|
|
v0x555555dabd60_6 .array/port v0x555555dabd60, 6;
|
|
v0x555555dabd60_7 .array/port v0x555555dabd60, 7;
|
|
E_0x555555ba4230/6 .event anyedge, v0x555555dabd60_4, v0x555555dabd60_5, v0x555555dabd60_6, v0x555555dabd60_7;
|
|
v0x555555daba90_0 .array/port v0x555555daba90, 0;
|
|
v0x555555daba90_1 .array/port v0x555555daba90, 1;
|
|
v0x555555daba90_2 .array/port v0x555555daba90, 2;
|
|
v0x555555daba90_3 .array/port v0x555555daba90, 3;
|
|
E_0x555555ba4230/7 .event anyedge, v0x555555daba90_0, v0x555555daba90_1, v0x555555daba90_2, v0x555555daba90_3;
|
|
v0x555555daba90_4 .array/port v0x555555daba90, 4;
|
|
v0x555555daba90_5 .array/port v0x555555daba90, 5;
|
|
v0x555555daba90_6 .array/port v0x555555daba90, 6;
|
|
v0x555555daba90_7 .array/port v0x555555daba90, 7;
|
|
E_0x555555ba4230/8 .event anyedge, v0x555555daba90_4, v0x555555daba90_5, v0x555555daba90_6, v0x555555daba90_7;
|
|
v0x555555dac680_0 .array/port v0x555555dac680, 0;
|
|
v0x555555dac680_1 .array/port v0x555555dac680, 1;
|
|
v0x555555dac680_2 .array/port v0x555555dac680, 2;
|
|
v0x555555dac680_3 .array/port v0x555555dac680, 3;
|
|
E_0x555555ba4230/9 .event anyedge, v0x555555dac680_0, v0x555555dac680_1, v0x555555dac680_2, v0x555555dac680_3;
|
|
v0x555555dac680_4 .array/port v0x555555dac680, 4;
|
|
v0x555555dac680_5 .array/port v0x555555dac680, 5;
|
|
v0x555555dac680_6 .array/port v0x555555dac680, 6;
|
|
v0x555555dac680_7 .array/port v0x555555dac680, 7;
|
|
E_0x555555ba4230/10 .event anyedge, v0x555555dac680_4, v0x555555dac680_5, v0x555555dac680_6, v0x555555dac680_7;
|
|
v0x555555dac180_0 .array/port v0x555555dac180, 0;
|
|
v0x555555dac180_1 .array/port v0x555555dac180, 1;
|
|
v0x555555dac180_2 .array/port v0x555555dac180, 2;
|
|
v0x555555dac180_3 .array/port v0x555555dac180, 3;
|
|
E_0x555555ba4230/11 .event anyedge, v0x555555dac180_0, v0x555555dac180_1, v0x555555dac180_2, v0x555555dac180_3;
|
|
v0x555555dac180_4 .array/port v0x555555dac180, 4;
|
|
v0x555555dac180_5 .array/port v0x555555dac180, 5;
|
|
v0x555555dac180_6 .array/port v0x555555dac180, 6;
|
|
v0x555555dac180_7 .array/port v0x555555dac180, 7;
|
|
E_0x555555ba4230/12 .event anyedge, v0x555555dac180_4, v0x555555dac180_5, v0x555555dac180_6, v0x555555dac180_7;
|
|
v0x555555db1340_0 .array/port v0x555555db1340, 0;
|
|
v0x555555db1340_1 .array/port v0x555555db1340, 1;
|
|
v0x555555db1340_2 .array/port v0x555555db1340, 2;
|
|
v0x555555db1340_3 .array/port v0x555555db1340, 3;
|
|
E_0x555555ba4230/13 .event anyedge, v0x555555db1340_0, v0x555555db1340_1, v0x555555db1340_2, v0x555555db1340_3;
|
|
v0x555555db1340_4 .array/port v0x555555db1340, 4;
|
|
v0x555555db1340_5 .array/port v0x555555db1340, 5;
|
|
E_0x555555ba4230/14 .event anyedge, v0x555555db1340_4, v0x555555db1340_5, v0x555555db2740_0, v0x555555db20a0_0;
|
|
E_0x555555ba4230/15 .event anyedge, v0x555555db2800_0, v0x555555db2a60_0, v0x555555db1fc0_0, v0x555555db2180_0;
|
|
E_0x555555ba4230/16 .event anyedge, v0x555555db1ca0_0, v0x555555db1a00_0, v0x555555db1bc0_0, v0x555555db0750_0;
|
|
v0x555555dabf70_0 .array/port v0x555555dabf70, 0;
|
|
v0x555555dabf70_1 .array/port v0x555555dabf70, 1;
|
|
v0x555555dabf70_2 .array/port v0x555555dabf70, 2;
|
|
E_0x555555ba4230/17 .event anyedge, v0x555555daac20_0, v0x555555dabf70_0, v0x555555dabf70_1, v0x555555dabf70_2;
|
|
v0x555555dabf70_3 .array/port v0x555555dabf70, 3;
|
|
v0x555555dabf70_4 .array/port v0x555555dabf70, 4;
|
|
v0x555555dabf70_5 .array/port v0x555555dabf70, 5;
|
|
v0x555555dabf70_6 .array/port v0x555555dabf70, 6;
|
|
E_0x555555ba4230/18 .event anyedge, v0x555555dabf70_3, v0x555555dabf70_4, v0x555555dabf70_5, v0x555555dabf70_6;
|
|
v0x555555dabf70_7 .array/port v0x555555dabf70, 7;
|
|
v0x555555daae80_0 .array/port v0x555555daae80, 0;
|
|
E_0x555555ba4230/19 .event anyedge, v0x555555dabf70_7, v0x555555db15a0_0, v0x555555dab250_0, v0x555555daae80_0;
|
|
v0x555555daae80_1 .array/port v0x555555daae80, 1;
|
|
v0x555555daae80_2 .array/port v0x555555daae80, 2;
|
|
v0x555555daae80_3 .array/port v0x555555daae80, 3;
|
|
v0x555555daae80_4 .array/port v0x555555daae80, 4;
|
|
E_0x555555ba4230/20 .event anyedge, v0x555555daae80_1, v0x555555daae80_2, v0x555555daae80_3, v0x555555daae80_4;
|
|
v0x555555daae80_5 .array/port v0x555555daae80, 5;
|
|
v0x555555daae80_6 .array/port v0x555555daae80, 6;
|
|
v0x555555daae80_7 .array/port v0x555555daae80, 7;
|
|
E_0x555555ba4230/21 .event anyedge, v0x555555daae80_5, v0x555555daae80_6, v0x555555daae80_7, v0x555555db1d60_0;
|
|
v0x555555dac470_0 .array/port v0x555555dac470, 0;
|
|
v0x555555dac470_1 .array/port v0x555555dac470, 1;
|
|
v0x555555dac470_2 .array/port v0x555555dac470, 2;
|
|
E_0x555555ba4230/22 .event anyedge, v0x555555db1f00_0, v0x555555dac470_0, v0x555555dac470_1, v0x555555dac470_2;
|
|
v0x555555dac470_3 .array/port v0x555555dac470, 3;
|
|
v0x555555dac470_4 .array/port v0x555555dac470, 4;
|
|
v0x555555dac470_5 .array/port v0x555555dac470, 5;
|
|
v0x555555dac470_6 .array/port v0x555555dac470, 6;
|
|
E_0x555555ba4230/23 .event anyedge, v0x555555dac470_3, v0x555555dac470_4, v0x555555dac470_5, v0x555555dac470_6;
|
|
v0x555555dac470_7 .array/port v0x555555dac470, 7;
|
|
E_0x555555ba4230/24 .event anyedge, v0x555555dac470_7, v0x555555db0450_0, v0x555555db28e0_0, v0x555555dae290_0;
|
|
E_0x555555ba4230/25 .event anyedge, v0x555555db1e40_0, v0x555555dae010_0;
|
|
E_0x555555ba4230 .event/or E_0x555555ba4230/0, E_0x555555ba4230/1, E_0x555555ba4230/2, E_0x555555ba4230/3, E_0x555555ba4230/4, E_0x555555ba4230/5, E_0x555555ba4230/6, E_0x555555ba4230/7, E_0x555555ba4230/8, E_0x555555ba4230/9, E_0x555555ba4230/10, E_0x555555ba4230/11, E_0x555555ba4230/12, E_0x555555ba4230/13, E_0x555555ba4230/14, E_0x555555ba4230/15, E_0x555555ba4230/16, E_0x555555ba4230/17, E_0x555555ba4230/18, E_0x555555ba4230/19, E_0x555555ba4230/20, E_0x555555ba4230/21, E_0x555555ba4230/22, E_0x555555ba4230/23, E_0x555555ba4230/24, E_0x555555ba4230/25;
|
|
L_0x555555db5f50 .part v0x555555db4660_0, 0, 1;
|
|
v0x555555dab4d0_0 .array/port v0x555555dab4d0, 0;
|
|
v0x555555dab4d0_1 .array/port v0x555555dab4d0, 1;
|
|
v0x555555dab4d0_2 .array/port v0x555555dab4d0, 2;
|
|
v0x555555dab4d0_3 .array/port v0x555555dab4d0, 3;
|
|
L_0x555555db60e0 .concat [ 26 26 26 26], v0x555555dab4d0_0, v0x555555dab4d0_1, v0x555555dab4d0_2, v0x555555dab4d0_3;
|
|
v0x555555dafe70_0 .array/port v0x555555dafe70, 0;
|
|
L_0x555555db62a0 .part v0x555555dafe70_0, 0, 1;
|
|
L_0x555555db63a0 .concat [ 5 27 0 0], v0x555555db2b20_0, L_0x7eff80b5c018;
|
|
L_0x555555dc6540 .cmp/eq 32, L_0x555555db63a0, L_0x7eff80b5c060;
|
|
L_0x555555dc6750 .part v0x555555dafe70_0, 1, 16;
|
|
L_0x555555dc6880 .array/port v0x555555db0210, L_0x555555dc6920;
|
|
L_0x555555dc6920 .concat [ 1 2 0 0], v0x555555dae810_0, L_0x7eff80b5c0a8;
|
|
L_0x555555dc6b30 .part v0x555555db43e0_0, 2, 1;
|
|
L_0x555555dc6c00 .reduce/nor L_0x555555dc6b30;
|
|
L_0x555555dc6d80 .part v0x555555db4180_0, 3, 1;
|
|
L_0x555555dc6e50 .reduce/nor L_0x555555dc6d80;
|
|
L_0x555555dc6f90 .concat [ 5 27 0 0], v0x555555db2b20_0, L_0x7eff80b5c0f0;
|
|
L_0x555555dc7120 .cmp/eq 32, L_0x555555dc6f90, L_0x7eff80b5c138;
|
|
L_0x555555dc72e0 .array/port v0x555555db0510, L_0x555555dc73b0;
|
|
L_0x555555dc73b0 .concat [ 3 2 0 0], v0x555555daecd0_0, L_0x7eff80b5c1c8;
|
|
L_0x555555dc7600 .array/port v0x555555db05d0, L_0x555555dc76d0;
|
|
L_0x555555dc76d0 .concat [ 3 2 0 0], v0x555555daecd0_0, L_0x7eff80b5c210;
|
|
L_0x555555dc7990 .array/port v0x555555dae410, L_0x555555dc7a30;
|
|
L_0x555555dc7a30 .concat [ 3 2 0 0], v0x555555daecd0_0, L_0x7eff80b5c258;
|
|
L_0x555555dc7810 .array/port v0x555555dae5b0, L_0x555555dc7c90;
|
|
L_0x555555dc7c90 .concat [ 3 2 0 0], v0x555555daecd0_0, L_0x7eff80b5c2a0;
|
|
L_0x555555dc7f50 .part v0x555555dad030_0, 0, 1;
|
|
L_0x555555dc8050 .arith/sum 6, v0x555555dad030_0, L_0x7eff80b5c2e8;
|
|
L_0x555555dc8300 .arith/sum 6, v0x555555dad030_0, L_0x7eff80b5c330;
|
|
L_0x555555dc83f0 .functor MUXZ 6, L_0x555555dc8300, L_0x555555dc8050, L_0x555555dc7f50, C4<>;
|
|
S_0x555555d03780 .scope function.vec4.s3, "WRA_mode_register_value" "WRA_mode_register_value" 2 1690, 2 1690 0, S_0x555555cfe490;
|
|
.timescale 0 0;
|
|
v0x555555d2a0b0_0 .var/i "WRA", 31 0;
|
|
; Variable WRA_mode_register_value is vec4 return value of scope S_0x555555d03780
|
|
TD_ddr3_controller.WRA_mode_register_value ;
|
|
%load/vec4 v0x555555d2a0b0_0;
|
|
%addi 1, 0, 32;
|
|
%dup/vec4;
|
|
%pushi/vec4 1, 0, 32;
|
|
%cmp/u;
|
|
%jmp/1 T_0.0, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 2, 0, 32;
|
|
%cmp/u;
|
|
%jmp/1 T_0.1, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 3, 0, 32;
|
|
%cmp/u;
|
|
%jmp/1 T_0.2, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 4, 0, 32;
|
|
%cmp/u;
|
|
%jmp/1 T_0.3, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 5, 0, 32;
|
|
%cmp/u;
|
|
%jmp/1 T_0.4, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 6, 0, 32;
|
|
%cmp/u;
|
|
%jmp/1 T_0.5, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 7, 0, 32;
|
|
%cmp/u;
|
|
%jmp/1 T_0.6, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 8, 0, 32;
|
|
%cmp/u;
|
|
%jmp/1 T_0.7, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 9, 0, 32;
|
|
%cmp/u;
|
|
%jmp/1 T_0.8, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 10, 0, 32;
|
|
%cmp/u;
|
|
%jmp/1 T_0.9, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 11, 0, 32;
|
|
%cmp/u;
|
|
%jmp/1 T_0.10, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 12, 0, 32;
|
|
%cmp/u;
|
|
%jmp/1 T_0.11, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 13, 0, 32;
|
|
%cmp/u;
|
|
%jmp/1 T_0.12, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 14, 0, 32;
|
|
%cmp/u;
|
|
%jmp/1 T_0.13, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 15, 0, 32;
|
|
%cmp/u;
|
|
%jmp/1 T_0.14, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 16, 0, 32;
|
|
%cmp/u;
|
|
%jmp/1 T_0.15, 6;
|
|
%pushi/vec4 0, 0, 3;
|
|
%ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval)
|
|
%jmp T_0.17;
|
|
T_0.0 ;
|
|
%pushi/vec4 1, 0, 3;
|
|
%ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval)
|
|
%jmp T_0.17;
|
|
T_0.1 ;
|
|
%pushi/vec4 1, 0, 3;
|
|
%ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval)
|
|
%jmp T_0.17;
|
|
T_0.2 ;
|
|
%pushi/vec4 1, 0, 3;
|
|
%ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval)
|
|
%jmp T_0.17;
|
|
T_0.3 ;
|
|
%pushi/vec4 1, 0, 3;
|
|
%ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval)
|
|
%jmp T_0.17;
|
|
T_0.4 ;
|
|
%pushi/vec4 1, 0, 3;
|
|
%ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval)
|
|
%jmp T_0.17;
|
|
T_0.5 ;
|
|
%pushi/vec4 2, 0, 3;
|
|
%ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval)
|
|
%jmp T_0.17;
|
|
T_0.6 ;
|
|
%pushi/vec4 3, 0, 3;
|
|
%ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval)
|
|
%jmp T_0.17;
|
|
T_0.7 ;
|
|
%pushi/vec4 4, 0, 3;
|
|
%ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval)
|
|
%jmp T_0.17;
|
|
T_0.8 ;
|
|
%pushi/vec4 5, 0, 3;
|
|
%ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval)
|
|
%jmp T_0.17;
|
|
T_0.9 ;
|
|
%pushi/vec4 5, 0, 3;
|
|
%ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval)
|
|
%jmp T_0.17;
|
|
T_0.10 ;
|
|
%pushi/vec4 6, 0, 3;
|
|
%ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval)
|
|
%jmp T_0.17;
|
|
T_0.11 ;
|
|
%pushi/vec4 6, 0, 3;
|
|
%ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval)
|
|
%jmp T_0.17;
|
|
T_0.12 ;
|
|
%pushi/vec4 7, 0, 3;
|
|
%ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval)
|
|
%jmp T_0.17;
|
|
T_0.13 ;
|
|
%pushi/vec4 7, 0, 3;
|
|
%ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval)
|
|
%jmp T_0.17;
|
|
T_0.14 ;
|
|
%pushi/vec4 0, 0, 3;
|
|
%ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval)
|
|
%jmp T_0.17;
|
|
T_0.15 ;
|
|
%pushi/vec4 0, 0, 3;
|
|
%ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval)
|
|
%jmp T_0.17;
|
|
T_0.17 ;
|
|
%pop/vec4 1;
|
|
%end;
|
|
S_0x555555da6970 .scope function.vec4.s4, "find_delay" "find_delay" 2 1767, 2 1767 0, S_0x555555cfe490;
|
|
.timescale 0 0;
|
|
v0x555555d472f0_0 .var/i "delay_nCK", 31 0;
|
|
v0x555555d474d0_0 .var "end_slot", 1 0;
|
|
; Variable find_delay is vec4 return value of scope S_0x555555da6970
|
|
v0x555555d64a10_0 .var/i "k", 31 0;
|
|
v0x555555d64ab0_0 .var "start_slot", 1 0;
|
|
TD_ddr3_controller.find_delay ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555d64a10_0, 0, 32;
|
|
T_1.18 ;
|
|
%pushi/vec4 4, 0, 32;
|
|
%load/vec4 v0x555555d64ab0_0;
|
|
%pad/u 32;
|
|
%sub;
|
|
%load/vec4 v0x555555d474d0_0;
|
|
%pad/u 32;
|
|
%add;
|
|
%load/vec4 v0x555555d64a10_0;
|
|
%muli 4, 0, 32;
|
|
%add;
|
|
%load/vec4 v0x555555d472f0_0;
|
|
%cmp/u;
|
|
%jmp/0xz T_1.19, 5;
|
|
%load/vec4 v0x555555d64a10_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555d64a10_0, 0, 32;
|
|
%jmp T_1.18;
|
|
T_1.19 ;
|
|
%load/vec4 v0x555555d64a10_0;
|
|
%parti/s 4, 0, 2;
|
|
%ret/vec4 0, 0, 4; Assign to find_delay (store_vec4_to_lval)
|
|
%end;
|
|
S_0x555555da6ce0 .scope generate, "genblk1" "genblk1" 2 1233, 2 1233 0, S_0x555555cfe490;
|
|
.timescale 0 0;
|
|
S_0x555555da6ec0 .scope function.vec4.s2, "get_slot" "get_slot" 2 1708, 2 1708 0, S_0x555555cfe490;
|
|
.timescale 0 0;
|
|
v0x555555da70a0_0 .var "anticipate_activate_slot", 1 0;
|
|
v0x555555da7180_0 .var "anticipate_precharge_slot", 1 0;
|
|
v0x555555da7260_0 .var "cmd", 3 0;
|
|
v0x555555da7320_0 .var/i "delay", 31 0;
|
|
; Variable get_slot is vec4 return value of scope S_0x555555da6ec0
|
|
v0x555555da7530_0 .var "read_slot", 1 0;
|
|
v0x555555da7610_0 .var "slot_number", 1 0;
|
|
v0x555555da76f0_0 .var "write_slot", 1 0;
|
|
TD_ddr3_controller.get_slot ;
|
|
%pushi/vec4 6, 0, 32;
|
|
%store/vec4 v0x555555da7320_0, 0, 32;
|
|
%pushi/vec4 0, 0, 2;
|
|
%store/vec4 v0x555555da7610_0, 0, 2;
|
|
T_2.20 ;
|
|
%load/vec4 v0x555555da7320_0;
|
|
%cmpi/ne 0, 0, 32;
|
|
%jmp/0xz T_2.21, 4;
|
|
%load/vec4 v0x555555da7610_0;
|
|
%subi 1, 0, 2;
|
|
%store/vec4 v0x555555da7610_0, 0, 2;
|
|
%load/vec4 v0x555555da7320_0;
|
|
%subi 1, 0, 32;
|
|
%store/vec4 v0x555555da7320_0, 0, 32;
|
|
%jmp T_2.20;
|
|
T_2.21 ;
|
|
%load/vec4 v0x555555da7610_0;
|
|
%store/vec4 v0x555555da7530_0, 0, 2;
|
|
%pushi/vec4 5, 0, 32;
|
|
%store/vec4 v0x555555da7320_0, 0, 32;
|
|
%pushi/vec4 0, 0, 2;
|
|
%store/vec4 v0x555555da7610_0, 0, 2;
|
|
T_2.22 ;
|
|
%load/vec4 v0x555555da7320_0;
|
|
%cmpi/ne 0, 0, 32;
|
|
%jmp/0xz T_2.23, 4;
|
|
%load/vec4 v0x555555da7610_0;
|
|
%subi 1, 0, 2;
|
|
%store/vec4 v0x555555da7610_0, 0, 2;
|
|
%load/vec4 v0x555555da7320_0;
|
|
%subi 1, 0, 32;
|
|
%store/vec4 v0x555555da7320_0, 0, 32;
|
|
%jmp T_2.22;
|
|
T_2.23 ;
|
|
%load/vec4 v0x555555da7610_0;
|
|
%store/vec4 v0x555555da76f0_0, 0, 2;
|
|
%load/vec4 v0x555555da7530_0;
|
|
%store/vec4 v0x555555da7610_0, 0, 2;
|
|
%pushi/vec4 13, 0, 32;
|
|
%store/vec4 v0x555555da8bd0_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.ns_to_nCK, S_0x555555da8960;
|
|
%store/vec4 v0x555555da7320_0, 0, 32;
|
|
%load/vec4 v0x555555da7610_0;
|
|
%store/vec4 v0x555555da7610_0, 0, 2;
|
|
T_2.24 ;
|
|
%load/vec4 v0x555555da7320_0;
|
|
%cmpi/ne 0, 0, 32;
|
|
%jmp/0xz T_2.25, 4;
|
|
%load/vec4 v0x555555da7610_0;
|
|
%subi 1, 0, 2;
|
|
%store/vec4 v0x555555da7610_0, 0, 2;
|
|
%load/vec4 v0x555555da7320_0;
|
|
%subi 1, 0, 32;
|
|
%store/vec4 v0x555555da7320_0, 0, 32;
|
|
%jmp T_2.24;
|
|
T_2.25 ;
|
|
%load/vec4 v0x555555da7610_0;
|
|
%store/vec4 v0x555555da70a0_0, 0, 2;
|
|
T_2.26 ;
|
|
%load/vec4 v0x555555da70a0_0;
|
|
%load/vec4 v0x555555da76f0_0;
|
|
%cmp/e;
|
|
%jmp/1 T_2.28, 4;
|
|
%flag_mov 8, 4;
|
|
%load/vec4 v0x555555da70a0_0;
|
|
%load/vec4 v0x555555da7530_0;
|
|
%cmp/e;
|
|
%flag_or 4, 8;
|
|
T_2.28;
|
|
%jmp/0xz T_2.27, 4;
|
|
%load/vec4 v0x555555da70a0_0;
|
|
%subi 1, 0, 2;
|
|
%store/vec4 v0x555555da70a0_0, 0, 2;
|
|
%jmp T_2.26;
|
|
T_2.27 ;
|
|
%pushi/vec4 0, 0, 2;
|
|
%store/vec4 v0x555555da7180_0, 0, 2;
|
|
T_2.29 ;
|
|
%load/vec4 v0x555555da7180_0;
|
|
%load/vec4 v0x555555da76f0_0;
|
|
%cmp/e;
|
|
%jmp/1 T_2.32, 4;
|
|
%flag_mov 8, 4;
|
|
%load/vec4 v0x555555da7180_0;
|
|
%load/vec4 v0x555555da7530_0;
|
|
%cmp/e;
|
|
%flag_or 4, 8;
|
|
T_2.32;
|
|
%jmp/1 T_2.31, 4;
|
|
%flag_mov 8, 4;
|
|
%load/vec4 v0x555555da7180_0;
|
|
%load/vec4 v0x555555da70a0_0;
|
|
%cmp/e;
|
|
%flag_or 4, 8;
|
|
T_2.31;
|
|
%jmp/0xz T_2.30, 4;
|
|
%load/vec4 v0x555555da7180_0;
|
|
%subi 1, 0, 2;
|
|
%store/vec4 v0x555555da7180_0, 0, 2;
|
|
%jmp T_2.29;
|
|
T_2.30 ;
|
|
%load/vec4 v0x555555da7260_0;
|
|
%dup/vec4;
|
|
%pushi/vec4 5, 0, 4;
|
|
%cmp/u;
|
|
%jmp/1 T_2.33, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 4, 0, 4;
|
|
%cmp/u;
|
|
%jmp/1 T_2.34, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 3, 0, 4;
|
|
%cmp/u;
|
|
%jmp/1 T_2.35, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 2, 0, 4;
|
|
%cmp/u;
|
|
%jmp/1 T_2.36, 6;
|
|
%jmp T_2.38;
|
|
T_2.33 ;
|
|
%load/vec4 v0x555555da7530_0;
|
|
%ret/vec4 0, 0, 2; Assign to get_slot (store_vec4_to_lval)
|
|
%jmp T_2.38;
|
|
T_2.34 ;
|
|
%load/vec4 v0x555555da76f0_0;
|
|
%ret/vec4 0, 0, 2; Assign to get_slot (store_vec4_to_lval)
|
|
%jmp T_2.38;
|
|
T_2.35 ;
|
|
%load/vec4 v0x555555da70a0_0;
|
|
%ret/vec4 0, 0, 2; Assign to get_slot (store_vec4_to_lval)
|
|
%jmp T_2.38;
|
|
T_2.36 ;
|
|
%load/vec4 v0x555555da7180_0;
|
|
%ret/vec4 0, 0, 2; Assign to get_slot (store_vec4_to_lval)
|
|
%jmp T_2.38;
|
|
T_2.38 ;
|
|
%pop/vec4 1;
|
|
%end;
|
|
S_0x555555da77d0 .scope function.vec4.u32, "max" "max" 2 1683, 2 1683 0, S_0x555555cfe490;
|
|
.timescale 0 0;
|
|
v0x555555da7a00_0 .var/i "a", 31 0;
|
|
v0x555555da7b00_0 .var/i "b", 31 0;
|
|
; Variable max is vec4 return value of scope S_0x555555da77d0
|
|
TD_ddr3_controller.max ;
|
|
%load/vec4 v0x555555da7b00_0;
|
|
%load/vec4 v0x555555da7a00_0;
|
|
%cmp/s;
|
|
%flag_or 5, 4;
|
|
%jmp/0xz T_3.39, 5;
|
|
%load/vec4 v0x555555da7a00_0;
|
|
%ret/vec4 0, 0, 32; Assign to max (store_vec4_to_lval)
|
|
%jmp T_3.40;
|
|
T_3.39 ;
|
|
%load/vec4 v0x555555da7b00_0;
|
|
%ret/vec4 0, 0, 32; Assign to max (store_vec4_to_lval)
|
|
T_3.40 ;
|
|
%end;
|
|
S_0x555555da7ca0 .scope function.vec4.s19, "nCK_to_cycles" "nCK_to_cycles" 2 1655, 2 1655 0, S_0x555555cfe490;
|
|
.timescale 0 0;
|
|
v0x555555da7e80_0 .var/i "nCK", 31 0;
|
|
; Variable nCK_to_cycles is vec4 return value of scope S_0x555555da7ca0
|
|
v0x555555da8060_0 .var/i "result", 31 0;
|
|
TD_ddr3_controller.nCK_to_cycles ;
|
|
%load/vec4 v0x555555da7e80_0;
|
|
%cvt/rv/s;
|
|
%pushi/real 1073741824, 4066; load=1.00000
|
|
%mul/wr;
|
|
%pushi/vec4 4, 0, 32;
|
|
%cvt/rv/s;
|
|
%div/wr;
|
|
%vpi_func/r 2 1658 "$ceil", W<0,r> {0 1 0};
|
|
%vpi_func 2 1658 "$rtoi" 32, W<0,r> {0 1 0};
|
|
%store/vec4 v0x555555da8060_0, 0, 32;
|
|
%load/vec4 v0x555555da8060_0;
|
|
%parti/s 19, 0, 2;
|
|
%ret/vec4 0, 0, 19; Assign to nCK_to_cycles (store_vec4_to_lval)
|
|
%end;
|
|
S_0x555555da8120 .scope function.vec4.u32, "nCK_to_ns" "nCK_to_ns" 2 1674, 2 1674 0, S_0x555555cfe490;
|
|
.timescale 0 0;
|
|
v0x555555da8300_0 .var/i "nCK", 31 0;
|
|
; Variable nCK_to_ns is vec4 return value of scope S_0x555555da8120
|
|
TD_ddr3_controller.nCK_to_ns ;
|
|
%load/vec4 v0x555555da8300_0;
|
|
%cvt/rv/s;
|
|
%pushi/real 1073741824, 4066; load=1.00000
|
|
%mul/wr;
|
|
%pushi/real 1342177280, 4067; load=2.50000
|
|
%mul/wr;
|
|
%vpi_func/r 2 1675 "$ceil", W<0,r> {0 1 0};
|
|
%vpi_func 2 1675 "$rtoi" 32, W<0,r> {0 1 0};
|
|
%ret/vec4 0, 0, 32; Assign to nCK_to_ns (store_vec4_to_lval)
|
|
%end;
|
|
S_0x555555da84e0 .scope function.vec4.s19, "ns_to_cycles" "ns_to_cycles" 2 1646, 2 1646 0, S_0x555555cfe490;
|
|
.timescale 0 0;
|
|
v0x555555da86c0_0 .var/i "ns", 31 0;
|
|
; Variable ns_to_cycles is vec4 return value of scope S_0x555555da84e0
|
|
v0x555555da88a0_0 .var/i "result", 31 0;
|
|
TD_ddr3_controller.ns_to_cycles ;
|
|
%load/vec4 v0x555555da86c0_0;
|
|
%cvt/rv/s;
|
|
%pushi/real 1073741824, 4066; load=1.00000
|
|
%mul/wr;
|
|
%pushi/real 1342177280, 4069; load=10.0000
|
|
%div/wr;
|
|
%vpi_func/r 2 1649 "$ceil", W<0,r> {0 1 0};
|
|
%vpi_func 2 1649 "$rtoi" 32, W<0,r> {0 1 0};
|
|
%store/vec4 v0x555555da88a0_0, 0, 32;
|
|
%load/vec4 v0x555555da88a0_0;
|
|
%parti/s 19, 0, 2;
|
|
%ret/vec4 0, 0, 19; Assign to ns_to_cycles (store_vec4_to_lval)
|
|
%end;
|
|
S_0x555555da8960 .scope function.vec4.u32, "ns_to_nCK" "ns_to_nCK" 2 1665, 2 1665 0, S_0x555555cfe490;
|
|
.timescale 0 0;
|
|
v0x555555da8bd0_0 .var/i "ns", 31 0;
|
|
; Variable ns_to_nCK is vec4 return value of scope S_0x555555da8960
|
|
TD_ddr3_controller.ns_to_nCK ;
|
|
%load/vec4 v0x555555da8bd0_0;
|
|
%cvt/rv/s;
|
|
%pushi/real 1073741824, 4066; load=1.00000
|
|
%mul/wr;
|
|
%pushi/real 1342177280, 4067; load=2.50000
|
|
%div/wr;
|
|
%vpi_func/r 2 1666 "$ceil", W<0,r> {0 1 0};
|
|
%vpi_func 2 1666 "$rtoi" 32, W<0,r> {0 1 0};
|
|
%ret/vec4 0, 0, 32; Assign to ns_to_nCK (store_vec4_to_lval)
|
|
%end;
|
|
S_0x555555da8db0 .scope function.vec4.s28, "read_rom_instruction" "read_rom_instruction" 2 508, 2 508 0, S_0x555555cfe490;
|
|
.timescale 0 0;
|
|
v0x555555da8f40_0 .var "instruction_address", 4 0;
|
|
; Variable read_rom_instruction is vec4 return value of scope S_0x555555da8db0
|
|
TD_ddr3_controller.read_rom_instruction ;
|
|
%load/vec4 v0x555555da8f40_0;
|
|
%dup/vec4;
|
|
%pushi/vec4 0, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_8.41, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 1, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_8.42, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 2, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_8.43, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 3, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_8.44, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 4, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_8.45, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 5, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_8.46, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 6, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_8.47, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 7, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_8.48, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 8, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_8.49, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 9, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_8.50, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 10, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_8.51, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 11, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_8.52, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 12, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_8.53, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 13, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_8.54, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 14, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_8.55, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 15, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_8.56, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 16, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_8.57, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 17, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_8.58, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 18, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_8.59, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 19, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_8.60, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 20, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_8.61, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 21, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_8.62, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 22, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_8.63, 6;
|
|
%pushi/vec4 28835840, 0, 28;
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.41 ;
|
|
%pushi/vec4 8, 0, 5;
|
|
%concati/vec4 7, 0, 4;
|
|
%pushi/vec4 200, 0, 32;
|
|
%store/vec4 v0x555555da86c0_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.ns_to_cycles, S_0x555555da84e0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.42 ;
|
|
%pushi/vec4 9, 0, 5;
|
|
%concati/vec4 7, 0, 4;
|
|
%pushi/vec4 500, 0, 32;
|
|
%store/vec4 v0x555555da86c0_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.ns_to_cycles, S_0x555555da84e0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.43 ;
|
|
%pushi/vec4 11, 0, 5;
|
|
%concati/vec4 7, 0, 4;
|
|
%pushi/vec4 360, 0, 32;
|
|
%store/vec4 v0x555555da86c0_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.ns_to_cycles, S_0x555555da84e0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.44 ;
|
|
%pushi/vec4 25296960, 0, 28;
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.45 ;
|
|
%pushi/vec4 25362432, 0, 28;
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.46 ;
|
|
%pushi/vec4 25233476, 0, 28;
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.47 ;
|
|
%pushi/vec4 58722080, 0, 28;
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.48 ;
|
|
%pushi/vec4 95944707, 0, 28;
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.49 ;
|
|
%pushi/vec4 128974976, 0, 28;
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.50 ;
|
|
%pushi/vec4 15, 0, 5;
|
|
%concati/vec4 2, 0, 4;
|
|
%pushi/vec4 14, 0, 32;
|
|
%store/vec4 v0x555555da86c0_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.ns_to_cycles, S_0x555555da84e0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.51 ;
|
|
%pushi/vec4 25362436, 0, 28;
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.52 ;
|
|
%pushi/vec4 95944707, 0, 28;
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.53 ;
|
|
%pushi/vec4 95944706, 0, 28;
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.54 ;
|
|
%pushi/vec4 25362432, 0, 28;
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.55 ;
|
|
%pushi/vec4 25233604, 0, 28;
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.56 ;
|
|
%pushi/vec4 95944714, 0, 28;
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.57 ;
|
|
%pushi/vec4 95944706, 0, 28;
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.58 ;
|
|
%pushi/vec4 25233476, 0, 28;
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.59 ;
|
|
%pushi/vec4 95944707, 0, 28;
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.60 ;
|
|
%pushi/vec4 15, 0, 5;
|
|
%concati/vec4 2, 0, 4;
|
|
%pushi/vec4 14, 0, 32;
|
|
%store/vec4 v0x555555da86c0_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.ns_to_cycles, S_0x555555da84e0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.61 ;
|
|
%pushi/vec4 11, 0, 5;
|
|
%concati/vec4 1, 0, 4;
|
|
%pushi/vec4 350, 0, 32;
|
|
%store/vec4 v0x555555da86c0_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.ns_to_cycles, S_0x555555da84e0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.62 ;
|
|
%pushi/vec4 27, 0, 5;
|
|
%concati/vec4 7, 0, 4;
|
|
%pushi/vec4 7800, 0, 32;
|
|
%store/vec4 v0x555555da86c0_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.ns_to_cycles, S_0x555555da84e0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.63 ;
|
|
%pushi/vec4 95944709, 0, 28;
|
|
%ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval)
|
|
%jmp T_8.65;
|
|
T_8.65 ;
|
|
%pop/vec4 1;
|
|
%end;
|
|
S_0x555555d02bb0 .scope module, "mini_fifo" "mini_fifo" 2 3346;
|
|
.timescale 0 0;
|
|
.port_info 0 /INPUT 1 "i_clk";
|
|
.port_info 1 /INPUT 1 "i_rst_n";
|
|
.port_info 2 /INPUT 1 "read_fifo";
|
|
.port_info 3 /INPUT 1 "write_fifo";
|
|
.port_info 4 /OUTPUT 1 "empty";
|
|
.port_info 5 /OUTPUT 1 "full";
|
|
.port_info 6 /INPUT 8 "write_data";
|
|
.port_info 7 /OUTPUT 8 "read_data";
|
|
.port_info 8 /OUTPUT 8 "read_data_next";
|
|
P_0x555555b810b0 .param/l "DATA_WIDTH" 0 2 3348, +C4<00000000000000000000000000001000>;
|
|
P_0x555555b810f0 .param/l "FIFO_WIDTH" 0 2 3347, +C4<00000000000000000000000000000001>;
|
|
L_0x555555dc80f0 .functor BUFZ 8, L_0x555555dc8660, C4<00000000>, C4<00000000>, C4<00000000>;
|
|
L_0x555555dc8c40 .functor BUFZ 8, L_0x555555dc8890, C4<00000000>, C4<00000000>, C4<00000000>;
|
|
v0x555555db4d80_0 .net *"_ivl_0", 7 0, L_0x555555dc8660; 1 drivers
|
|
v0x555555db4e80_0 .net *"_ivl_11", 0 0, L_0x555555dc8960; 1 drivers
|
|
v0x555555db4f40_0 .net *"_ivl_12", 2 0, L_0x555555dc8ab0; 1 drivers
|
|
L_0x7eff80b5c3c0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
|
|
v0x555555db5030_0 .net *"_ivl_15", 1 0, L_0x7eff80b5c3c0; 1 drivers
|
|
v0x555555db5110_0 .net *"_ivl_2", 2 0, L_0x555555dc8700; 1 drivers
|
|
L_0x7eff80b5c378 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
|
|
v0x555555db5240_0 .net *"_ivl_5", 1 0, L_0x7eff80b5c378; 1 drivers
|
|
v0x555555db5320_0 .net *"_ivl_8", 7 0, L_0x555555dc8890; 1 drivers
|
|
v0x555555db5400_0 .var "empty", 0 0;
|
|
v0x555555db54c0 .array "fifo_reg", 0 1, 7 0;
|
|
v0x555555db5610_0 .var "full", 0 0;
|
|
o0x7eff80ba9008 .functor BUFZ 1, C4<z>; HiZ drive
|
|
v0x555555db56d0_0 .net "i_clk", 0 0, o0x7eff80ba9008; 0 drivers
|
|
o0x7eff80ba9038 .functor BUFZ 1, C4<z>; HiZ drive
|
|
v0x555555db5790_0 .net "i_rst_n", 0 0, o0x7eff80ba9038; 0 drivers
|
|
v0x555555db5850_0 .net "read_data", 7 0, L_0x555555dc80f0; 1 drivers
|
|
v0x555555db5930_0 .net "read_data_next", 7 0, L_0x555555dc8c40; 1 drivers
|
|
o0x7eff80ba90c8 .functor BUFZ 1, C4<z>; HiZ drive
|
|
v0x555555db5a10_0 .net "read_fifo", 0 0, o0x7eff80ba90c8; 0 drivers
|
|
v0x555555db5ad0_0 .var "read_pointer", 0 0;
|
|
o0x7eff80ba9128 .functor BUFZ 8, C4<zzzzzzzz>; HiZ drive
|
|
v0x555555db5bb0_0 .net "write_data", 7 0, o0x7eff80ba9128; 0 drivers
|
|
o0x7eff80ba9158 .functor BUFZ 1, C4<z>; HiZ drive
|
|
v0x555555db5c90_0 .net "write_fifo", 0 0, o0x7eff80ba9158; 0 drivers
|
|
v0x555555db5d50_0 .var "write_pointer", 0 0;
|
|
E_0x555555d8c690/0 .event negedge, v0x555555db5790_0;
|
|
E_0x555555d8c690/1 .event posedge, v0x555555db56d0_0;
|
|
E_0x555555d8c690 .event/or E_0x555555d8c690/0, E_0x555555d8c690/1;
|
|
L_0x555555dc8660 .array/port v0x555555db54c0, L_0x555555dc8700;
|
|
L_0x555555dc8700 .concat [ 1 2 0 0], v0x555555db5ad0_0, L_0x7eff80b5c378;
|
|
L_0x555555dc8890 .array/port v0x555555db54c0, L_0x555555dc8ab0;
|
|
L_0x555555dc8960 .reduce/nor v0x555555db5ad0_0;
|
|
L_0x555555dc8ab0 .concat [ 1 2 0 0], L_0x555555dc8960, L_0x7eff80b5c3c0;
|
|
.scope S_0x555555cfe490;
|
|
T_9 ;
|
|
%pushi/vec4 0, 0, 5;
|
|
%store/vec4 v0x555555daea70_0, 0, 5;
|
|
%pushi/vec4 70778885, 0, 28;
|
|
%store/vec4 v0x555555dae990_0, 0, 28;
|
|
%pushi/vec4 5, 0, 16;
|
|
%store/vec4 v0x555555dac970_0, 0, 16;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555daca50_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db11c0_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db0690_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db1ca0_0, 0, 1;
|
|
%pushi/vec4 0, 0, 16;
|
|
%store/vec4 v0x555555db14c0_0, 0, 16;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db1f00_0, 0, 1;
|
|
%pushi/vec4 0, 0, 512;
|
|
%store/vec4 v0x555555db1760_0, 0, 512;
|
|
%pushi/vec4 0, 0, 64;
|
|
%store/vec4 v0x555555db1840_0, 0, 64;
|
|
%pushi/vec4 0, 0, 10;
|
|
%store/vec4 v0x555555db1680_0, 0, 10;
|
|
%pushi/vec4 0, 0, 3;
|
|
%store/vec4 v0x555555db15a0_0, 0, 3;
|
|
%pushi/vec4 0, 0, 16;
|
|
%store/vec4 v0x555555db1d60_0, 0, 16;
|
|
%pushi/vec4 0, 0, 10;
|
|
%store/vec4 v0x555555db1ae0_0, 0, 10;
|
|
%pushi/vec4 0, 0, 3;
|
|
%store/vec4 v0x555555db1a00_0, 0, 3;
|
|
%pushi/vec4 0, 0, 16;
|
|
%store/vec4 v0x555555db1bc0_0, 0, 16;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db2740_0, 0, 1;
|
|
%pushi/vec4 0, 0, 16;
|
|
%store/vec4 v0x555555db1fc0_0, 0, 16;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db2a60_0, 0, 1;
|
|
%pushi/vec4 0, 0, 64;
|
|
%store/vec4 v0x555555db2580_0, 0, 64;
|
|
%pushi/vec4 0, 0, 512;
|
|
%store/vec4 v0x555555db2380_0, 0, 512;
|
|
%pushi/vec4 0, 0, 10;
|
|
%store/vec4 v0x555555db2180_0, 0, 10;
|
|
%pushi/vec4 0, 0, 3;
|
|
%store/vec4 v0x555555db20a0_0, 0, 3;
|
|
%pushi/vec4 0, 0, 16;
|
|
%store/vec4 v0x555555db2800_0, 0, 16;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555dab6d0_0, 0, 1;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x555555db0450_0, 0, 1;
|
|
%pushi/vec4 0, 0, 40;
|
|
%store/vec4 v0x555555dad110_0, 0, 40;
|
|
%pushi/vec4 0, 0, 4;
|
|
%store/vec4 v0x555555dacd90_0, 0, 4;
|
|
%pushi/vec4 0, 0, 6;
|
|
%store/vec4 v0x555555dace70_0, 0, 6;
|
|
%pushi/vec4 0, 0, 6;
|
|
%store/vec4 v0x555555dad030_0, 0, 6;
|
|
%pushi/vec4 0, 0, 6;
|
|
%store/vec4 v0x555555dad1f0_0, 0, 6;
|
|
%pushi/vec4 0, 0, 6;
|
|
%store/vec4 v0x555555dad2d0_0, 0, 6;
|
|
%pushi/vec4 0, 0, 6;
|
|
%store/vec4 v0x555555dacbd0_0, 0, 6;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555dacf50_0, 0, 1;
|
|
%pushi/vec4 0, 0, 4;
|
|
%store/vec4 v0x555555dac390_0, 0, 4;
|
|
%pushi/vec4 0, 0, 5;
|
|
%store/vec4 v0x555555dac890_0, 0, 5;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555dae8d0_0, 0, 1;
|
|
%pushi/vec4 0, 0, 3;
|
|
%store/vec4 v0x555555daecd0_0, 0, 3;
|
|
%pushi/vec4 0, 0, 16;
|
|
%store/vec4 v0x555555daccb0_0, 0, 16;
|
|
%pushi/vec4 0, 0, 4;
|
|
%store/vec4 v0x555555daada0_0, 0, 4;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db4000_0, 0, 1;
|
|
%pushi/vec4 0, 0, 16;
|
|
%store/vec4 v0x555555db3b20_0, 0, 16;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db40c0_0, 0, 1;
|
|
%pushi/vec4 0, 0, 10;
|
|
%store/vec4 v0x555555db3c00_0, 0, 10;
|
|
%pushi/vec4 0, 0, 512;
|
|
%store/vec4 v0x555555db3ce0_0, 0, 512;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db3f40_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db3e80_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db3dc0_0, 0, 1;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x555555db0810_0, 0, 1;
|
|
%pushi/vec4 0, 0, 512;
|
|
%store/vec4 v0x555555db10e0_0, 0, 512;
|
|
%pushi/vec4 0, 0, 128;
|
|
%store/vec4 v0x555555db4740_0, 0, 128;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db3800_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db38c0_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db3980_0, 0, 1;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555db2e60_0, 0, 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555db2f40_0, 0, 32;
|
|
%pushi/vec4 0, 0, 4;
|
|
%store/vec4 v0x555555db3720_0, 0, 4;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x555555db29a0_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db28e0_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db1e40_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db1920_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db2660_0, 0, 1;
|
|
%end;
|
|
.thread T_9;
|
|
.scope S_0x555555cfe490;
|
|
T_10 ;
|
|
%pushi/vec4 0, 0, 8;
|
|
%store/vec4 v0x555555daee90_0, 0, 8;
|
|
%end;
|
|
.thread T_10;
|
|
.scope S_0x555555cfe490;
|
|
T_11 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_11.0 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%cmpi/s 8, 0, 32;
|
|
%jmp/0xz T_11.1, 5;
|
|
%pushi/vec4 0, 0, 1;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4 v0x555555dab330_0, 4, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4 v0x555555dab250_0, 4, 1;
|
|
%pushi/vec4 0, 0, 16;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4a v0x555555dab040, 4, 0;
|
|
%pushi/vec4 0, 0, 16;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4a v0x555555daae80, 4, 0;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_11.0;
|
|
T_11.1 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_11.2 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%pad/u 36;
|
|
%cmpi/u 2, 0, 36;
|
|
%jmp/0xz T_11.3, 5;
|
|
%pushi/vec4 0, 0, 512;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4a v0x555555db2260, 4, 0;
|
|
%pushi/vec4 0, 0, 64;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4a v0x555555db2460, 4, 0;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_11.2;
|
|
T_11.3 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_11.4 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%cmpi/s 8, 0, 32;
|
|
%jmp/0xz T_11.5, 5;
|
|
%pushi/vec4 0, 0, 4;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4a v0x555555dabd60, 4, 0;
|
|
%pushi/vec4 0, 0, 4;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4a v0x555555daba90, 4, 0;
|
|
%pushi/vec4 0, 0, 4;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4a v0x555555dac680, 4, 0;
|
|
%pushi/vec4 0, 0, 4;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4a v0x555555dac180, 4, 0;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_11.4;
|
|
T_11.5 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_11.6 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%pad/s 36;
|
|
%cmpi/s 6, 0, 36;
|
|
%jmp/0xz T_11.7, 5;
|
|
%pushi/vec4 0, 0, 17;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4a v0x555555db1340, 4, 0;
|
|
%pushi/vec4 0, 0, 17;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4a v0x555555db1280, 4, 0;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_11.6;
|
|
T_11.7 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_11.8 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%cmpi/s 4, 0, 32;
|
|
%jmp/0xz T_11.9, 5;
|
|
%pushi/vec4 67108863, 0, 26;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4a v0x555555dab790, 4, 0;
|
|
%pushi/vec4 67108863, 0, 26;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4a v0x555555dab4d0, 4, 0;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_11.8;
|
|
T_11.9 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_11.10 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%cmpi/u 8, 0, 32;
|
|
%jmp/0xz T_11.11, 5;
|
|
%pushi/vec4 0, 0, 5;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4a v0x555555db0510, 4, 0;
|
|
%pushi/vec4 8, 0, 5;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4a v0x555555db05d0, 4, 0;
|
|
%pushi/vec4 0, 0, 5;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4a v0x555555dae410, 4, 0;
|
|
%pushi/vec4 8, 0, 5;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4a v0x555555dae5b0, 4, 0;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_11.10;
|
|
T_11.11 ;
|
|
%end;
|
|
.thread T_11;
|
|
.scope S_0x555555cfe490;
|
|
T_12 ;
|
|
%wait E_0x555555cb9a50;
|
|
%load/vec4 v0x555555dad990_0;
|
|
%nor/r;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_12.0, 8;
|
|
%pushi/vec4 0, 0, 5;
|
|
%assign/vec4 v0x555555daea70_0, 0;
|
|
%pushi/vec4 70778885, 0, 28;
|
|
%assign/vec4 v0x555555dae990_0, 0;
|
|
%pushi/vec4 5, 0, 16;
|
|
%assign/vec4 v0x555555dac970_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555daca50_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db11c0_0, 0;
|
|
%jmp T_12.1;
|
|
T_12.0 ;
|
|
%load/vec4 v0x555555daca50_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_12.2, 8;
|
|
%load/vec4 v0x555555dae990_0;
|
|
%parti/s 16, 0, 2;
|
|
%assign/vec4 v0x555555dac970_0, 0;
|
|
%jmp T_12.3;
|
|
T_12.2 ;
|
|
%load/vec4 v0x555555dae990_0;
|
|
%parti/s 1, 26, 6;
|
|
%flag_set/vec4 9;
|
|
%flag_get/vec4 9;
|
|
%jmp/0 T_12.6, 9;
|
|
%load/vec4 v0x555555db0690_0;
|
|
%nor/r;
|
|
%and;
|
|
T_12.6;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_12.4, 8;
|
|
%load/vec4 v0x555555dac970_0;
|
|
%subi 1, 0, 16;
|
|
%assign/vec4 v0x555555dac970_0, 0;
|
|
T_12.4 ;
|
|
T_12.3 ;
|
|
%load/vec4 v0x555555dac970_0;
|
|
%pad/u 32;
|
|
%cmpi/e 1, 0, 32;
|
|
%jmp/1 T_12.9, 4;
|
|
%flag_mov 8, 4;
|
|
%load/vec4 v0x555555dae990_0;
|
|
%parti/s 1, 26, 6;
|
|
%nor/r;
|
|
%flag_set/vec4 9;
|
|
%flag_or 9, 8;
|
|
%flag_mov 4, 9;
|
|
T_12.9;
|
|
%jmp/0xz T_12.7, 4;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555daca50_0, 0;
|
|
%load/vec4 v0x555555daea70_0;
|
|
%store/vec4 v0x555555da8f40_0, 0, 5;
|
|
%callf/vec4 TD_ddr3_controller.read_rom_instruction, S_0x555555da8db0;
|
|
%assign/vec4 v0x555555dae990_0, 0;
|
|
%load/vec4 v0x555555daea70_0;
|
|
%cmpi/e 22, 0, 5;
|
|
%flag_mov 8, 4;
|
|
%jmp/0 T_12.10, 8;
|
|
%pushi/vec4 19, 0, 5;
|
|
%jmp/1 T_12.11, 8;
|
|
T_12.10 ; End of true expr.
|
|
%load/vec4 v0x555555daea70_0;
|
|
%addi 1, 0, 5;
|
|
%jmp/0 T_12.11, 8;
|
|
; End of false expr.
|
|
%blend;
|
|
T_12.11;
|
|
%assign/vec4 v0x555555daea70_0, 0;
|
|
%jmp T_12.8;
|
|
T_12.7 ;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555daca50_0, 0;
|
|
T_12.8 ;
|
|
%load/vec4 v0x555555dae990_0;
|
|
%parti/s 1, 27, 6;
|
|
%flag_set/vec4 8;
|
|
%jmp/0 T_12.12, 8;
|
|
%pushi/vec4 1, 0, 1;
|
|
%jmp/1 T_12.13, 8;
|
|
T_12.12 ; End of true expr.
|
|
%load/vec4 v0x555555db11c0_0;
|
|
%jmp/0 T_12.13, 8;
|
|
; End of false expr.
|
|
%blend;
|
|
T_12.13;
|
|
%assign/vec4 v0x555555db11c0_0, 0;
|
|
T_12.1 ;
|
|
%jmp T_12;
|
|
.thread T_12;
|
|
.scope S_0x555555cfe490;
|
|
T_13 ;
|
|
%wait E_0x555555cb9a50;
|
|
%load/vec4 v0x555555dad990_0;
|
|
%nor/r;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_13.0, 8;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555db02d0_0, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555db0450_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db1ca0_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db1f00_0, 0;
|
|
%pushi/vec4 0, 0, 10;
|
|
%assign/vec4 v0x555555db1680_0, 0;
|
|
%pushi/vec4 0, 0, 3;
|
|
%assign/vec4 v0x555555db15a0_0, 0;
|
|
%pushi/vec4 0, 0, 16;
|
|
%assign/vec4 v0x555555db1d60_0, 0;
|
|
%pushi/vec4 0, 0, 3;
|
|
%assign/vec4 v0x555555db1a00_0, 0;
|
|
%pushi/vec4 0, 0, 16;
|
|
%assign/vec4 v0x555555db1bc0_0, 0;
|
|
%pushi/vec4 0, 0, 10;
|
|
%assign/vec4 v0x555555db1ae0_0, 0;
|
|
%pushi/vec4 0, 0, 512;
|
|
%assign/vec4 v0x555555db1760_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db2740_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db2a60_0, 0;
|
|
%pushi/vec4 0, 0, 10;
|
|
%assign/vec4 v0x555555db2180_0, 0;
|
|
%pushi/vec4 0, 0, 3;
|
|
%assign/vec4 v0x555555db20a0_0, 0;
|
|
%pushi/vec4 0, 0, 16;
|
|
%assign/vec4 v0x555555db2800_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555dab6d0_0, 0;
|
|
%pushi/vec4 0, 0, 512;
|
|
%assign/vec4 v0x555555db2380_0, 0;
|
|
%pushi/vec4 0, 0, 64;
|
|
%assign/vec4 v0x555555db2580_0, 0;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_13.2 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%cmpi/u 8, 0, 32;
|
|
%jmp/0xz T_13.3, 5;
|
|
%pushi/vec4 0, 0, 64;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555db2ce0, 0, 4;
|
|
%pushi/vec4 0, 0, 8;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555db2da0, 0, 4;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_13.2;
|
|
T_13.3 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_13.4 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%cmpi/s 8, 0, 32;
|
|
%jmp/0xz T_13.5, 5;
|
|
%pushi/vec4 0, 0, 4;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dabd60, 0, 4;
|
|
%pushi/vec4 0, 0, 4;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555daba90, 0, 4;
|
|
%pushi/vec4 0, 0, 4;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dac680, 0, 4;
|
|
%pushi/vec4 0, 0, 4;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dac180, 0, 4;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_13.4;
|
|
T_13.5 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_13.6 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%cmpi/s 8, 0, 32;
|
|
%jmp/0xz T_13.7, 5;
|
|
%pushi/vec4 0, 0, 1;
|
|
%ix/load 5, 0, 0;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%assign/vec4/off/d v0x555555dab330_0, 4, 5;
|
|
%pushi/vec4 0, 0, 16;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dab040, 0, 4;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_13.6;
|
|
T_13.7 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_13.8 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%pad/u 36;
|
|
%cmpi/u 2, 0, 36;
|
|
%jmp/0xz T_13.9, 5;
|
|
%pushi/vec4 0, 0, 512;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555db2260, 0, 4;
|
|
%pushi/vec4 0, 0, 64;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555db2460, 0, 4;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_13.8;
|
|
T_13.9 ;
|
|
%jmp T_13.1;
|
|
T_13.0 ;
|
|
%load/vec4 v0x555555db11c0_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_13.10, 8;
|
|
%load/vec4 v0x555555db0390_0;
|
|
%flag_set/vec4 8;
|
|
%flag_get/vec4 8;
|
|
%jmp/1 T_13.12, 8;
|
|
%load/vec4 v0x555555db2b20_0;
|
|
%pad/u 32;
|
|
%pushi/vec4 14, 0, 32;
|
|
%cmp/ne;
|
|
%flag_get/vec4 4;
|
|
%or;
|
|
T_13.12;
|
|
%assign/vec4 v0x555555db02d0_0, 0;
|
|
%load/vec4 v0x555555db0390_0;
|
|
%assign/vec4 v0x555555db0450_0, 0;
|
|
%load/vec4 v0x555555dab610_0;
|
|
%assign/vec4 v0x555555dab6d0_0, 0;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_13.13 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%cmpi/s 8, 0, 32;
|
|
%jmp/0xz T_13.14, 5;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555dabca0, 4;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dabd60, 0, 4;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555dab9d0, 4;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555daba90, 0, 4;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555dac470, 4;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dac680, 0, 4;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555dabf70, 4;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dac180, 0, 4;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_13.13;
|
|
T_13.14 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_13.15 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%cmpi/s 4, 0, 32;
|
|
%jmp/0xz T_13.16, 5;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555dab4d0, 4;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dab790, 0, 4;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_13.15;
|
|
T_13.16 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_13.17 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%cmpi/s 8, 0, 32;
|
|
%jmp/0xz T_13.18, 5;
|
|
%load/vec4 v0x555555dab250_0;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%part/s 1;
|
|
%ix/load 5, 0, 0;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%assign/vec4/off/d v0x555555dab330_0, 4, 5;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555daae80, 4;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dab040, 0, 4;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_13.17;
|
|
T_13.18 ;
|
|
%load/vec4 v0x555555daea70_0;
|
|
%pad/u 32;
|
|
%cmpi/e 20, 0, 32;
|
|
%jmp/0xz T_13.19, 4;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555dab6d0_0, 0;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_13.21 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%cmpi/s 8, 0, 32;
|
|
%jmp/0xz T_13.22, 5;
|
|
%pushi/vec4 0, 0, 1;
|
|
%ix/load 5, 0, 0;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%assign/vec4/off/d v0x555555dab330_0, 4, 5;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_13.21;
|
|
T_13.22 ;
|
|
T_13.19 ;
|
|
%load/vec4 v0x555555dae990_0;
|
|
%parti/s 1, 27, 6;
|
|
%nor/r;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_13.23, 8;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555db02d0_0, 0;
|
|
T_13.23 ;
|
|
%load/vec4 v0x555555db0450_0;
|
|
%nor/r;
|
|
%flag_set/vec4 9;
|
|
%flag_get/vec4 9;
|
|
%jmp/0 T_13.27, 9;
|
|
%load/vec4 v0x555555db29a0_0;
|
|
%and;
|
|
T_13.27;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_13.25, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db1ca0_0, 0;
|
|
%load/vec4 v0x555555db1ca0_0;
|
|
%assign/vec4 v0x555555db2740_0, 0;
|
|
%load/vec4 v0x555555db14c0_0;
|
|
%assign/vec4 v0x555555db1fc0_0, 0;
|
|
%load/vec4 v0x555555db1f00_0;
|
|
%assign/vec4 v0x555555db2a60_0, 0;
|
|
%load/vec4 v0x555555db1840_0;
|
|
%inv;
|
|
%assign/vec4 v0x555555db2580_0, 0;
|
|
%load/vec4 v0x555555db1680_0;
|
|
%assign/vec4 v0x555555db2180_0, 0;
|
|
%load/vec4 v0x555555db15a0_0;
|
|
%assign/vec4 v0x555555db20a0_0, 0;
|
|
%load/vec4 v0x555555db1d60_0;
|
|
%assign/vec4 v0x555555db2800_0, 0;
|
|
%load/vec4 v0x555555db1760_0;
|
|
%assign/vec4 v0x555555db2380_0, 0;
|
|
T_13.25 ;
|
|
%load/vec4 v0x555555dae010_0;
|
|
%flag_set/vec4 9;
|
|
%flag_get/vec4 9;
|
|
%jmp/0 T_13.30, 9;
|
|
%load/vec4 v0x555555db02d0_0;
|
|
%nor/r;
|
|
%and;
|
|
T_13.30;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_13.28, 8;
|
|
%load/vec4 v0x555555dae290_0;
|
|
%assign/vec4 v0x555555db1ca0_0, 0;
|
|
%load/vec4 v0x555555dad490_0;
|
|
%assign/vec4 v0x555555db14c0_0, 0;
|
|
%load/vec4 v0x555555dae350_0;
|
|
%assign/vec4 v0x555555db1f00_0, 0;
|
|
%load/vec4 v0x555555dae1b0_0;
|
|
%assign/vec4 v0x555555db1840_0, 0;
|
|
%load/vec4 v0x555555dadf30_0;
|
|
%parti/s 7, 0, 2;
|
|
%concati/vec4 0, 0, 3;
|
|
%assign/vec4 v0x555555db1680_0, 0;
|
|
%load/vec4 v0x555555dadf30_0;
|
|
%parti/s 3, 7, 4;
|
|
%assign/vec4 v0x555555db15a0_0, 0;
|
|
%load/vec4 v0x555555dadf30_0;
|
|
%parti/s 16, 10, 5;
|
|
%assign/vec4 v0x555555db1d60_0, 0;
|
|
%load/vec4 v0x555555dadf30_0;
|
|
%addi 5, 0, 26;
|
|
%split/vec4 7;
|
|
%ix/load 4, 3, 0;
|
|
%ix/load 5, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%assign/vec4/off/d v0x555555db1ae0_0, 4, 5;
|
|
%split/vec4 3;
|
|
%assign/vec4 v0x555555db1a00_0, 0;
|
|
%assign/vec4 v0x555555db1bc0_0, 0;
|
|
%load/vec4 v0x555555dae0d0_0;
|
|
%assign/vec4 v0x555555db1760_0, 0;
|
|
%jmp T_13.29;
|
|
T_13.28 ;
|
|
%load/vec4 v0x555555db2b20_0;
|
|
%pad/u 32;
|
|
%cmpi/ne 14, 0, 32;
|
|
%jmp/0xz T_13.31, 4;
|
|
%load/vec4 v0x555555db4000_0;
|
|
%assign/vec4 v0x555555db1ca0_0, 0;
|
|
%load/vec4 v0x555555db40c0_0;
|
|
%assign/vec4 v0x555555db1f00_0, 0;
|
|
%pushi/vec4 0, 0, 64;
|
|
%assign/vec4 v0x555555db1840_0, 0;
|
|
%load/vec4 v0x555555db3b20_0;
|
|
%assign/vec4 v0x555555db14c0_0, 0;
|
|
%load/vec4 v0x555555db3c00_0;
|
|
%assign/vec4 v0x555555db1680_0, 0;
|
|
%pushi/vec4 0, 0, 3;
|
|
%assign/vec4 v0x555555db15a0_0, 0;
|
|
%pushi/vec4 0, 0, 16;
|
|
%assign/vec4 v0x555555db1d60_0, 0;
|
|
%pushi/vec4 0, 0, 26;
|
|
%split/vec4 7;
|
|
%ix/load 4, 3, 0;
|
|
%ix/load 5, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%assign/vec4/off/d v0x555555db1ae0_0, 4, 5;
|
|
%split/vec4 3;
|
|
%assign/vec4 v0x555555db1a00_0, 0;
|
|
%assign/vec4 v0x555555db1bc0_0, 0;
|
|
%load/vec4 v0x555555db3ce0_0;
|
|
%assign/vec4 v0x555555db1760_0, 0;
|
|
T_13.31 ;
|
|
T_13.29 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_13.33 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%cmpi/u 8, 0, 32;
|
|
%jmp/0xz T_13.34, 5;
|
|
%load/vec4 v0x555555db2380_0;
|
|
%pushi/vec4 448, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%load/vec4 v0x555555db2380_0;
|
|
%pushi/vec4 384, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db2380_0;
|
|
%pushi/vec4 320, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db2380_0;
|
|
%pushi/vec4 256, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db2380_0;
|
|
%pushi/vec4 192, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db2380_0;
|
|
%pushi/vec4 128, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db2380_0;
|
|
%pushi/vec4 64, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db2380_0;
|
|
%pushi/vec4 0, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%concat/vec4; draw_concat_vec4
|
|
%pad/u 128;
|
|
%ix/getv/s 5, v0x555555dae670_0;
|
|
%load/vec4a v0x555555dab910, 5;
|
|
%ix/vec4 4;
|
|
%shiftl 4;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555db2ce0, 4;
|
|
%pad/u 128;
|
|
%or;
|
|
%split/vec4 8;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 0, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db2260, 5, 6;
|
|
%split/vec4 8;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 64, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db2260, 5, 6;
|
|
%split/vec4 8;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 128, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db2260, 5, 6;
|
|
%split/vec4 8;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 192, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db2260, 5, 6;
|
|
%split/vec4 8;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 256, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db2260, 5, 6;
|
|
%split/vec4 8;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 320, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db2260, 5, 6;
|
|
%split/vec4 8;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 384, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db2260, 5, 6;
|
|
%split/vec4 8;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 448, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db2260, 5, 6;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555db2ce0, 0, 4;
|
|
%load/vec4 v0x555555db2580_0;
|
|
%pushi/vec4 56, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%add;
|
|
%part/u 1;
|
|
%load/vec4 v0x555555db2580_0;
|
|
%pushi/vec4 48, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%add;
|
|
%part/u 1;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db2580_0;
|
|
%pushi/vec4 40, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%add;
|
|
%part/u 1;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db2580_0;
|
|
%pushi/vec4 32, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%add;
|
|
%part/u 1;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db2580_0;
|
|
%pushi/vec4 24, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%add;
|
|
%part/u 1;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db2580_0;
|
|
%pushi/vec4 16, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%add;
|
|
%part/u 1;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db2580_0;
|
|
%pushi/vec4 8, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%add;
|
|
%part/u 1;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db2580_0;
|
|
%pushi/vec4 0, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%add;
|
|
%part/u 1;
|
|
%concat/vec4; draw_concat_vec4
|
|
%pad/u 16;
|
|
%ix/getv/s 5, v0x555555dae670_0;
|
|
%load/vec4a v0x555555dab910, 5;
|
|
%ix/load 5, 3, 0;
|
|
%flag_set/imm 4, 0;
|
|
%shiftr 5;
|
|
%ix/vec4 4;
|
|
%shiftl 4;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555db2da0, 4;
|
|
%pad/u 16;
|
|
%or;
|
|
%split/vec4 1;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 0, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db2460, 5, 6;
|
|
%split/vec4 1;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 8, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db2460, 5, 6;
|
|
%split/vec4 1;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 16, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db2460, 5, 6;
|
|
%split/vec4 1;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 24, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db2460, 5, 6;
|
|
%split/vec4 1;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 32, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db2460, 5, 6;
|
|
%split/vec4 1;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 40, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db2460, 5, 6;
|
|
%split/vec4 1;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 48, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db2460, 5, 6;
|
|
%split/vec4 1;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 56, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db2460, 5, 6;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555db2da0, 0, 4;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_13.33;
|
|
T_13.34 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_13.35 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%pad/u 36;
|
|
%cmpi/u 1, 0, 36;
|
|
%jmp/0xz T_13.36, 5;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555db2260, 4;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%ix/vec4/s 3;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555db2260, 0, 4;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555db2460, 4;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%ix/vec4/s 3;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555db2460, 0, 4;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_13.35;
|
|
T_13.36 ;
|
|
%load/vec4 v0x555555dae010_0;
|
|
%nor/r;
|
|
%flag_set/vec4 9;
|
|
%flag_get/vec4 9;
|
|
%jmp/0 T_13.39, 9;
|
|
%load/vec4 v0x555555db2b20_0;
|
|
%pad/u 32;
|
|
%pushi/vec4 14, 0, 32;
|
|
%cmp/e;
|
|
%flag_get/vec4 4;
|
|
%and;
|
|
T_13.39;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_13.37, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db2740_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db1ca0_0, 0;
|
|
T_13.37 ;
|
|
T_13.10 ;
|
|
T_13.1 ;
|
|
%jmp T_13;
|
|
.thread T_13;
|
|
.scope S_0x555555cfe490;
|
|
T_14 ;
|
|
%wait E_0x555555ba4230;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db1920_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db2660_0, 0, 1;
|
|
%load/vec4 v0x555555dab6d0_0;
|
|
%flag_set/vec4 8;
|
|
%flag_get/vec4 8;
|
|
%jmp/1 T_14.0, 8;
|
|
%load/vec4 v0x555555db3f40_0;
|
|
%or;
|
|
T_14.0;
|
|
%store/vec4 v0x555555dab610_0, 0, 1;
|
|
%load/vec4 v0x555555dae990_0;
|
|
%parti/s 1, 24, 6;
|
|
%store/vec4 v0x555555dab410_0, 0, 1;
|
|
%load/vec4 v0x555555dae990_0;
|
|
%parti/s 1, 23, 6;
|
|
%store/vec4 v0x555555dab850_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db1e40_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db28e0_0, 0, 1;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x555555db29a0_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db0390_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db0750_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555daac20_0, 0, 1;
|
|
%load/vec4 v0x555555db3e80_0;
|
|
%store/vec4 v0x555555db44c0_0, 0, 1;
|
|
%load/vec4 v0x555555db3dc0_0;
|
|
%store/vec4 v0x555555db4260_0, 0, 1;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_14.1 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%cmpi/s 8, 0, 32;
|
|
%jmp/0xz T_14.2, 5;
|
|
%load/vec4 v0x555555dab330_0;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%part/s 1;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4 v0x555555dab250_0, 4, 1;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555dab040, 4;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4a v0x555555daae80, 4, 0;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_14.1;
|
|
T_14.2 ;
|
|
%load/vec4 v0x555555daca50_0;
|
|
%nor/r;
|
|
%load/vec4 v0x555555dae990_0;
|
|
%parti/s 3, 19, 6;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555dab610_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555dae990_0;
|
|
%parti/s 1, 24, 6;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555dae990_0;
|
|
%parti/s 1, 23, 6;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555dae990_0;
|
|
%parti/s 3, 16, 6;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555dae990_0;
|
|
%parti/s 16, 0, 2;
|
|
%concat/vec4; draw_concat_vec4
|
|
%ix/load 4, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x555555dab4d0, 4, 0;
|
|
%load/vec4 v0x555555dae990_0;
|
|
%parti/s 1, 25, 6;
|
|
%ix/load 4, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%ix/load 5, 10, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_or 4, 8;
|
|
%store/vec4a v0x555555dab4d0, 4, 5;
|
|
%load/vec4 v0x555555daeb50_0;
|
|
%nor/r;
|
|
%concati/vec4 5, 0, 3;
|
|
%load/vec4 v0x555555dab610_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555dab410_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555dab850_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%concati/vec4 0, 0, 19;
|
|
%ix/load 4, 2, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x555555dab4d0, 4, 0;
|
|
%load/vec4 v0x555555daec10_0;
|
|
%nor/r;
|
|
%concati/vec4 4, 0, 3;
|
|
%load/vec4 v0x555555dab610_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555dab410_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555dab850_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%concati/vec4 0, 0, 19;
|
|
%ix/load 4, 3, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x555555dab4d0, 4, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%concati/vec4 3, 0, 3;
|
|
%load/vec4 v0x555555dab610_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555dab410_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555dab850_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%concati/vec4 0, 0, 19;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x555555dab4d0, 4, 0;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_14.3 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%cmpi/s 8, 0, 32;
|
|
%jmp/0xz T_14.4, 5;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555dabd60, 4;
|
|
%pad/u 32;
|
|
%cmpi/e 0, 0, 32;
|
|
%flag_mov 8, 4;
|
|
%jmp/0 T_14.5, 8;
|
|
%pushi/vec4 0, 0, 4;
|
|
%jmp/1 T_14.6, 8;
|
|
T_14.5 ; End of true expr.
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555dabd60, 4;
|
|
%subi 1, 0, 4;
|
|
%jmp/0 T_14.6, 8;
|
|
; End of false expr.
|
|
%blend;
|
|
T_14.6;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4a v0x555555dabca0, 4, 0;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555daba90, 4;
|
|
%pad/u 32;
|
|
%cmpi/e 0, 0, 32;
|
|
%flag_mov 8, 4;
|
|
%jmp/0 T_14.7, 8;
|
|
%pushi/vec4 0, 0, 4;
|
|
%jmp/1 T_14.8, 8;
|
|
T_14.7 ; End of true expr.
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555daba90, 4;
|
|
%subi 1, 0, 4;
|
|
%jmp/0 T_14.8, 8;
|
|
; End of false expr.
|
|
%blend;
|
|
T_14.8;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4a v0x555555dab9d0, 4, 0;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555dac680, 4;
|
|
%pad/u 32;
|
|
%cmpi/e 0, 0, 32;
|
|
%flag_mov 8, 4;
|
|
%jmp/0 T_14.9, 8;
|
|
%pushi/vec4 0, 0, 4;
|
|
%jmp/1 T_14.10, 8;
|
|
T_14.9 ; End of true expr.
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555dac680, 4;
|
|
%subi 1, 0, 4;
|
|
%jmp/0 T_14.10, 8;
|
|
; End of false expr.
|
|
%blend;
|
|
T_14.10;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4a v0x555555dac470, 4, 0;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555dac180, 4;
|
|
%pad/u 32;
|
|
%cmpi/e 0, 0, 32;
|
|
%flag_mov 8, 4;
|
|
%jmp/0 T_14.11, 8;
|
|
%pushi/vec4 0, 0, 4;
|
|
%jmp/1 T_14.12, 8;
|
|
T_14.11 ; End of true expr.
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555dac180, 4;
|
|
%subi 1, 0, 4;
|
|
%jmp/0 T_14.12, 8;
|
|
; End of false expr.
|
|
%blend;
|
|
T_14.12;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4a v0x555555dabf70, 4, 0;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_14.3;
|
|
T_14.4 ;
|
|
%pushi/vec4 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_14.13 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%pad/s 36;
|
|
%cmpi/s 6, 0, 36;
|
|
%jmp/0xz T_14.14, 5;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555db1340, 4;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%subi 1, 0, 32;
|
|
%ix/vec4/s 4;
|
|
%store/vec4a v0x555555db1280, 4, 0;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_14.13;
|
|
T_14.14 ;
|
|
%pushi/vec4 0, 0, 17;
|
|
%ix/load 4, 5, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x555555db1280, 4, 0;
|
|
%load/vec4 v0x555555db2740_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_14.15, 8;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x555555db28e0_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db29a0_0, 0, 1;
|
|
%load/vec4 v0x555555dab330_0;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%part/u 1;
|
|
%flag_set/vec4 9;
|
|
%flag_get/vec4 9;
|
|
%jmp/0 T_14.19, 9;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dab040, 4;
|
|
%load/vec4 v0x555555db2800_0;
|
|
%cmp/e;
|
|
%flag_get/vec4 4;
|
|
%and;
|
|
T_14.19;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_14.17, 8;
|
|
%load/vec4 v0x555555db2a60_0;
|
|
%flag_set/vec4 9;
|
|
%flag_get/vec4 9;
|
|
%jmp/0 T_14.22, 9;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dac680, 4;
|
|
%pad/u 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%cmp/e;
|
|
%flag_get/vec4 4;
|
|
%and;
|
|
T_14.22;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_14.20, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db28e0_0, 0, 1;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x555555db29a0_0, 0, 1;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x555555dab610_0, 0, 1;
|
|
%load/vec4 v0x555555db1fc0_0;
|
|
%concati/vec4 1, 0, 1;
|
|
%ix/load 4, 5, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x555555db1280, 4, 0;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dabd60, 4;
|
|
%cmpi/u 4, 0, 4;
|
|
%flag_or 5, 4;
|
|
%jmp/0xz T_14.23, 5;
|
|
%pushi/vec4 4, 0, 4;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%store/vec4a v0x555555dabca0, 4, 0;
|
|
T_14.23 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_14.25 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%cmpi/s 8, 0, 32;
|
|
%jmp/0xz T_14.26, 5;
|
|
%pushi/vec4 3, 0, 4;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%store/vec4a v0x555555dabf70, 4, 0;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_14.25;
|
|
T_14.26 ;
|
|
%pushi/vec4 3, 0, 4;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%store/vec4a v0x555555dabf70, 4, 0;
|
|
%pushi/vec4 0, 0, 4;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%store/vec4a v0x555555dac470, 4, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%concati/vec4 4, 0, 3;
|
|
%load/vec4 v0x555555dab610_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555dab410_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555dab850_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%concati/vec4 0, 0, 5;
|
|
%concati/vec4 0, 0, 1;
|
|
%load/vec4 v0x555555db2180_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%ix/load 4, 3, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x555555dab4d0, 4, 0;
|
|
%load/vec4 v0x555555dab610_0;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%ix/load 5, 21, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_or 4, 8;
|
|
%store/vec4a v0x555555dab4d0, 4, 5;
|
|
%load/vec4 v0x555555dab610_0;
|
|
%ix/load 4, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%ix/load 5, 21, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_or 4, 8;
|
|
%store/vec4a v0x555555dab4d0, 4, 5;
|
|
%load/vec4 v0x555555dab610_0;
|
|
%ix/load 4, 2, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%ix/load 5, 21, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_or 4, 8;
|
|
%store/vec4a v0x555555dab4d0, 4, 5;
|
|
%load/vec4 v0x555555dab610_0;
|
|
%ix/load 4, 3, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%ix/load 5, 21, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_or 4, 8;
|
|
%store/vec4a v0x555555dab4d0, 4, 5;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x555555db44c0_0, 0, 1;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x555555db4260_0, 0, 1;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x555555db2660_0, 0, 1;
|
|
%jmp T_14.21;
|
|
T_14.20 ;
|
|
%load/vec4 v0x555555db2a60_0;
|
|
%nor/r;
|
|
%flag_set/vec4 9;
|
|
%flag_get/vec4 9;
|
|
%jmp/0 T_14.29, 9;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dac180, 4;
|
|
%pad/u 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%cmp/e;
|
|
%flag_get/vec4 4;
|
|
%and;
|
|
T_14.29;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_14.27, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db28e0_0, 0, 1;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x555555db29a0_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555dab610_0, 0, 1;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dabd60, 4;
|
|
%cmpi/u 1, 0, 4;
|
|
%flag_or 5, 4;
|
|
%jmp/0xz T_14.30, 5;
|
|
%pushi/vec4 1, 0, 4;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%store/vec4a v0x555555dabca0, 4, 0;
|
|
T_14.30 ;
|
|
%pushi/vec4 0, 0, 4;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%store/vec4a v0x555555dabf70, 4, 0;
|
|
%pushi/vec4 1, 0, 4;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%store/vec4a v0x555555dac470, 4, 0;
|
|
%load/vec4 v0x555555db1fc0_0;
|
|
%concati/vec4 1, 0, 1;
|
|
%ix/load 4, 5, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x555555db1280, 4, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%concati/vec4 5, 0, 3;
|
|
%load/vec4 v0x555555dab610_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555dab410_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555dab850_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%concati/vec4 0, 0, 5;
|
|
%concati/vec4 0, 0, 1;
|
|
%load/vec4 v0x555555db2180_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%ix/load 4, 2, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x555555dab4d0, 4, 0;
|
|
%load/vec4 v0x555555dab610_0;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%ix/load 5, 21, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_or 4, 8;
|
|
%store/vec4a v0x555555dab4d0, 4, 5;
|
|
%load/vec4 v0x555555dab610_0;
|
|
%ix/load 4, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%ix/load 5, 21, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_or 4, 8;
|
|
%store/vec4a v0x555555dab4d0, 4, 5;
|
|
%load/vec4 v0x555555dab610_0;
|
|
%ix/load 4, 2, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%ix/load 5, 21, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_or 4, 8;
|
|
%store/vec4a v0x555555dab4d0, 4, 5;
|
|
%load/vec4 v0x555555dab610_0;
|
|
%ix/load 4, 3, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%ix/load 5, 21, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_or 4, 8;
|
|
%store/vec4a v0x555555dab4d0, 4, 5;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x555555db2660_0, 0, 1;
|
|
T_14.27 ;
|
|
T_14.21 ;
|
|
%jmp T_14.18;
|
|
T_14.17 ;
|
|
%load/vec4 v0x555555dab330_0;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%part/u 1;
|
|
%nor/r;
|
|
%flag_set/vec4 9;
|
|
%flag_get/vec4 9;
|
|
%jmp/0 T_14.34, 9;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555daba90, 4;
|
|
%pad/u 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%cmp/e;
|
|
%flag_get/vec4 4;
|
|
%and;
|
|
T_14.34;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_14.32, 8;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x555555daac20_0, 0, 1;
|
|
%pushi/vec4 3, 0, 4;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%store/vec4a v0x555555dabca0, 4, 0;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dac180, 4;
|
|
%cmpi/u 0, 0, 4;
|
|
%flag_or 5, 4;
|
|
%jmp/0xz T_14.35, 5;
|
|
%pushi/vec4 0, 0, 4;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%store/vec4a v0x555555dabf70, 4, 0;
|
|
T_14.35 ;
|
|
%pushi/vec4 0, 0, 4;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%store/vec4a v0x555555dac470, 4, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%concati/vec4 3, 0, 3;
|
|
%load/vec4 v0x555555dab610_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555dab410_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555dab850_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db2800_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x555555dab4d0, 4, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%ix/getv 4, v0x555555db20a0_0;
|
|
%store/vec4 v0x555555dab250_0, 4, 1;
|
|
%load/vec4 v0x555555db2800_0;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%store/vec4a v0x555555daae80, 4, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x555555db2660_0, 0, 1;
|
|
%jmp T_14.33;
|
|
T_14.32 ;
|
|
%load/vec4 v0x555555dab330_0;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%part/u 1;
|
|
%flag_set/vec4 10;
|
|
%flag_get/vec4 10;
|
|
%jmp/0 T_14.40, 10;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dab040, 4;
|
|
%load/vec4 v0x555555db2800_0;
|
|
%cmp/ne;
|
|
%flag_get/vec4 4;
|
|
%and;
|
|
T_14.40;
|
|
%flag_set/vec4 9;
|
|
%flag_get/vec4 9;
|
|
%jmp/0 T_14.39, 9;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dabd60, 4;
|
|
%pad/u 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%cmp/e;
|
|
%flag_get/vec4 4;
|
|
%and;
|
|
T_14.39;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_14.37, 8;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x555555db0750_0, 0, 1;
|
|
%pushi/vec4 1, 0, 4;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%store/vec4a v0x555555dab9d0, 4, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%concati/vec4 2, 0, 3;
|
|
%load/vec4 v0x555555dab610_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555dab410_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555dab850_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%pushi/vec4 0, 0, 5;
|
|
%concati/vec4 0, 0, 1;
|
|
%load/vec4 v0x555555db2800_0;
|
|
%parti/s 10, 0, 2;
|
|
%concat/vec4; draw_concat_vec4
|
|
%concat/vec4; draw_concat_vec4
|
|
%ix/load 4, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x555555dab4d0, 4, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%ix/getv 4, v0x555555db20a0_0;
|
|
%store/vec4 v0x555555dab250_0, 4, 1;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x555555db2660_0, 0, 1;
|
|
T_14.37 ;
|
|
T_14.33 ;
|
|
T_14.18 ;
|
|
T_14.15 ;
|
|
%load/vec4 v0x555555db1ca0_0;
|
|
%flag_set/vec4 9;
|
|
%flag_get/vec4 9;
|
|
%jmp/0 T_14.43, 9;
|
|
%load/vec4 v0x555555db1a00_0;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%cmp/e;
|
|
%flag_get/vec4 4;
|
|
%jmp/0 T_14.44, 4;
|
|
%load/vec4 v0x555555db2740_0;
|
|
%and;
|
|
T_14.44;
|
|
%nor/r;
|
|
%and;
|
|
T_14.43;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_14.41, 8;
|
|
%load/vec4 v0x555555dab330_0;
|
|
%load/vec4 v0x555555db1a00_0;
|
|
%part/u 1;
|
|
%flag_set/vec4 11;
|
|
%flag_get/vec4 11;
|
|
%jmp/0 T_14.49, 11;
|
|
%load/vec4 v0x555555db1a00_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dab040, 4;
|
|
%load/vec4 v0x555555db1bc0_0;
|
|
%cmp/ne;
|
|
%flag_get/vec4 4;
|
|
%and;
|
|
T_14.49;
|
|
%flag_set/vec4 10;
|
|
%flag_get/vec4 10;
|
|
%jmp/0 T_14.48, 10;
|
|
%load/vec4 v0x555555db1a00_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dabd60, 4;
|
|
%pad/u 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%cmp/e;
|
|
%flag_get/vec4 4;
|
|
%and;
|
|
T_14.48;
|
|
%flag_set/vec4 9;
|
|
%flag_get/vec4 9;
|
|
%jmp/0 T_14.47, 9;
|
|
%load/vec4 v0x555555db0750_0;
|
|
%nor/r;
|
|
%and;
|
|
T_14.47;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_14.45, 8;
|
|
%pushi/vec4 1, 0, 4;
|
|
%load/vec4 v0x555555db1a00_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%store/vec4a v0x555555dab9d0, 4, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%concati/vec4 2, 0, 3;
|
|
%load/vec4 v0x555555dab610_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555dab410_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555dab850_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db1a00_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%pushi/vec4 0, 0, 5;
|
|
%concati/vec4 0, 0, 1;
|
|
%load/vec4 v0x555555db1bc0_0;
|
|
%parti/s 10, 0, 2;
|
|
%concat/vec4; draw_concat_vec4
|
|
%concat/vec4; draw_concat_vec4
|
|
%ix/load 4, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x555555dab4d0, 4, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%ix/getv 4, v0x555555db1a00_0;
|
|
%store/vec4 v0x555555dab250_0, 4, 1;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x555555db1920_0, 0, 1;
|
|
%jmp T_14.46;
|
|
T_14.45 ;
|
|
%load/vec4 v0x555555dab330_0;
|
|
%load/vec4 v0x555555db1a00_0;
|
|
%part/u 1;
|
|
%nor/r;
|
|
%flag_set/vec4 10;
|
|
%flag_get/vec4 10;
|
|
%jmp/0 T_14.53, 10;
|
|
%load/vec4 v0x555555db1a00_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555daba90, 4;
|
|
%pad/u 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%cmp/e;
|
|
%flag_get/vec4 4;
|
|
%and;
|
|
T_14.53;
|
|
%flag_set/vec4 9;
|
|
%flag_get/vec4 9;
|
|
%jmp/0 T_14.52, 9;
|
|
%load/vec4 v0x555555daac20_0;
|
|
%nor/r;
|
|
%and;
|
|
T_14.52;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_14.50, 8;
|
|
%pushi/vec4 3, 0, 4;
|
|
%load/vec4 v0x555555db1a00_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%store/vec4a v0x555555dabca0, 4, 0;
|
|
%load/vec4 v0x555555db1a00_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dabf70, 4;
|
|
%cmpi/u 0, 0, 4;
|
|
%flag_or 5, 4;
|
|
%jmp/0xz T_14.54, 5;
|
|
%pushi/vec4 0, 0, 4;
|
|
%load/vec4 v0x555555db1a00_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%store/vec4a v0x555555dabf70, 4, 0;
|
|
T_14.54 ;
|
|
%pushi/vec4 0, 0, 4;
|
|
%load/vec4 v0x555555db1a00_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%store/vec4a v0x555555dac470, 4, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%concati/vec4 3, 0, 3;
|
|
%load/vec4 v0x555555dab610_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555dab410_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555dab850_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db1a00_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db1bc0_0;
|
|
%concat/vec4; draw_concat_vec4
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4a v0x555555dab4d0, 4, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%ix/getv 4, v0x555555db1a00_0;
|
|
%store/vec4 v0x555555dab250_0, 4, 1;
|
|
%load/vec4 v0x555555db1bc0_0;
|
|
%load/vec4 v0x555555db1a00_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%store/vec4a v0x555555daae80, 4, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x555555db1920_0, 0, 1;
|
|
T_14.50 ;
|
|
T_14.46 ;
|
|
T_14.41 ;
|
|
%load/vec4 v0x555555db1ca0_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_14.56, 8;
|
|
%load/vec4 v0x555555dab250_0;
|
|
%load/vec4 v0x555555db15a0_0;
|
|
%part/u 1;
|
|
%nor/r;
|
|
%flag_set/vec4 8;
|
|
%jmp/1 T_14.60, 8;
|
|
%load/vec4 v0x555555dab250_0;
|
|
%load/vec4 v0x555555db15a0_0;
|
|
%part/u 1;
|
|
%flag_set/vec4 10;
|
|
%flag_get/vec4 10;
|
|
%jmp/0 T_14.61, 10;
|
|
%load/vec4 v0x555555db15a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555daae80, 4;
|
|
%load/vec4 v0x555555db1d60_0;
|
|
%cmp/ne;
|
|
%flag_get/vec4 4;
|
|
%and;
|
|
T_14.61;
|
|
%flag_set/vec4 9;
|
|
%flag_or 8, 9;
|
|
T_14.60;
|
|
%jmp/0xz T_14.58, 8;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x555555db1e40_0, 0, 1;
|
|
%jmp T_14.59;
|
|
T_14.58 ;
|
|
%load/vec4 v0x555555db1f00_0;
|
|
%nor/r;
|
|
%flag_set/vec4 9;
|
|
%flag_get/vec4 9;
|
|
%jmp/0 T_14.64, 9;
|
|
%load/vec4 v0x555555db15a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dabf70, 4;
|
|
%pad/u 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%cmp/ne;
|
|
%flag_get/vec4 4;
|
|
%and;
|
|
T_14.64;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_14.62, 8;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x555555db1e40_0, 0, 1;
|
|
%jmp T_14.63;
|
|
T_14.62 ;
|
|
%load/vec4 v0x555555db1f00_0;
|
|
%flag_set/vec4 9;
|
|
%flag_get/vec4 9;
|
|
%jmp/0 T_14.67, 9;
|
|
%load/vec4 v0x555555db15a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dac470, 4;
|
|
%pad/u 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%cmp/ne;
|
|
%flag_get/vec4 4;
|
|
%and;
|
|
T_14.67;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_14.65, 8;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x555555db1e40_0, 0, 1;
|
|
T_14.65 ;
|
|
T_14.63 ;
|
|
T_14.59 ;
|
|
T_14.56 ;
|
|
%load/vec4 v0x555555db2740_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_14.68, 8;
|
|
%load/vec4 v0x555555dab250_0;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%part/u 1;
|
|
%flag_set/vec4 9;
|
|
%flag_get/vec4 9;
|
|
%jmp/0 T_14.72, 9;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555daae80, 4;
|
|
%load/vec4 v0x555555db2800_0;
|
|
%cmp/e;
|
|
%flag_get/vec4 4;
|
|
%and;
|
|
T_14.72;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_14.70, 8;
|
|
%load/vec4 v0x555555db2a60_0;
|
|
%flag_set/vec4 9;
|
|
%flag_get/vec4 9;
|
|
%jmp/0 T_14.75, 9;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dac470, 4;
|
|
%pad/u 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%cmp/e;
|
|
%flag_get/vec4 4;
|
|
%and;
|
|
T_14.75;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_14.73, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db28e0_0, 0, 1;
|
|
%jmp T_14.74;
|
|
T_14.73 ;
|
|
%load/vec4 v0x555555db2a60_0;
|
|
%nor/r;
|
|
%flag_set/vec4 9;
|
|
%flag_get/vec4 9;
|
|
%jmp/0 T_14.78, 9;
|
|
%load/vec4 v0x555555db20a0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dabf70, 4;
|
|
%pad/u 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%cmp/e;
|
|
%flag_get/vec4 4;
|
|
%and;
|
|
T_14.78;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_14.76, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db28e0_0, 0, 1;
|
|
T_14.76 ;
|
|
T_14.74 ;
|
|
T_14.70 ;
|
|
T_14.68 ;
|
|
%load/vec4 v0x555555db0450_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_14.79, 8;
|
|
%load/vec4 v0x555555db28e0_0;
|
|
%store/vec4 v0x555555db0390_0, 0, 1;
|
|
%jmp T_14.80;
|
|
T_14.79 ;
|
|
%load/vec4 v0x555555dae290_0;
|
|
%nor/r;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_14.81, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db0390_0, 0, 1;
|
|
%jmp T_14.82;
|
|
T_14.81 ;
|
|
%load/vec4 v0x555555db1ca0_0;
|
|
%nor/r;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_14.83, 8;
|
|
%load/vec4 v0x555555db28e0_0;
|
|
%store/vec4 v0x555555db0390_0, 0, 1;
|
|
%jmp T_14.84;
|
|
T_14.83 ;
|
|
%load/vec4 v0x555555db1e40_0;
|
|
%store/vec4 v0x555555db0390_0, 0, 1;
|
|
T_14.84 ;
|
|
T_14.82 ;
|
|
T_14.80 ;
|
|
%load/vec4 v0x555555dae010_0;
|
|
%nor/r;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_14.85, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db0390_0, 0, 1;
|
|
T_14.85 ;
|
|
%jmp T_14;
|
|
.thread T_14, $push;
|
|
.scope S_0x555555cfe490;
|
|
T_15 ;
|
|
%wait E_0x555555cb9a50;
|
|
%load/vec4 v0x555555dad990_0;
|
|
%nor/r;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_15.0, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555dae750_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555dae810_0, 0;
|
|
%pushi/vec4 0, 0, 3;
|
|
%assign/vec4 v0x555555db4660_0, 0;
|
|
%pushi/vec4 0, 0, 2;
|
|
%assign/vec4 v0x555555db4580_0, 0;
|
|
%pushi/vec4 0, 0, 3;
|
|
%assign/vec4 v0x555555db43e0_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db4320_0, 0;
|
|
%pushi/vec4 0, 0, 4;
|
|
%assign/vec4 v0x555555db4180_0, 0;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_15.2 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%cmpi/s 2, 0, 32;
|
|
%jmp/0xz T_15.3, 5;
|
|
%pushi/vec4 0, 0, 16;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dacb10, 0, 4;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_15.2;
|
|
T_15.3 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_15.4 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%cmpi/s 2, 0, 32;
|
|
%jmp/0xz T_15.5, 5;
|
|
%pushi/vec4 0, 0, 512;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555db0210, 0, 4;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_15.4;
|
|
T_15.5 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_15.6 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%pad/s 36;
|
|
%cmpi/s 6, 0, 36;
|
|
%jmp/0xz T_15.7, 5;
|
|
%pushi/vec4 0, 0, 17;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555db1340, 0, 4;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_15.6;
|
|
T_15.7 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_15.8 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%cmpi/s 16, 0, 32;
|
|
%jmp/0xz T_15.9, 5;
|
|
%pushi/vec4 0, 0, 17;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dafe70, 0, 4;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_15.8;
|
|
T_15.9 ;
|
|
%jmp T_15.1;
|
|
T_15.0 ;
|
|
%load/vec4 v0x555555db44c0_0;
|
|
%flag_set/vec4 8;
|
|
%flag_get/vec4 8;
|
|
%jmp/1 T_15.10, 8;
|
|
%load/vec4 v0x555555db4580_0;
|
|
%parti/s 1, 0, 2;
|
|
%or;
|
|
T_15.10;
|
|
%ix/load 4, 0, 0;
|
|
%ix/load 5, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%assign/vec4/off/d v0x555555db4660_0, 4, 5;
|
|
%load/vec4 v0x555555db44c0_0;
|
|
%ix/load 4, 0, 0;
|
|
%ix/load 5, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%assign/vec4/off/d v0x555555db4580_0, 4, 5;
|
|
%load/vec4 v0x555555db4580_0;
|
|
%parti/s 1, 0, 2;
|
|
%ix/load 4, 1, 0;
|
|
%ix/load 5, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%assign/vec4/off/d v0x555555db4580_0, 4, 5;
|
|
%load/vec4 v0x555555db44c0_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/1 T_15.12, 8;
|
|
%load/vec4 v0x555555db4580_0;
|
|
%parti/s 1, 1, 2;
|
|
%flag_set/vec4 9;
|
|
%flag_or 8, 9;
|
|
T_15.12;
|
|
%flag_get/vec4 8;
|
|
%jmp/1 T_15.11, 8;
|
|
%load/vec4 v0x555555db4580_0;
|
|
%parti/s 1, 0, 2;
|
|
%or;
|
|
T_15.11;
|
|
%ix/load 4, 0, 0;
|
|
%ix/load 5, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%assign/vec4/off/d v0x555555db43e0_0, 4, 5;
|
|
%load/vec4 v0x555555db4260_0;
|
|
%assign/vec4 v0x555555db4320_0, 0;
|
|
%load/vec4 v0x555555db4260_0;
|
|
%flag_set/vec4 8;
|
|
%flag_get/vec4 8;
|
|
%jmp/1 T_15.13, 8;
|
|
%load/vec4 v0x555555db4320_0;
|
|
%or;
|
|
T_15.13;
|
|
%ix/load 4, 0, 0;
|
|
%ix/load 5, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%assign/vec4/off/d v0x555555db4180_0, 4, 5;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_15.14 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%pad/u 36;
|
|
%cmpi/u 2, 0, 36;
|
|
%jmp/0xz T_15.15, 5;
|
|
%load/vec4 v0x555555db43e0_0;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%part/s 1;
|
|
%ix/load 5, 0, 0;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%ix/vec4/s 4;
|
|
%assign/vec4/off/d v0x555555db43e0_0, 4, 5;
|
|
%load/vec4 v0x555555db4660_0;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%part/s 1;
|
|
%ix/load 5, 0, 0;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%ix/vec4/s 4;
|
|
%assign/vec4/off/d v0x555555db4660_0, 4, 5;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_15.14;
|
|
T_15.15 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_15.16 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%pad/u 36;
|
|
%cmpi/u 3, 0, 36;
|
|
%jmp/0xz T_15.17, 5;
|
|
%load/vec4 v0x555555db4180_0;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%part/s 1;
|
|
%ix/load 5, 0, 0;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%ix/vec4/s 4;
|
|
%assign/vec4/off/d v0x555555db4180_0, 4, 5;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_15.16;
|
|
T_15.17 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_15.18 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%pad/s 36;
|
|
%cmpi/s 6, 0, 36;
|
|
%jmp/0xz T_15.19, 5;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555db1280, 4;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555db1340, 0, 4;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_15.18;
|
|
T_15.19 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_15.20 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%cmpi/s 2, 0, 32;
|
|
%jmp/0xz T_15.21, 5;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555dacb10, 4;
|
|
%ix/load 4, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%shiftr 4;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dacb10, 0, 4;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_15.20;
|
|
T_15.21 ;
|
|
%ix/load 4, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%load/vec4a v0x555555db1340, 4;
|
|
%parti/s 1, 0, 2;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_15.22, 8;
|
|
%load/vec4 v0x555555dae750_0;
|
|
%nor/r;
|
|
%assign/vec4 v0x555555dae750_0, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%load/vec4 v0x555555dae750_0;
|
|
%pad/u 3;
|
|
%ix/vec4 4;
|
|
%flag_mov 8, 4;
|
|
%ix/getv 5, v0x555555daada0_0;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555dacb10, 5, 6;
|
|
T_15.22 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_15.24 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%cmpi/u 8, 0, 32;
|
|
%jmp/0xz T_15.25, 5;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%load/vec4a v0x555555dacb10, 4;
|
|
%pushi/vec4 0, 0, 3;
|
|
%load/vec4 v0x555555daada0_0;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555daace0, 4;
|
|
%cmp/ne;
|
|
%flag_get/vec4 4;
|
|
%concat/vec4; draw_concat_vec4
|
|
%part/u 1;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_15.26, 8;
|
|
%load/vec4 v0x555555dad7d0_0;
|
|
%pushi/vec4 0, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 0, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db0210, 5, 6;
|
|
%load/vec4 v0x555555dad7d0_0;
|
|
%pushi/vec4 64, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 64, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db0210, 5, 6;
|
|
%load/vec4 v0x555555dad7d0_0;
|
|
%pushi/vec4 128, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 128, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db0210, 5, 6;
|
|
%load/vec4 v0x555555dad7d0_0;
|
|
%pushi/vec4 192, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 192, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db0210, 5, 6;
|
|
%load/vec4 v0x555555dad7d0_0;
|
|
%pushi/vec4 256, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 256, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db0210, 5, 6;
|
|
%load/vec4 v0x555555dad7d0_0;
|
|
%pushi/vec4 320, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 320, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db0210, 5, 6;
|
|
%load/vec4 v0x555555dad7d0_0;
|
|
%pushi/vec4 384, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 384, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db0210, 5, 6;
|
|
%load/vec4 v0x555555dad7d0_0;
|
|
%pushi/vec4 448, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 448, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db0210, 5, 6;
|
|
T_15.26 ;
|
|
%ix/load 4, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%load/vec4a v0x555555dacb10, 4;
|
|
%pushi/vec4 0, 0, 3;
|
|
%load/vec4 v0x555555daada0_0;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555daace0, 4;
|
|
%cmp/ne;
|
|
%flag_get/vec4 4;
|
|
%concat/vec4; draw_concat_vec4
|
|
%part/u 1;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_15.28, 8;
|
|
%load/vec4 v0x555555dad7d0_0;
|
|
%pushi/vec4 0, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%ix/load 4, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 0, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db0210, 5, 6;
|
|
%load/vec4 v0x555555dad7d0_0;
|
|
%pushi/vec4 64, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%ix/load 4, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 64, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db0210, 5, 6;
|
|
%load/vec4 v0x555555dad7d0_0;
|
|
%pushi/vec4 128, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%ix/load 4, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 128, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db0210, 5, 6;
|
|
%load/vec4 v0x555555dad7d0_0;
|
|
%pushi/vec4 192, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%ix/load 4, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 192, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db0210, 5, 6;
|
|
%load/vec4 v0x555555dad7d0_0;
|
|
%pushi/vec4 256, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%ix/load 4, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 256, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db0210, 5, 6;
|
|
%load/vec4 v0x555555dad7d0_0;
|
|
%pushi/vec4 320, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%ix/load 4, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 320, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db0210, 5, 6;
|
|
%load/vec4 v0x555555dad7d0_0;
|
|
%pushi/vec4 384, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%ix/load 4, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 384, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db0210, 5, 6;
|
|
%load/vec4 v0x555555dad7d0_0;
|
|
%pushi/vec4 448, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%ix/load 4, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%flag_mov 8, 4;
|
|
%pushi/vec4 448, 0, 32;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%ix/vec4 5;
|
|
%flag_or 8, 4;
|
|
%ix/load 6, 0, 0; Constant delay
|
|
%ix/mov 3, 4;
|
|
%flag_mov 4, 8;
|
|
%assign/vec4/a/d v0x555555db0210, 5, 6;
|
|
T_15.28 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_15.24;
|
|
T_15.25 ;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%load/vec4a v0x555555dafe70, 4;
|
|
%parti/s 1, 0, 2;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_15.30, 8;
|
|
%load/vec4 v0x555555dae810_0;
|
|
%nor/r;
|
|
%assign/vec4 v0x555555dae810_0, 0;
|
|
T_15.30 ;
|
|
%pushi/vec4 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_15.32 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%cmpi/s 16, 0, 32;
|
|
%jmp/0xz T_15.33, 5;
|
|
%ix/getv/s 4, v0x555555dae670_0;
|
|
%load/vec4a v0x555555dafe70, 4;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%subi 1, 0, 32;
|
|
%ix/vec4/s 3;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dafe70, 0, 4;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_15.32;
|
|
T_15.33 ;
|
|
%pushi/vec4 0, 0, 17;
|
|
%ix/load 3, 15, 0;
|
|
%flag_set/imm 4, 0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dafe70, 0, 4;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%load/vec4a v0x555555db1340, 4;
|
|
%load/vec4 v0x555555daada0_0;
|
|
%pad/u 6;
|
|
%ix/vec4 3;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dafe70, 0, 4;
|
|
%load/vec4 v0x555555dae010_0;
|
|
%nor/r;
|
|
%flag_set/vec4 9;
|
|
%flag_get/vec4 9;
|
|
%jmp/0 T_15.36, 9;
|
|
%load/vec4 v0x555555db2b20_0;
|
|
%pad/u 32;
|
|
%pushi/vec4 14, 0, 32;
|
|
%cmp/e;
|
|
%flag_get/vec4 4;
|
|
%and;
|
|
T_15.36;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_15.34, 8;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_15.37 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%cmpi/s 16, 0, 32;
|
|
%jmp/0xz T_15.38, 5;
|
|
%pushi/vec4 0, 0, 17;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dafe70, 0, 4;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_15.37;
|
|
T_15.38 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_15.39 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%pad/s 36;
|
|
%cmpi/s 6, 0, 36;
|
|
%jmp/0xz T_15.40, 5;
|
|
%pushi/vec4 0, 0, 17;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555db1340, 0, 4;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_15.39;
|
|
T_15.40 ;
|
|
T_15.34 ;
|
|
T_15.1 ;
|
|
%jmp T_15;
|
|
.thread T_15;
|
|
.scope S_0x555555cfe490;
|
|
T_16 ;
|
|
%wait E_0x555555cb9a50;
|
|
%load/vec4 v0x555555dad990_0;
|
|
%nor/r;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_16.0, 8;
|
|
%pushi/vec4 0, 0, 5;
|
|
%assign/vec4 v0x555555db2b20_0, 0;
|
|
%pushi/vec4 0, 0, 2;
|
|
%assign/vec4 v0x555555db2c00_0, 0;
|
|
%pushi/vec4 0, 0, 40;
|
|
%assign/vec4 v0x555555dad110_0, 0;
|
|
%pushi/vec4 0, 0, 4;
|
|
%assign/vec4 v0x555555dacd90_0, 0;
|
|
%pushi/vec4 0, 0, 6;
|
|
%assign/vec4 v0x555555dace70_0, 0;
|
|
%pushi/vec4 0, 0, 6;
|
|
%assign/vec4 v0x555555dad1f0_0, 0;
|
|
%pushi/vec4 0, 0, 6;
|
|
%assign/vec4 v0x555555dad2d0_0, 0;
|
|
%pushi/vec4 0, 0, 8;
|
|
%assign/vec4 v0x555555daee90_0, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555dae8d0_0, 0;
|
|
%pushi/vec4 0, 0, 3;
|
|
%assign/vec4 v0x555555daecd0_0, 0;
|
|
%pushi/vec4 0, 0, 16;
|
|
%assign/vec4 v0x555555daccb0_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db3e80_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db3dc0_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db3f40_0, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555db0810_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db4000_0, 0;
|
|
%pushi/vec4 0, 0, 16;
|
|
%assign/vec4 v0x555555db3b20_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db40c0_0, 0;
|
|
%pushi/vec4 0, 0, 10;
|
|
%assign/vec4 v0x555555db3c00_0, 0;
|
|
%pushi/vec4 0, 0, 512;
|
|
%assign/vec4 v0x555555db3ce0_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db0690_0, 0;
|
|
%pushi/vec4 0, 0, 512;
|
|
%assign/vec4 v0x555555db10e0_0, 0;
|
|
%pushi/vec4 0, 0, 128;
|
|
%assign/vec4 v0x555555db4740_0, 0;
|
|
%pushi/vec4 0, 0, 4;
|
|
%assign/vec4 v0x555555daada0_0, 0;
|
|
%pushi/vec4 0, 0, 6;
|
|
%assign/vec4 v0x555555dad030_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555dacf50_0, 0;
|
|
%pushi/vec4 0, 0, 5;
|
|
%assign/vec4 v0x555555dac890_0, 0;
|
|
%pushi/vec4 0, 0, 4;
|
|
%assign/vec4 v0x555555dac390_0, 0;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
T_16.2 ;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%cmpi/u 8, 0, 32;
|
|
%jmp/0xz T_16.3, 5;
|
|
%pushi/vec4 0, 0, 4;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555daace0, 0, 4;
|
|
%pushi/vec4 0, 0, 7;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dab910, 0, 4;
|
|
%pushi/vec4 0, 0, 5;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555db0510, 0, 4;
|
|
%pushi/vec4 8, 0, 5;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555db05d0, 0, 4;
|
|
%pushi/vec4 0, 0, 5;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dae410, 0, 4;
|
|
%pushi/vec4 8, 0, 5;
|
|
%ix/getv/s 3, v0x555555dae670_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dae5b0, 0, 4;
|
|
%load/vec4 v0x555555dae670_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0x555555dae670_0, 0, 32;
|
|
%jmp T_16.2;
|
|
T_16.3 ;
|
|
%jmp T_16.1;
|
|
T_16.0 ;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db4000_0, 0;
|
|
%pushi/vec4 0, 0, 16;
|
|
%assign/vec4 v0x555555db3b20_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db40c0_0, 0;
|
|
%pushi/vec4 0, 0, 10;
|
|
%assign/vec4 v0x555555db3c00_0, 0;
|
|
%pushi/vec4 0, 0, 512;
|
|
%assign/vec4 v0x555555db3ce0_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db3e80_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db3dc0_0, 0;
|
|
%load/vec4 v0x555555db2c00_0;
|
|
%pad/u 32;
|
|
%cmpi/e 0, 0, 32;
|
|
%flag_mov 8, 4;
|
|
%jmp/0 T_16.4, 8;
|
|
%pushi/vec4 0, 0, 2;
|
|
%jmp/1 T_16.5, 8;
|
|
T_16.4 ; End of true expr.
|
|
%load/vec4 v0x555555db2c00_0;
|
|
%subi 1, 0, 2;
|
|
%jmp/0 T_16.5, 8;
|
|
; End of false expr.
|
|
%blend;
|
|
T_16.5;
|
|
%assign/vec4 v0x555555db2c00_0, 0;
|
|
%load/vec4 v0x555555dac390_0;
|
|
%pad/u 32;
|
|
%cmpi/e 0, 0, 32;
|
|
%flag_mov 8, 4;
|
|
%jmp/0 T_16.6, 8;
|
|
%pushi/vec4 0, 0, 4;
|
|
%jmp/1 T_16.7, 8;
|
|
T_16.6 ; End of true expr.
|
|
%load/vec4 v0x555555dac390_0;
|
|
%subi 1, 0, 4;
|
|
%jmp/0 T_16.7, 8;
|
|
; End of false expr.
|
|
%blend;
|
|
T_16.7;
|
|
%assign/vec4 v0x555555dac390_0, 0;
|
|
%load/vec4 v0x555555dac890_0;
|
|
%pad/u 32;
|
|
%cmpi/e 0, 0, 32;
|
|
%flag_mov 8, 4;
|
|
%jmp/0 T_16.8, 8;
|
|
%pushi/vec4 0, 0, 5;
|
|
%jmp/1 T_16.9, 8;
|
|
T_16.8 ; End of true expr.
|
|
%load/vec4 v0x555555dac890_0;
|
|
%subi 1, 0, 5;
|
|
%jmp/0 T_16.9, 8;
|
|
; End of false expr.
|
|
%blend;
|
|
T_16.9;
|
|
%assign/vec4 v0x555555dac890_0, 0;
|
|
%pushi/vec4 0, 0, 8;
|
|
%assign/vec4 v0x555555daee90_0, 0;
|
|
%pushi/vec4 0, 0, 8;
|
|
%assign/vec4 v0x555555daf7f0_0, 0;
|
|
%pushi/vec4 0, 0, 8;
|
|
%assign/vec4 v0x555555daf9b0_0, 0;
|
|
%pushi/vec4 0, 0, 8;
|
|
%assign/vec4 v0x555555daf470_0, 0;
|
|
%pushi/vec4 0, 0, 8;
|
|
%assign/vec4 v0x555555daf630_0, 0;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dae410, 4;
|
|
%assign/vec4 v0x555555dae4d0_0, 0;
|
|
%load/vec4 v0x555555db38c0_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_16.10, 8;
|
|
%load/vec4 v0x555555db3480_0;
|
|
%load/vec4 v0x555555db3a40_0;
|
|
%part/u 1;
|
|
%flag_set/vec4 8;
|
|
%jmp/0 T_16.12, 8;
|
|
%load/vec4 v0x555555db33a0_0;
|
|
%jmp/1 T_16.13, 8;
|
|
T_16.12 ; End of true expr.
|
|
%load/vec4 v0x555555db3a40_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555db0510, 4;
|
|
%jmp/0 T_16.13, 8;
|
|
; End of false expr.
|
|
%blend;
|
|
T_16.13;
|
|
%load/vec4 v0x555555db3a40_0;
|
|
%pad/u 5;
|
|
%ix/vec4 3;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555db0510, 0, 4;
|
|
%load/vec4 v0x555555db3640_0;
|
|
%load/vec4 v0x555555db3a40_0;
|
|
%part/u 1;
|
|
%flag_set/vec4 8;
|
|
%jmp/0 T_16.14, 8;
|
|
%load/vec4 v0x555555db3560_0;
|
|
%jmp/1 T_16.15, 8;
|
|
T_16.14 ; End of true expr.
|
|
%load/vec4 v0x555555db3a40_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555db05d0, 4;
|
|
%jmp/0 T_16.15, 8;
|
|
; End of false expr.
|
|
%blend;
|
|
T_16.15;
|
|
%load/vec4 v0x555555db3a40_0;
|
|
%pad/u 5;
|
|
%ix/vec4 3;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555db05d0, 0, 4;
|
|
%load/vec4 v0x555555db3100_0;
|
|
%load/vec4 v0x555555db3a40_0;
|
|
%part/u 1;
|
|
%flag_set/vec4 8;
|
|
%jmp/0 T_16.16, 8;
|
|
%load/vec4 v0x555555db3020_0;
|
|
%jmp/1 T_16.17, 8;
|
|
T_16.16 ; End of true expr.
|
|
%load/vec4 v0x555555db3a40_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dae410, 4;
|
|
%jmp/0 T_16.17, 8;
|
|
; End of false expr.
|
|
%blend;
|
|
T_16.17;
|
|
%load/vec4 v0x555555db3a40_0;
|
|
%pad/u 5;
|
|
%ix/vec4 3;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dae410, 0, 4;
|
|
%load/vec4 v0x555555db32c0_0;
|
|
%load/vec4 v0x555555db3a40_0;
|
|
%part/u 1;
|
|
%flag_set/vec4 8;
|
|
%jmp/0 T_16.18, 8;
|
|
%load/vec4 v0x555555db31e0_0;
|
|
%jmp/1 T_16.19, 8;
|
|
T_16.18 ; End of true expr.
|
|
%load/vec4 v0x555555db3a40_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dae5b0, 4;
|
|
%jmp/0 T_16.19, 8;
|
|
; End of false expr.
|
|
%blend;
|
|
T_16.19;
|
|
%load/vec4 v0x555555db3a40_0;
|
|
%pad/u 5;
|
|
%ix/vec4 3;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dae5b0, 0, 4;
|
|
%load/vec4 v0x555555db3480_0;
|
|
%assign/vec4 v0x555555daf7f0_0, 0;
|
|
%load/vec4 v0x555555db3640_0;
|
|
%assign/vec4 v0x555555daf9b0_0, 0;
|
|
%load/vec4 v0x555555db3100_0;
|
|
%assign/vec4 v0x555555daf470_0, 0;
|
|
%load/vec4 v0x555555db32c0_0;
|
|
%assign/vec4 v0x555555daf630_0, 0;
|
|
%load/vec4 v0x555555db3a40_0;
|
|
%assign/vec4 v0x555555daecd0_0, 0;
|
|
%jmp T_16.11;
|
|
T_16.10 ;
|
|
%load/vec4 v0x555555db2b20_0;
|
|
%pad/u 32;
|
|
%cmpi/ne 14, 0, 32;
|
|
%jmp/0xz T_16.20, 4;
|
|
%load/vec4 v0x555555daf7f0_0;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%part/u 1;
|
|
%flag_set/vec4 8;
|
|
%jmp/0 T_16.22, 8;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555db0510, 4;
|
|
%addi 1, 0, 5;
|
|
%jmp/1 T_16.23, 8;
|
|
T_16.22 ; End of true expr.
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555db0510, 4;
|
|
%jmp/0 T_16.23, 8;
|
|
; End of false expr.
|
|
%blend;
|
|
T_16.23;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 3;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555db0510, 0, 4;
|
|
%load/vec4 v0x555555daf9b0_0;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%part/u 1;
|
|
%flag_set/vec4 8;
|
|
%jmp/0 T_16.24, 8;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555db05d0, 4;
|
|
%addi 1, 0, 5;
|
|
%jmp/1 T_16.25, 8;
|
|
T_16.24 ; End of true expr.
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555db05d0, 4;
|
|
%jmp/0 T_16.25, 8;
|
|
; End of false expr.
|
|
%blend;
|
|
T_16.25;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 3;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555db05d0, 0, 4;
|
|
%load/vec4 v0x555555daf470_0;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%part/u 1;
|
|
%flag_set/vec4 8;
|
|
%jmp/0 T_16.26, 8;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dae410, 4;
|
|
%addi 1, 0, 5;
|
|
%jmp/1 T_16.27, 8;
|
|
T_16.26 ; End of true expr.
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dae410, 4;
|
|
%jmp/0 T_16.27, 8;
|
|
; End of false expr.
|
|
%blend;
|
|
T_16.27;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 3;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dae410, 0, 4;
|
|
%load/vec4 v0x555555daf630_0;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%part/u 1;
|
|
%flag_set/vec4 8;
|
|
%jmp/0 T_16.28, 8;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dae5b0, 4;
|
|
%addi 1, 0, 5;
|
|
%jmp/1 T_16.29, 8;
|
|
T_16.28 ; End of true expr.
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dae5b0, 4;
|
|
%jmp/0 T_16.29, 8;
|
|
; End of false expr.
|
|
%blend;
|
|
T_16.29;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 3;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dae5b0, 0, 4;
|
|
T_16.20 ;
|
|
T_16.11 ;
|
|
%load/vec4 v0x555555dae8d0_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_16.30, 8;
|
|
%load/vec4 v0x555555dad3b0_0;
|
|
%assign/vec4 v0x555555dad1f0_0, 0;
|
|
%load/vec4 v0x555555dad3b0_0;
|
|
%assign/vec4 v0x555555dacbd0_0, 0;
|
|
%load/vec4 v0x555555dad3b0_0;
|
|
%assign/vec4 v0x555555dad2d0_0, 0;
|
|
T_16.30 ;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dae5b0, 4;
|
|
%pad/u 32;
|
|
%cmpi/e 0, 0, 32;
|
|
%jmp/0xz T_16.32, 4;
|
|
%load/vec4 v0x555555dad2d0_0;
|
|
%subi 2, 0, 6;
|
|
%assign/vec4 v0x555555dad1f0_0, 0;
|
|
T_16.32 ;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dae410, 4;
|
|
%pad/u 32;
|
|
%cmpi/e 0, 0, 32;
|
|
%flag_get/vec4 4;
|
|
%jmp/0 T_16.36, 4;
|
|
%load/vec4 v0x555555dae4d0_0;
|
|
%pad/u 32;
|
|
%pushi/vec4 31, 0, 32;
|
|
%cmp/e;
|
|
%flag_get/vec4 4;
|
|
%and;
|
|
T_16.36;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_16.34, 8;
|
|
%load/vec4 v0x555555dad2d0_0;
|
|
%subi 2, 0, 6;
|
|
%assign/vec4 v0x555555dacbd0_0, 0;
|
|
T_16.34 ;
|
|
%load/vec4 v0x555555db2b20_0;
|
|
%dup/vec4;
|
|
%pushi/vec4 0, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_16.37, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 1, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_16.38, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 2, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_16.39, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 3, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_16.40, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 4, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_16.41, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 5, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_16.42, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 6, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_16.43, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 7, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_16.44, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 8, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_16.45, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 9, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_16.46, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 10, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_16.47, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 11, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_16.48, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 12, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_16.49, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 13, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_16.50, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 14, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_16.51, 6;
|
|
%jmp T_16.52;
|
|
T_16.37 ;
|
|
%load/vec4 v0x555555dad630_0;
|
|
%flag_set/vec4 9;
|
|
%flag_get/vec4 9;
|
|
%jmp/0 T_16.55, 9;
|
|
%load/vec4 v0x555555daea70_0;
|
|
%pad/u 32;
|
|
%pushi/vec4 13, 0, 32;
|
|
%cmp/e;
|
|
%flag_get/vec4 4;
|
|
%and;
|
|
T_16.55;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_16.53, 8;
|
|
%pushi/vec4 1, 0, 5;
|
|
%assign/vec4 v0x555555db2b20_0, 0;
|
|
%pushi/vec4 0, 0, 3;
|
|
%assign/vec4 v0x555555daecd0_0, 0;
|
|
%pushi/vec4 255, 0, 8;
|
|
%assign/vec4 v0x555555daf7f0_0, 0;
|
|
%pushi/vec4 255, 0, 8;
|
|
%assign/vec4 v0x555555daf9b0_0, 0;
|
|
%pushi/vec4 255, 0, 8;
|
|
%assign/vec4 v0x555555daf470_0, 0;
|
|
%pushi/vec4 255, 0, 8;
|
|
%assign/vec4 v0x555555daf630_0, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555db0690_0, 0;
|
|
%jmp T_16.54;
|
|
T_16.53 ;
|
|
%load/vec4 v0x555555daea70_0;
|
|
%pad/u 32;
|
|
%cmpi/e 13, 0, 32;
|
|
%jmp/0xz T_16.56, 4;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555db0690_0, 0;
|
|
T_16.56 ;
|
|
T_16.54 ;
|
|
%jmp T_16.52;
|
|
T_16.38 ;
|
|
%load/vec4 v0x555555db2c00_0;
|
|
%pad/u 32;
|
|
%cmpi/e 0, 0, 32;
|
|
%jmp/0xz T_16.58, 4;
|
|
%load/vec4 v0x555555dad6f0_0;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 32;
|
|
%muli 8, 0, 32;
|
|
%part/u 8;
|
|
%cmpi/e 120, 0, 8;
|
|
%jmp/0xz T_16.60, 4;
|
|
%pushi/vec4 2, 0, 5;
|
|
%assign/vec4 v0x555555db2b20_0, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555dae8d0_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555dacf50_0, 0;
|
|
%pushi/vec4 0, 0, 6;
|
|
%assign/vec4 v0x555555dad030_0, 0;
|
|
%jmp T_16.61;
|
|
T_16.60 ;
|
|
%pushi/vec4 1, 0, 1;
|
|
%ix/load 5, 0, 0;
|
|
%ix/getv 4, v0x555555daecd0_0;
|
|
%assign/vec4/off/d v0x555555daee90_0, 4, 5;
|
|
%pushi/vec4 3, 0, 2;
|
|
%assign/vec4 v0x555555db2c00_0, 0;
|
|
T_16.61 ;
|
|
T_16.58 ;
|
|
%jmp T_16.52;
|
|
T_16.39 ;
|
|
%pushi/vec4 5, 0, 4;
|
|
%assign/vec4 v0x555555dac390_0, 0;
|
|
%pushi/vec4 3, 0, 5;
|
|
%assign/vec4 v0x555555db2b20_0, 0;
|
|
%pushi/vec4 0, 0, 4;
|
|
%assign/vec4 v0x555555dacd90_0, 0;
|
|
%jmp T_16.52;
|
|
T_16.40 ;
|
|
%load/vec4 v0x555555dac390_0;
|
|
%pad/u 32;
|
|
%cmpi/e 0, 0, 32;
|
|
%jmp/0xz T_16.62, 4;
|
|
%load/vec4 v0x555555dad8b0_0;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 32;
|
|
%muli 8, 0, 32;
|
|
%part/u 8;
|
|
%load/vec4 v0x555555dad110_0;
|
|
%parti/s 32, 8, 5;
|
|
%concat/vec4; draw_concat_vec4
|
|
%assign/vec4 v0x555555dad110_0, 0;
|
|
%load/vec4 v0x555555dacd90_0;
|
|
%addi 1, 0, 4;
|
|
%assign/vec4 v0x555555dacd90_0, 0;
|
|
%load/vec4 v0x555555dacd90_0;
|
|
%pad/u 32;
|
|
%cmpi/e 5, 0, 32;
|
|
%jmp/0xz T_16.64, 4;
|
|
%pushi/vec4 4, 0, 5;
|
|
%assign/vec4 v0x555555db2b20_0, 0;
|
|
%load/vec4 v0x555555dace70_0;
|
|
%assign/vec4 v0x555555dad030_0, 0;
|
|
%pushi/vec4 0, 0, 6;
|
|
%assign/vec4 v0x555555dace70_0, 0;
|
|
T_16.64 ;
|
|
T_16.62 ;
|
|
%jmp T_16.52;
|
|
T_16.41 ;
|
|
%load/vec4 v0x555555dad110_0;
|
|
%load/vec4 v0x555555dace70_0;
|
|
%part/u 10;
|
|
%cmpi/e 340, 0, 10;
|
|
%jmp/0xz T_16.66, 4;
|
|
%load/vec4 v0x555555dace70_0;
|
|
%load/vec4 v0x555555dad030_0;
|
|
%cmp/e;
|
|
%flag_mov 8, 4;
|
|
%jmp/0 T_16.68, 8;
|
|
%load/vec4 v0x555555dacf50_0;
|
|
%pad/u 2;
|
|
%addi 1, 0, 2;
|
|
%jmp/1 T_16.69, 8;
|
|
T_16.68 ; End of true expr.
|
|
%pushi/vec4 0, 0, 2;
|
|
%jmp/0 T_16.69, 8;
|
|
; End of false expr.
|
|
%blend;
|
|
T_16.69;
|
|
%pad/u 1;
|
|
%assign/vec4 v0x555555dacf50_0, 0;
|
|
%load/vec4 v0x555555dacf50_0;
|
|
%pad/u 32;
|
|
%cmpi/e 1, 0, 32;
|
|
%jmp/0xz T_16.70, 4;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555dae8d0_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555dacf50_0, 0;
|
|
%pushi/vec4 5, 0, 5;
|
|
%assign/vec4 v0x555555db2b20_0, 0;
|
|
%jmp T_16.71;
|
|
T_16.70 ;
|
|
%pushi/vec4 2, 0, 5;
|
|
%assign/vec4 v0x555555db2b20_0, 0;
|
|
T_16.71 ;
|
|
%jmp T_16.67;
|
|
T_16.66 ;
|
|
%load/vec4 v0x555555dace70_0;
|
|
%addi 1, 0, 6;
|
|
%assign/vec4 v0x555555dace70_0, 0;
|
|
T_16.67 ;
|
|
%jmp T_16.52;
|
|
T_16.42 ;
|
|
%load/vec4 v0x555555dad030_0;
|
|
%load/vec4 v0x555555dad1f0_0;
|
|
%cmp/e;
|
|
%jmp/0xz T_16.72, 4;
|
|
%load/vec4 v0x555555dacbd0_0;
|
|
%parti/s 3, 3, 3;
|
|
%pad/u 4;
|
|
%pushi/vec4 0, 0, 3;
|
|
%pushi/vec4 5, 0, 32;
|
|
%load/vec4 v0x555555dacbd0_0;
|
|
%parti/s 3, 0, 2;
|
|
%pad/u 32;
|
|
%cmp/u;
|
|
%flag_get/vec4 4;
|
|
%flag_get/vec4 5;
|
|
%or;
|
|
%concat/vec4; draw_concat_vec4
|
|
%add;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 3;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555daace0, 0, 4;
|
|
%pushi/vec4 15420, 0, 16;
|
|
%load/vec4 v0x555555dacbd0_0;
|
|
%parti/s 3, 0, 2;
|
|
%ix/vec4 4;
|
|
%shiftr 4;
|
|
%assign/vec4 v0x555555daccb0_0, 0;
|
|
%pushi/vec4 6, 0, 5;
|
|
%assign/vec4 v0x555555db2b20_0, 0;
|
|
%jmp T_16.73;
|
|
T_16.72 ;
|
|
%pushi/vec4 1, 0, 1;
|
|
%ix/load 5, 0, 0;
|
|
%ix/getv 4, v0x555555daecd0_0;
|
|
%assign/vec4/off/d v0x555555daf470_0, 4, 5;
|
|
%pushi/vec4 1, 0, 1;
|
|
%ix/load 5, 0, 0;
|
|
%ix/getv 4, v0x555555daecd0_0;
|
|
%assign/vec4/off/d v0x555555daf630_0, 4, 5;
|
|
%pushi/vec4 2, 0, 5;
|
|
%assign/vec4 v0x555555db2b20_0, 0;
|
|
T_16.73 ;
|
|
%jmp T_16.52;
|
|
T_16.43 ;
|
|
%load/vec4 v0x555555db2c00_0;
|
|
%pad/u 32;
|
|
%cmpi/e 0, 0, 32;
|
|
%jmp/0xz T_16.74, 4;
|
|
%load/vec4 v0x555555dad6f0_0;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 32;
|
|
%muli 8, 0, 32;
|
|
%part/u 8;
|
|
%load/vec4 v0x555555daccb0_0;
|
|
%parti/s 8, 0, 2;
|
|
%cmp/e;
|
|
%jmp/0xz T_16.76, 4;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 32;
|
|
%cmpi/e 4294967295, 0, 32;
|
|
%jmp/0xz T_16.78, 4;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db0690_0, 0;
|
|
%pushi/vec4 0, 0, 3;
|
|
%assign/vec4 v0x555555daecd0_0, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555db0810_0, 0;
|
|
%pushi/vec4 7, 0, 5;
|
|
%assign/vec4 v0x555555db2b20_0, 0;
|
|
%jmp T_16.79;
|
|
T_16.78 ;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%addi 1, 0, 3;
|
|
%assign/vec4 v0x555555daecd0_0, 0;
|
|
%pushi/vec4 1, 0, 5;
|
|
%assign/vec4 v0x555555db2b20_0, 0;
|
|
T_16.79 ;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555daace0, 4;
|
|
%load/vec4 v0x555555daada0_0;
|
|
%cmp/u;
|
|
%flag_mov 8, 5;
|
|
%jmp/0 T_16.80, 8;
|
|
%load/vec4 v0x555555daada0_0;
|
|
%jmp/1 T_16.81, 8;
|
|
T_16.80 ; End of true expr.
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555daace0, 4;
|
|
%jmp/0 T_16.81, 8;
|
|
; End of false expr.
|
|
%blend;
|
|
T_16.81;
|
|
%assign/vec4 v0x555555daada0_0, 0;
|
|
%jmp T_16.77;
|
|
T_16.76 ;
|
|
%pushi/vec4 1, 0, 1;
|
|
%ix/load 5, 0, 0;
|
|
%ix/getv 4, v0x555555daecd0_0;
|
|
%assign/vec4/off/d v0x555555daee90_0, 4, 5;
|
|
%pushi/vec4 3, 0, 2;
|
|
%assign/vec4 v0x555555db2c00_0, 0;
|
|
T_16.77 ;
|
|
T_16.74 ;
|
|
%jmp T_16.52;
|
|
T_16.44 ;
|
|
%load/vec4 v0x555555daea70_0;
|
|
%pad/u 32;
|
|
%cmpi/e 17, 0, 32;
|
|
%jmp/0xz T_16.82, 4;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555db3e80_0, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555db3f40_0, 0;
|
|
%pushi/vec4 13, 0, 5;
|
|
%assign/vec4 v0x555555dac890_0, 0;
|
|
%pushi/vec4 8, 0, 5;
|
|
%assign/vec4 v0x555555db2b20_0, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555db0690_0, 0;
|
|
T_16.82 ;
|
|
%jmp T_16.52;
|
|
T_16.45 ;
|
|
%load/vec4 v0x555555dac890_0;
|
|
%pad/u 32;
|
|
%cmpi/e 0, 0, 32;
|
|
%jmp/0xz T_16.84, 4;
|
|
%load/vec4 v0x555555dad7d0_0;
|
|
%parti/s 1, 0, 2;
|
|
%assign/vec4 v0x555555db0810_0, 0;
|
|
%load/vec4 v0x555555db0810_0;
|
|
%load/vec4 v0x555555dad7d0_0;
|
|
%parti/s 1, 0, 2;
|
|
%concat/vec4; draw_concat_vec4
|
|
%cmpi/e 1, 0, 2;
|
|
%jmp/0xz T_16.86, 4;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 32;
|
|
%cmpi/e 4294967295, 0, 32;
|
|
%jmp/0xz T_16.88, 4;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db3f40_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db0690_0, 0;
|
|
%pushi/vec4 0, 0, 3;
|
|
%assign/vec4 v0x555555daecd0_0, 0;
|
|
%pushi/vec4 9, 0, 5;
|
|
%assign/vec4 v0x555555db2b20_0, 0;
|
|
%jmp T_16.89;
|
|
T_16.88 ;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%addi 1, 0, 3;
|
|
%assign/vec4 v0x555555daecd0_0, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555db0810_0, 0;
|
|
%pushi/vec4 7, 0, 5;
|
|
%assign/vec4 v0x555555db2b20_0, 0;
|
|
T_16.89 ;
|
|
%jmp T_16.87;
|
|
T_16.86 ;
|
|
%pushi/vec4 1, 0, 1;
|
|
%ix/load 5, 0, 0;
|
|
%ix/getv 4, v0x555555daecd0_0;
|
|
%assign/vec4/off/d v0x555555daf7f0_0, 4, 5;
|
|
%pushi/vec4 1, 0, 1;
|
|
%ix/load 5, 0, 0;
|
|
%ix/getv 4, v0x555555daecd0_0;
|
|
%assign/vec4/off/d v0x555555daf9b0_0, 4, 5;
|
|
%pushi/vec4 7, 0, 5;
|
|
%assign/vec4 v0x555555db2b20_0, 0;
|
|
T_16.87 ;
|
|
T_16.84 ;
|
|
%jmp T_16.52;
|
|
T_16.46 ;
|
|
%load/vec4 v0x555555daea70_0;
|
|
%pad/u 32;
|
|
%cmpi/e 22, 0, 32;
|
|
%flag_get/vec4 4;
|
|
%jmp/0 T_16.92, 4;
|
|
%load/vec4 v0x555555db0450_0;
|
|
%nor/r;
|
|
%and;
|
|
T_16.92;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_16.90, 8;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555db4000_0, 0;
|
|
%pushi/vec4 1, 0, 16;
|
|
%assign/vec4 v0x555555db3b20_0, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555db40c0_0, 0;
|
|
%pushi/vec4 0, 0, 10;
|
|
%assign/vec4 v0x555555db3c00_0, 0;
|
|
%pushi/vec4 2442236305, 0, 32;
|
|
%concati/vec4 2442236305, 0, 32;
|
|
%concati/vec4 4008636142, 0, 33;
|
|
%concati/vec4 4008636142, 0, 32;
|
|
%concati/vec4 2762253476, 0, 33;
|
|
%concati/vec4 2762253478, 0, 32;
|
|
%concati/vec4 3368601800, 0, 34;
|
|
%concati/vec4 3368601805, 0, 32;
|
|
%concati/vec4 3503345872, 0, 36;
|
|
%concati/vec4 3503345837, 0, 32;
|
|
%concati/vec4 2913840557, 0, 32;
|
|
%concati/vec4 2913840465, 0, 32;
|
|
%concati/vec4 2728567458, 0, 33;
|
|
%concati/vec4 2728567683, 0, 32;
|
|
%concati/vec4 2206434179, 0, 32;
|
|
%concati/vec4 4309441, 0, 23;
|
|
%assign/vec4 v0x555555db3ce0_0, 0;
|
|
%pushi/vec4 10, 0, 5;
|
|
%assign/vec4 v0x555555db2b20_0, 0;
|
|
T_16.90 ;
|
|
%jmp T_16.52;
|
|
T_16.47 ;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555db4000_0, 0;
|
|
%pushi/vec4 1, 0, 16;
|
|
%assign/vec4 v0x555555db3b20_0, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555db40c0_0, 0;
|
|
%pushi/vec4 8, 0, 10;
|
|
%assign/vec4 v0x555555db3c00_0, 0;
|
|
%pushi/vec4 2155905152, 0, 32;
|
|
%concati/vec4 2155905152, 0, 32;
|
|
%concati/vec4 3688618971, 0, 32;
|
|
%concati/vec4 3688618971, 0, 32;
|
|
%concati/vec4 3486502863, 0, 32;
|
|
%concati/vec4 3486502863, 0, 32;
|
|
%concati/vec4 3537031890, 0, 32;
|
|
%concati/vec4 3537031890, 0, 32;
|
|
%concati/vec4 3941264106, 0, 33;
|
|
%concati/vec4 3941264107, 0, 32;
|
|
%concati/vec4 3823363043, 0, 32;
|
|
%concati/vec4 3823363042, 0, 32;
|
|
%concati/vec4 2964369584, 0, 33;
|
|
%concati/vec4 2964369584, 0, 32;
|
|
%concati/vec4 4109694196, 0, 32;
|
|
%concati/vec4 1027423549, 0, 30;
|
|
%assign/vec4 v0x555555db3ce0_0, 0;
|
|
%pushi/vec4 11, 0, 5;
|
|
%assign/vec4 v0x555555db2b20_0, 0;
|
|
%jmp T_16.52;
|
|
T_16.48 ;
|
|
%load/vec4 v0x555555db0450_0;
|
|
%nor/r;
|
|
%flag_set/vec4 9;
|
|
%flag_get/vec4 9;
|
|
%jmp/0 T_16.95, 9;
|
|
%load/vec4 v0x555555db4000_0;
|
|
%pad/u 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%cmp/e;
|
|
%flag_get/vec4 4;
|
|
%and;
|
|
T_16.95;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_16.93, 8;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555db4000_0, 0;
|
|
%pushi/vec4 0, 0, 16;
|
|
%assign/vec4 v0x555555db3b20_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db40c0_0, 0;
|
|
%pushi/vec4 12, 0, 5;
|
|
%assign/vec4 v0x555555db2b20_0, 0;
|
|
T_16.93 ;
|
|
%jmp T_16.52;
|
|
T_16.49 ;
|
|
%ix/load 4, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%load/vec4a v0x555555dafe70, 4;
|
|
%cmpi/e 1, 0, 17;
|
|
%jmp/0xz T_16.96, 4;
|
|
%load/vec4 v0x555555db0130_0;
|
|
%assign/vec4 v0x555555db10e0_0, 0;
|
|
%pushi/vec4 13, 0, 5;
|
|
%assign/vec4 v0x555555db2b20_0, 0;
|
|
%pushi/vec4 0, 0, 7;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 3;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dab910, 0, 4;
|
|
%pushi/vec4 2161889234, 0, 32;
|
|
%concati/vec4 3957479547, 0, 33;
|
|
%concati/vec4 2344176742, 0, 34;
|
|
%concati/vec4 279794113, 0, 29;
|
|
%assign/vec4 v0x555555db4740_0, 0;
|
|
T_16.96 ;
|
|
%jmp T_16.52;
|
|
T_16.50 ;
|
|
%load/vec4 v0x555555db4740_0;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dab910, 4;
|
|
%part/u 64;
|
|
%load/vec4 v0x555555db10e0_0;
|
|
%pushi/vec4 448, 0, 32;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 32;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%load/vec4 v0x555555db10e0_0;
|
|
%pushi/vec4 384, 0, 32;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 32;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db10e0_0;
|
|
%pushi/vec4 320, 0, 32;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 32;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db10e0_0;
|
|
%pushi/vec4 256, 0, 32;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 32;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db10e0_0;
|
|
%pushi/vec4 192, 0, 32;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 32;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db10e0_0;
|
|
%pushi/vec4 128, 0, 32;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 32;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db10e0_0;
|
|
%pushi/vec4 64, 0, 32;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 32;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0x555555db10e0_0;
|
|
%pushi/vec4 0, 0, 32;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 32;
|
|
%muli 8, 0, 32;
|
|
%add;
|
|
%part/u 8;
|
|
%concat/vec4; draw_concat_vec4
|
|
%cmp/e;
|
|
%jmp/0xz T_16.98, 4;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 32;
|
|
%cmpi/e 4294967295, 0, 32;
|
|
%jmp/0xz T_16.100, 4;
|
|
%pushi/vec4 14, 0, 5;
|
|
%assign/vec4 v0x555555db2b20_0, 0;
|
|
%jmp T_16.101;
|
|
T_16.100 ;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%addi 1, 0, 3;
|
|
%assign/vec4 v0x555555daecd0_0, 0;
|
|
%pushi/vec4 0, 0, 7;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 32;
|
|
%addi 1, 0, 32;
|
|
%ix/vec4 3;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dab910, 0, 4;
|
|
T_16.101 ;
|
|
%jmp T_16.99;
|
|
T_16.98 ;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dab910, 4;
|
|
%addi 8, 0, 7;
|
|
%load/vec4 v0x555555daecd0_0;
|
|
%pad/u 5;
|
|
%ix/vec4 3;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555dab910, 0, 4;
|
|
T_16.99 ;
|
|
%jmp T_16.52;
|
|
T_16.51 ;
|
|
%pushi/vec4 14, 0, 5;
|
|
%assign/vec4 v0x555555db2b20_0, 0;
|
|
%load/vec4 v0x555555daea70_0;
|
|
%pad/u 32;
|
|
%cmpi/e 19, 0, 32;
|
|
%jmp/0xz T_16.102, 4;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555db0690_0, 0;
|
|
%load/vec4 v0x555555db1ca0_0;
|
|
%nor/r;
|
|
%flag_set/vec4 10;
|
|
%flag_get/vec4 10;
|
|
%jmp/0 T_16.107, 10;
|
|
%load/vec4 v0x555555db2740_0;
|
|
%nor/r;
|
|
%and;
|
|
T_16.107;
|
|
%flag_set/vec4 9;
|
|
%flag_get/vec4 9;
|
|
%jmp/0 T_16.106, 9;
|
|
%load/vec4 v0x555555db02d0_0;
|
|
%and;
|
|
T_16.106;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_16.104, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db0690_0, 0;
|
|
T_16.104 ;
|
|
T_16.102 ;
|
|
%jmp T_16.52;
|
|
T_16.52 ;
|
|
%pop/vec4 1;
|
|
T_16.1 ;
|
|
%jmp T_16;
|
|
.thread T_16;
|
|
.scope S_0x555555cfe490;
|
|
T_17 ;
|
|
%wait E_0x555555cb9a50;
|
|
%load/vec4 v0x555555dad990_0;
|
|
%nor/r;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_17.0, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db3800_0, 0;
|
|
%jmp T_17.1;
|
|
T_17.0 ;
|
|
%load/vec4 v0x555555dadb30_0;
|
|
%flag_set/vec4 9;
|
|
%flag_get/vec4 9;
|
|
%jmp/0 T_17.4, 9;
|
|
%load/vec4 v0x555555dafcf0_0;
|
|
%nor/r;
|
|
%and;
|
|
T_17.4;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_17.2, 8;
|
|
%load/vec4 v0x555555daddb0_0;
|
|
%assign/vec4 v0x555555db3800_0, 0;
|
|
%load/vec4 v0x555555dade70_0;
|
|
%assign/vec4 v0x555555db3980_0, 0;
|
|
%load/vec4 v0x555555dada50_0;
|
|
%assign/vec4 v0x555555db2e60_0, 0;
|
|
%load/vec4 v0x555555dadbf0_0;
|
|
%assign/vec4 v0x555555db2f40_0, 0;
|
|
%load/vec4 v0x555555dadcd0_0;
|
|
%assign/vec4 v0x555555db3720_0, 0;
|
|
%jmp T_17.3;
|
|
T_17.2 ;
|
|
%load/vec4 v0x555555dafcf0_0;
|
|
%nor/r;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_17.5, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db3800_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db3980_0, 0;
|
|
%pushi/vec4 0, 0, 32;
|
|
%assign/vec4 v0x555555db2e60_0, 0;
|
|
%pushi/vec4 0, 0, 32;
|
|
%assign/vec4 v0x555555db2f40_0, 0;
|
|
%pushi/vec4 0, 0, 4;
|
|
%assign/vec4 v0x555555db3720_0, 0;
|
|
T_17.5 ;
|
|
T_17.3 ;
|
|
T_17.1 ;
|
|
%jmp T_17;
|
|
.thread T_17;
|
|
.scope S_0x555555cfe490;
|
|
T_18 ;
|
|
%wait E_0x555555cb9a50;
|
|
%load/vec4 v0x555555dad990_0;
|
|
%nor/r;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_18.0, 8;
|
|
%pushi/vec4 0, 0, 5;
|
|
%assign/vec4 v0x555555db33a0_0, 0;
|
|
%pushi/vec4 0, 0, 8;
|
|
%assign/vec4 v0x555555db3480_0, 0;
|
|
%pushi/vec4 0, 0, 5;
|
|
%assign/vec4 v0x555555db3560_0, 0;
|
|
%pushi/vec4 0, 0, 8;
|
|
%assign/vec4 v0x555555db3640_0, 0;
|
|
%pushi/vec4 0, 0, 5;
|
|
%assign/vec4 v0x555555db3020_0, 0;
|
|
%pushi/vec4 0, 0, 8;
|
|
%assign/vec4 v0x555555db3100_0, 0;
|
|
%pushi/vec4 0, 0, 5;
|
|
%assign/vec4 v0x555555db31e0_0, 0;
|
|
%pushi/vec4 0, 0, 8;
|
|
%assign/vec4 v0x555555db32c0_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db38c0_0, 0;
|
|
%pushi/vec4 0, 0, 3;
|
|
%assign/vec4 v0x555555db3a40_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555dafb50_0, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555dafcf0_0, 0;
|
|
%jmp T_18.1;
|
|
T_18.0 ;
|
|
%pushi/vec4 0, 0, 8;
|
|
%assign/vec4 v0x555555db3480_0, 0;
|
|
%pushi/vec4 0, 0, 8;
|
|
%assign/vec4 v0x555555db3640_0, 0;
|
|
%pushi/vec4 0, 0, 8;
|
|
%assign/vec4 v0x555555db3100_0, 0;
|
|
%pushi/vec4 0, 0, 8;
|
|
%assign/vec4 v0x555555db32c0_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db38c0_0, 0;
|
|
%pushi/vec4 0, 0, 3;
|
|
%assign/vec4 v0x555555db3a40_0, 0;
|
|
%load/vec4 v0x555555db3800_0;
|
|
%flag_set/vec4 8;
|
|
%flag_get/vec4 8;
|
|
%jmp/0 T_18.2, 8;
|
|
%load/vec4 v0x555555dadb30_0;
|
|
%and;
|
|
T_18.2;
|
|
%assign/vec4 v0x555555dafb50_0, 0;
|
|
%load/vec4 v0x555555db2b20_0;
|
|
%pad/u 32;
|
|
%pushi/vec4 14, 0, 32;
|
|
%cmp/ne;
|
|
%flag_get/vec4 4;
|
|
%assign/vec4 v0x555555dafcf0_0, 0;
|
|
%load/vec4 v0x555555db3800_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_18.3, 8;
|
|
%load/vec4 v0x555555db2e60_0;
|
|
%parti/s 4, 0, 2;
|
|
%dup/vec4;
|
|
%pushi/vec4 0, 0, 4;
|
|
%cmp/u;
|
|
%jmp/1 T_18.5, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 1, 0, 4;
|
|
%cmp/u;
|
|
%jmp/1 T_18.6, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 2, 0, 4;
|
|
%cmp/u;
|
|
%jmp/1 T_18.7, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 3, 0, 4;
|
|
%cmp/u;
|
|
%jmp/1 T_18.8, 6;
|
|
%load/vec4 v0x555555db3980_0;
|
|
%nor/r;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_18.11, 8;
|
|
%pushi/vec4 2863311530, 0, 32;
|
|
%assign/vec4 v0x555555dafc10_0, 0;
|
|
T_18.11 ;
|
|
%jmp T_18.10;
|
|
T_18.5 ;
|
|
%load/vec4 v0x555555db3980_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_18.13, 8;
|
|
%load/vec4 v0x555555db2f40_0;
|
|
%parti/s 5, 0, 2;
|
|
%assign/vec4 v0x555555db33a0_0, 0;
|
|
%pushi/vec4 1, 0, 8;
|
|
%load/vec4 v0x555555db2f40_0;
|
|
%parti/s 3, 5, 4;
|
|
%ix/vec4 4;
|
|
%shiftl 4;
|
|
%assign/vec4 v0x555555db3480_0, 0;
|
|
%load/vec4 v0x555555db3720_0;
|
|
%parti/s 1, 0, 2;
|
|
%assign/vec4 v0x555555db38c0_0, 0;
|
|
%jmp T_18.14;
|
|
T_18.13 ;
|
|
%pushi/vec4 0, 0, 27;
|
|
%load/vec4 v0x555555db2e60_0;
|
|
%parti/s 3, 4, 4;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555db0510, 4;
|
|
%concat/vec4; draw_concat_vec4
|
|
%assign/vec4 v0x555555dafc10_0, 0;
|
|
T_18.14 ;
|
|
%jmp T_18.10;
|
|
T_18.6 ;
|
|
%load/vec4 v0x555555db3980_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_18.15, 8;
|
|
%load/vec4 v0x555555db2f40_0;
|
|
%parti/s 5, 0, 2;
|
|
%assign/vec4 v0x555555db3560_0, 0;
|
|
%pushi/vec4 1, 0, 8;
|
|
%load/vec4 v0x555555db2f40_0;
|
|
%parti/s 3, 5, 4;
|
|
%ix/vec4 4;
|
|
%shiftl 4;
|
|
%assign/vec4 v0x555555db3640_0, 0;
|
|
%load/vec4 v0x555555db3720_0;
|
|
%parti/s 1, 0, 2;
|
|
%assign/vec4 v0x555555db38c0_0, 0;
|
|
%jmp T_18.16;
|
|
T_18.15 ;
|
|
%pushi/vec4 0, 0, 27;
|
|
%load/vec4 v0x555555db2e60_0;
|
|
%parti/s 3, 4, 4;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555db05d0, 4;
|
|
%concat/vec4; draw_concat_vec4
|
|
%assign/vec4 v0x555555dafc10_0, 0;
|
|
T_18.16 ;
|
|
%jmp T_18.10;
|
|
T_18.7 ;
|
|
%load/vec4 v0x555555db3980_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_18.17, 8;
|
|
%load/vec4 v0x555555db2f40_0;
|
|
%parti/s 5, 0, 2;
|
|
%assign/vec4 v0x555555db3020_0, 0;
|
|
%pushi/vec4 1, 0, 8;
|
|
%load/vec4 v0x555555db2f40_0;
|
|
%parti/s 3, 5, 4;
|
|
%ix/vec4 4;
|
|
%shiftl 4;
|
|
%assign/vec4 v0x555555db3100_0, 0;
|
|
%load/vec4 v0x555555db3720_0;
|
|
%parti/s 1, 0, 2;
|
|
%assign/vec4 v0x555555db38c0_0, 0;
|
|
%jmp T_18.18;
|
|
T_18.17 ;
|
|
%pushi/vec4 0, 0, 27;
|
|
%load/vec4 v0x555555db2e60_0;
|
|
%parti/s 3, 4, 4;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dae410, 4;
|
|
%concat/vec4; draw_concat_vec4
|
|
%assign/vec4 v0x555555dafc10_0, 0;
|
|
T_18.18 ;
|
|
%jmp T_18.10;
|
|
T_18.8 ;
|
|
%load/vec4 v0x555555db3980_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_18.19, 8;
|
|
%load/vec4 v0x555555db2f40_0;
|
|
%parti/s 5, 0, 2;
|
|
%assign/vec4 v0x555555db31e0_0, 0;
|
|
%pushi/vec4 1, 0, 8;
|
|
%load/vec4 v0x555555db2f40_0;
|
|
%parti/s 3, 5, 4;
|
|
%ix/vec4 4;
|
|
%shiftl 4;
|
|
%assign/vec4 v0x555555db32c0_0, 0;
|
|
%load/vec4 v0x555555db3720_0;
|
|
%parti/s 1, 0, 2;
|
|
%assign/vec4 v0x555555db38c0_0, 0;
|
|
%jmp T_18.20;
|
|
T_18.19 ;
|
|
%pushi/vec4 0, 0, 27;
|
|
%load/vec4 v0x555555db2e60_0;
|
|
%parti/s 3, 4, 4;
|
|
%pad/u 5;
|
|
%ix/vec4 4;
|
|
%load/vec4a v0x555555dae5b0, 4;
|
|
%concat/vec4; draw_concat_vec4
|
|
%assign/vec4 v0x555555dafc10_0, 0;
|
|
T_18.20 ;
|
|
%jmp T_18.10;
|
|
T_18.10 ;
|
|
%pop/vec4 1;
|
|
%load/vec4 v0x555555db2f40_0;
|
|
%parti/s 3, 5, 4;
|
|
%assign/vec4 v0x555555db3a40_0, 0;
|
|
T_18.3 ;
|
|
T_18.1 ;
|
|
%jmp T_18;
|
|
.thread T_18;
|
|
.scope S_0x555555cfe490;
|
|
T_19 ;
|
|
%vpi_call 2 1786 "$display", "TEST FUNCTIONS\012-----------------------------\012" {0 0 0};
|
|
%vpi_call 2 1787 "$display", "Test ns_to_cycles() function:" {0 0 0};
|
|
%pushi/vec4 15, 0, 32;
|
|
%store/vec4 v0x555555da86c0_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.ns_to_cycles, S_0x555555da84e0;
|
|
%vpi_call 2 1788 "$display", "\011ns_to_cycles(15) = %0d [exact]", S<0,vec4,u19> {1 0 0};
|
|
%pushi/vec4 15, 0, 32;
|
|
%store/vec4 v0x555555da86c0_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.ns_to_cycles, S_0x555555da84e0;
|
|
%vpi_call 2 1789 "$display", "\011ns_to_cycles(14.5) = %0d [round-off]", S<0,vec4,u19> {1 0 0};
|
|
%pushi/vec4 11, 0, 32;
|
|
%store/vec4 v0x555555da86c0_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.ns_to_cycles, S_0x555555da84e0;
|
|
%vpi_call 2 1790 "$display", "\011ns_to_cycles(11) = %0d [round-up]\012", S<0,vec4,u19> {1 0 0};
|
|
%vpi_call 2 1792 "$display", "Test nCK_to_cycles() function:" {0 0 0};
|
|
%pushi/vec4 16, 0, 32;
|
|
%store/vec4 v0x555555da7e80_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.nCK_to_cycles, S_0x555555da7ca0;
|
|
%vpi_call 2 1793 "$display", "\011ns_to_cycles(16) = %0d [exact]", S<0,vec4,u19> {1 0 0};
|
|
%pushi/vec4 15, 0, 32;
|
|
%store/vec4 v0x555555da7e80_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.nCK_to_cycles, S_0x555555da7ca0;
|
|
%vpi_call 2 1794 "$display", "\011ns_to_cycles(15) = %0d [round-off]", S<0,vec4,u19> {1 0 0};
|
|
%pushi/vec4 13, 0, 32;
|
|
%store/vec4 v0x555555da7e80_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.nCK_to_cycles, S_0x555555da7ca0;
|
|
%vpi_call 2 1795 "$display", "\011ns_to_cycles(13) = %0d [round-up]\012", S<0,vec4,u19> {1 0 0};
|
|
%vpi_call 2 1797 "$display", "Test ns_to_nCK() function:" {0 0 0};
|
|
%pushi/vec4 15, 0, 32;
|
|
%store/vec4 v0x555555da8bd0_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.ns_to_nCK, S_0x555555da8960;
|
|
%vpi_call 2 1798 "$display", "\011ns_to_cycles(15) = %0d [exact]", S<0,vec4,s32> {1 0 0};
|
|
%pushi/vec4 15, 0, 32;
|
|
%store/vec4 v0x555555da8bd0_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.ns_to_nCK, S_0x555555da8960;
|
|
%vpi_call 2 1799 "$display", "\011ns_to_cycles(14.875) = %0d [round-off]", S<0,vec4,s32> {1 0 0};
|
|
%pushi/vec4 14, 0, 32;
|
|
%store/vec4 v0x555555da8bd0_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.ns_to_nCK, S_0x555555da8960;
|
|
%vpi_call 2 1800 "$display", "\011ns_to_cycles(13.875) = %0d [round-up] \012", S<0,vec4,s32> {1 0 0};
|
|
%vpi_call 2 1802 "$display", "Test nCK_to_ns() function:" {0 0 0};
|
|
%pushi/vec4 4, 0, 32;
|
|
%store/vec4 v0x555555da8300_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.nCK_to_ns, S_0x555555da8120;
|
|
%vpi_call 2 1803 "$display", "\011ns_to_cycles(4) = %0d [exact]", S<0,vec4,s32> {1 0 0};
|
|
%pushi/vec4 3, 0, 32;
|
|
%store/vec4 v0x555555da8300_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.nCK_to_ns, S_0x555555da8120;
|
|
%vpi_call 2 1804 "$display", "\011ns_to_cycles(14.875) = %0d [round-off]", S<0,vec4,s32> {1 0 0};
|
|
%pushi/vec4 5, 0, 32;
|
|
%store/vec4 v0x555555da8300_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.nCK_to_ns, S_0x555555da8120;
|
|
%vpi_call 2 1805 "$display", "\011ns_to_cycles(13.875) = %0d [round-up]\012", S<0,vec4,s32> {1 0 0};
|
|
%vpi_call 2 1807 "$display", "Test nCK_to_ns() function:" {0 0 0};
|
|
%pushi/vec4 4, 0, 32;
|
|
%store/vec4 v0x555555da8300_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.nCK_to_ns, S_0x555555da8120;
|
|
%vpi_call 2 1808 "$display", "\011ns_to_cycles(4) = %0d [exact]", S<0,vec4,s32> {1 0 0};
|
|
%pushi/vec4 3, 0, 32;
|
|
%store/vec4 v0x555555da8300_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.nCK_to_ns, S_0x555555da8120;
|
|
%vpi_call 2 1809 "$display", "\011ns_to_cycles(14.875) = %0d [round-off]", S<0,vec4,s32> {1 0 0};
|
|
%pushi/vec4 5, 0, 32;
|
|
%store/vec4 v0x555555da8300_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.nCK_to_ns, S_0x555555da8120;
|
|
%vpi_call 2 1810 "$display", "\011ns_to_cycles(13.875) = %0d [round-up]\012", S<0,vec4,s32> {1 0 0};
|
|
%vpi_call 2 1812 "$display", "Test $floor() function:" {0 0 0};
|
|
%pushi/real 1073741824, 4067; load=2.00000
|
|
%vpi_call 2 1813 "$display", "\011$floor(5/2) = %0d", W<0,r> {0 1 0};
|
|
%pushi/real 1073741824, 4067; load=2.00000
|
|
%vpi_call 2 1814 "$display", "\011$floor(9/4) = %0d", W<0,r> {0 1 0};
|
|
%pushi/real 1073741824, 4067; load=2.00000
|
|
%vpi_call 2 1815 "$display", "\011$floor(9/4) = %0d", W<0,r> {0 1 0};
|
|
%pushi/real 1073741824, 4066; load=1.00000
|
|
%vpi_call 2 1816 "$display", "\011$floor(9/5) = %0d\012", W<0,r> {0 1 0};
|
|
%vpi_call 2 1818 "$display", "\012DISPLAY CONTROLLER PARAMETERS\012-----------------------------\012" {0 0 0};
|
|
%vpi_call 2 1819 "$display", "DELAY_COUNTER_WIDTH = %0d", P_0x555555d8dee0 {0 0 0};
|
|
%vpi_call 2 1820 "$display", "DELAY_SLOT_WIDTH = %0d", P_0x555555d8df60 {0 0 0};
|
|
%vpi_call 2 1823 "$display", "serdes_ratio = %0d", P_0x555555d8f1e0 {0 0 0};
|
|
%vpi_call 2 1824 "$display", "wb_addr_bits = %0d", P_0x555555d8f660 {0 0 0};
|
|
%vpi_call 2 1825 "$display", "wb_data_bits = %0d", P_0x555555d8f6a0 {0 0 0};
|
|
%vpi_call 2 1826 "$display", "wb_sel_bits = %0d\012\012", P_0x555555d8f6e0 {0 0 0};
|
|
%vpi_call 2 1831 "$display", "READ_SLOT = %0d", P_0x555555d8eae0 {0 0 0};
|
|
%vpi_call 2 1832 "$display", "WRITE_SLOT = %0d", P_0x555555d8f0a0 {0 0 0};
|
|
%vpi_call 2 1833 "$display", "ACTIVATE_SLOT = %0d", P_0x555555d8d320 {0 0 0};
|
|
%vpi_call 2 1834 "$display", "PRECHARGE_SLOT = %0d", P_0x555555d8e8e0 {0 0 0};
|
|
%vpi_call 2 1836 "$display", "\012\012DELAYS:" {0 0 0};
|
|
%pushi/vec4 14, 0, 32;
|
|
%store/vec4 v0x555555da8bd0_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.ns_to_nCK, S_0x555555da8960;
|
|
%vpi_call 2 1837 "$display", "\011ns_to_nCK(tRCD): %0d", S<0,vec4,s32> {1 0 0};
|
|
%pushi/vec4 14, 0, 32;
|
|
%store/vec4 v0x555555da8bd0_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.ns_to_nCK, S_0x555555da8960;
|
|
%vpi_call 2 1838 "$display", "\011ns_to_nCK(tRP): %0d", S<0,vec4,s32> {1 0 0};
|
|
%pushi/vec4 10, 0, 32;
|
|
%store/vec4 v0x555555da8bd0_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.ns_to_nCK, S_0x555555da8960;
|
|
%vpi_call 2 1839 "$display", "\011ns_to_nCK(tRTP): %0d", S<0,vec4,s32> {1 0 0};
|
|
%vpi_call 2 1840 "$display", "\011tCCD: %0d", P_0x555555d8f220 {0 0 0};
|
|
%vpi_call 2 1841 "$display", "\011(CL_nCK + tCCD + 2 - CWL_nCK): %0d", 32'sb00000000000000000000000000000111 {0 0 0};
|
|
%pushi/vec4 9, 0, 32;
|
|
%pushi/vec4 15, 0, 32;
|
|
%store/vec4 v0x555555da8bd0_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.ns_to_nCK, S_0x555555da8960;
|
|
%add;
|
|
%vpi_call 2 1842 "$display", "\011(CWL_nCK + 4 + ns_to_nCK(tWR)): %0d", S<0,vec4,s32> {1 0 0};
|
|
%pushi/vec4 9, 0, 32;
|
|
%pushi/vec4 10, 0, 32;
|
|
%store/vec4 v0x555555da8bd0_0, 0, 32;
|
|
%callf/vec4 TD_ddr3_controller.ns_to_nCK, S_0x555555da8960;
|
|
%add;
|
|
%vpi_call 2 1843 "$display", "\011(CWL_nCK + 4 + ns_to_nCK(tWTR)): %0d", S<0,vec4,s32> {1 0 0};
|
|
%vpi_call 2 1845 "$display", "\012\012PRECHARGE_TO_ACTIVATE_DELAY = %0d", P_0x555555d8e920 {0 0 0};
|
|
%vpi_call 2 1846 "$display", "ACTIVATE_TO_WRITE_DELAY = %0d", P_0x555555d8d3e0 {0 0 0};
|
|
%vpi_call 2 1847 "$display", "ACTIVATE_TO_READ_DELAY = %0d", P_0x555555d8d3a0 {0 0 0};
|
|
%vpi_call 2 1848 "$display", "READ_TO_WRITE_DELAY = %0d", P_0x555555d8eba0 {0 0 0};
|
|
%vpi_call 2 1849 "$display", "READ_TO_READ_DELAY = %0d", P_0x555555d8eb60 {0 0 0};
|
|
%vpi_call 2 1850 "$display", "READ_TO_PRECHARGE_DELAY = %0d", P_0x555555d8eb20 {0 0 0};
|
|
%vpi_call 2 1851 "$display", "WRITE_TO_WRITE_DELAY = %0d", P_0x555555d8f160 {0 0 0};
|
|
%vpi_call 2 1852 "$display", "WRITE_TO_READ_DELAY = %0d", P_0x555555d8f120 {0 0 0};
|
|
%vpi_call 2 1853 "$display", "WRITE_TO_PRECHARGE_DELAY = %0d", P_0x555555d8f0e0 {0 0 0};
|
|
%vpi_call 2 1854 "$display", "STAGE2_DATA_DEPTH = %0d", P_0x555555d8ede0 {0 0 0};
|
|
%vpi_call 2 1855 "$display", "READ_ACK_PIPE_WIDTH = %0d", P_0x555555d8ea20 {0 0 0};
|
|
%end;
|
|
.thread T_19;
|
|
.scope S_0x555555d02bb0;
|
|
T_20 ;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db5d50_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db5ad0_0, 0, 1;
|
|
%end;
|
|
.thread T_20;
|
|
.scope S_0x555555d02bb0;
|
|
T_21 ;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0x555555db5400_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0x555555db5610_0, 0, 1;
|
|
%end;
|
|
.thread T_21;
|
|
.scope S_0x555555d02bb0;
|
|
T_22 ;
|
|
%wait E_0x555555d8c690;
|
|
%load/vec4 v0x555555db5790_0;
|
|
%nor/r;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_22.0, 8;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555db5400_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db5610_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db5ad0_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db5d50_0, 0;
|
|
%jmp T_22.1;
|
|
T_22.0 ;
|
|
%load/vec4 v0x555555db5a10_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_22.2, 8;
|
|
%load/vec4 v0x555555db5c90_0;
|
|
%nor/r;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_22.4, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db5610_0, 0;
|
|
T_22.4 ;
|
|
%load/vec4 v0x555555db5ad0_0;
|
|
%pad/u 2;
|
|
%addi 1, 0, 2;
|
|
%pad/u 1;
|
|
%assign/vec4 v0x555555db5ad0_0, 0;
|
|
%load/vec4 v0x555555db5ad0_0;
|
|
%addi 1, 0, 1;
|
|
%load/vec4 v0x555555db5d50_0;
|
|
%cmp/e;
|
|
%flag_get/vec4 4;
|
|
%jmp/0 T_22.8, 4;
|
|
%load/vec4 v0x555555db5c90_0;
|
|
%nor/r;
|
|
%and;
|
|
T_22.8;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_22.6, 8;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555db5400_0, 0;
|
|
T_22.6 ;
|
|
T_22.2 ;
|
|
%load/vec4 v0x555555db5c90_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_22.9, 8;
|
|
%load/vec4 v0x555555db5a10_0;
|
|
%nor/r;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_22.11, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0x555555db5400_0, 0;
|
|
T_22.11 ;
|
|
%load/vec4 v0x555555db5bb0_0;
|
|
%load/vec4 v0x555555db5d50_0;
|
|
%pad/u 3;
|
|
%ix/vec4 3;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0x555555db54c0, 0, 4;
|
|
%load/vec4 v0x555555db5d50_0;
|
|
%pad/u 2;
|
|
%addi 1, 0, 2;
|
|
%pad/u 1;
|
|
%assign/vec4 v0x555555db5d50_0, 0;
|
|
%load/vec4 v0x555555db5d50_0;
|
|
%addi 1, 0, 1;
|
|
%load/vec4 v0x555555db5ad0_0;
|
|
%cmp/e;
|
|
%flag_get/vec4 4;
|
|
%jmp/0 T_22.15, 4;
|
|
%load/vec4 v0x555555db5a10_0;
|
|
%nor/r;
|
|
%and;
|
|
T_22.15;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_22.13, 8;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0x555555db5610_0, 0;
|
|
T_22.13 ;
|
|
T_22.9 ;
|
|
T_22.1 ;
|
|
%jmp T_22;
|
|
.thread T_22;
|
|
# The file index is used to find the file name in the following table.
|
|
:file_names 3;
|
|
"N/A";
|
|
"<interactive>";
|
|
"rtl/ddr3_controller.v";
|