161 lines
3.6 KiB
Plaintext
161 lines
3.6 KiB
Plaintext
[*]
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[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
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[*] Tue Jul 11 12:39:11 2023
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[*]
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[timestart] 0
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[size] 1848 1126
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[pos] -1 -1
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*-4.757294 10 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] ddr3_controller.
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[sst_width] 297
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[signals_width] 395
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[sst_expanded] 1
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[sst_vpaned_height] 743
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@28
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ddr3_controller.i_controller_clk
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ddr3_controller.i_rst_n
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@24
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ddr3_controller.state_calibrate[4:0]
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@200
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-
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@28
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ddr3_controller.wb2_properties.i_wb_cyc
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@22
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ddr3_controller.wb2_properties.f_nacks[3:0]
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ddr3_controller.wb2_properties.f_nreqs[3:0]
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ddr3_controller.wb2_properties.f_outstanding[3:0]
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ddr3_controller.f_outstanding_2[3:0]
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@200
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-
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-
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@28
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ddr3_controller.i_wb2_addr[31:0]
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[color] 2
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ddr3_controller.i_wb2_cyc
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ddr3_controller.i_wb2_data[31:0]
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[color] 2
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ddr3_controller.i_wb2_stb
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[color] 2
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ddr3_controller.i_wb2_we
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[color] 2
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ddr3_controller.o_wb2_ack
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ddr3_controller.o_wb2_data[31:0]
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ddr3_controller.o_wb2_stall
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@200
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-
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@28
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[color] 4
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ddr3_controller.f_delay_ld[7:0]
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[color] 4
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ddr3_controller.o_phy_idelay_data_ld[7:0]
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[color] 4
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ddr3_controller.o_phy_idelay_dqs_ld[7:0]
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[color] 4
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ddr3_controller.o_phy_odelay_data_ld[7:0]
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[color] 4
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ddr3_controller.o_phy_odelay_dqs_ld[7:0]
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ddr3_controller.o_phy_idelay_data_cntvaluein[4:0]
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ddr3_controller.o_phy_idelay_dqs_cntvaluein[4:0]
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ddr3_controller.o_phy_odelay_data_cntvaluein[4:0]
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ddr3_controller.o_phy_odelay_dqs_cntvaluein[4:0]
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@200
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-
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@22
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ddr3_controller.odelay_data_cntvaluein<0>[4:0]
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ddr3_controller.odelay_data_cntvaluein<1>[4:0]
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ddr3_controller.odelay_data_cntvaluein<2>[4:0]
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ddr3_controller.odelay_data_cntvaluein<3>[4:0]
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ddr3_controller.odelay_data_cntvaluein<4>[4:0]
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ddr3_controller.odelay_data_cntvaluein<5>[4:0]
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@28
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ddr3_controller.odelay_data_cntvaluein<6>[4:0]
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@22
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ddr3_controller.odelay_data_cntvaluein<7>[4:0]
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@200
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-
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@28
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[color] 4
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ddr3_controller.wb2_addr[31:0]
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[color] 4
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ddr3_controller.wb2_data[31:0]
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@22
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[color] 4
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ddr3_controller.wb2_phy_idelay_data_cntvaluein[4:0]
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@28
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[color] 4
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ddr3_controller.wb2_phy_idelay_data_ld[7:0]
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@22
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[color] 4
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ddr3_controller.wb2_phy_idelay_dqs_cntvaluein[4:0]
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@c00028
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[color] 4
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ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
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@28
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(0)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
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(1)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
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(2)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
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(3)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
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(4)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
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(5)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
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(6)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
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(7)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
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@1401200
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-group_end
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@22
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[color] 4
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ddr3_controller.wb2_phy_odelay_data_cntvaluein[4:0]
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@28
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[color] 4
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ddr3_controller.wb2_phy_odelay_data_ld[7:0]
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@c00028
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[color] 4
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ddr3_controller.f_delay_ld[7:0]
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@28
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(0)ddr3_controller.f_delay_ld[7:0]
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(1)ddr3_controller.f_delay_ld[7:0]
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(2)ddr3_controller.f_delay_ld[7:0]
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(3)ddr3_controller.f_delay_ld[7:0]
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(4)ddr3_controller.f_delay_ld[7:0]
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(5)ddr3_controller.f_delay_ld[7:0]
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(6)ddr3_controller.f_delay_ld[7:0]
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(7)ddr3_controller.f_delay_ld[7:0]
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@1401200
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-group_end
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@22
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[color] 4
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ddr3_controller.wb2_phy_odelay_dqs_cntvaluein[4:0]
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@28
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[color] 4
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ddr3_controller.wb2_phy_odelay_dqs_ld[7:0]
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[color] 2
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ddr3_controller.wb2_stb
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[color] 4
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ddr3_controller.wb2_update
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[color] 2
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ddr3_controller.wb2_we
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[color] 4
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ddr3_controller.wb2_write_lane[2:0]
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[color] 2
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ddr3_controller.f_o_wb2_ack_q
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ddr3_controller.f_read_data_2[12:0]
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ddr3_controller.f_read_data_2_q[12:0]
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@200
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-
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@28
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ddr3_controller.fifo_2.read_fifo
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ddr3_controller.f_read_fifo_2
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[color] 2
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ddr3_controller.fifo_2.write_fifo
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[color] 2
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ddr3_controller.fifo_2.empty
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[color] 2
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ddr3_controller.fifo_2.full
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@29
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ddr3_controller.f_full_2
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@28
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ddr3_controller.fifo_2.read_pointer
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ddr3_controller.fifo_2.write_pointer
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[pattern_trace] 1
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[pattern_trace] 0
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