67 lines
1.9 KiB
Verilog
67 lines
1.9 KiB
Verilog
`timescale 1ps/1ps
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module clk_wiz
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(
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input wire clk_in1,
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output wire clk_out1,
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output wire clk_out2,
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output wire clk_out3,
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output wire clk_out4,
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input wire reset,
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output wire locked
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);
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wire clk_out1_clk_wiz_0;
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wire clk_out2_clk_wiz_0;
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wire clk_out3_clk_wiz_0;
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wire clk_out4_clk_wiz_0;
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wire clkfbout;
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PLLE2_ADV
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#(.BANDWIDTH ("OPTIMIZED"),
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.COMPENSATION ("INTERNAL"),
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.STARTUP_WAIT ("FALSE"),
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.DIVCLK_DIVIDE (1),
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.CLKFBOUT_MULT (20), // 50 MHz * 20 = 1000 MHz
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.CLKFBOUT_PHASE (0.000),
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.CLKOUT0_DIVIDE (12), // 1000 MHz / 12 = 83.333 MHz
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.CLKOUT0_PHASE (0.000),
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.CLKOUT0_DUTY_CYCLE (0.500),
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.CLKOUT1_DIVIDE (3), // 1000 MHz / 3 = 333.333 MHz
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.CLKOUT1_PHASE (0.000),
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.CLKOUT1_DUTY_CYCLE (0.500),
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.CLKOUT2_DIVIDE (5), // 1000 MHz / 5 = 200 MHz
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.CLKOUT2_PHASE (0.000),
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.CLKOUT2_DUTY_CYCLE (0.500),
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.CLKOUT3_DIVIDE (3), // 1000 MHz / 3 = 333.333 MHz, 90 phase
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.CLKOUT3_PHASE (90.000),
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.CLKOUT3_DUTY_CYCLE (0.500),
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.CLKIN1_PERIOD (20.000) // 50 MHz input
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)
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plle2_adv_inst
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(
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.CLKFBOUT (clkfbout),
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.CLKOUT0 (clk_out1_clk_wiz_0),
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.CLKOUT1 (clk_out2_clk_wiz_0),
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.CLKOUT2 (clk_out3_clk_wiz_0),
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.CLKOUT3 (clk_out4_clk_wiz_0),
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.CLKFBIN (clkfbout),
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.CLKIN1 (clk_in1),
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.LOCKED (locked),
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.RST (reset)
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);
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BUFG clkout1_buf
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(.O (clk_out1),
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.I (clk_out1_clk_wiz_0));
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BUFG clkout2_buf
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(.O (clk_out2),
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.I (clk_out2_clk_wiz_0));
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BUFG clkout3_buf
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(.O (clk_out3),
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.I (clk_out3_clk_wiz_0));
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BUFG clkout4_buf
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(.O (clk_out4),
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.I (clk_out4_clk_wiz_0));
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endmodule
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