114 lines
3.4 KiB
Verilog
114 lines
3.4 KiB
Verilog
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: ddr3_test_top.v
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// Project: Testbench for ddr3_test_top.v
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//
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// Engineer: Angelo C. Jacobo
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2023-2025 Angelo Jacobo
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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//
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////////////////////////////////////////////////////////////////////////////////
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`timescale 1ps / 1ps
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module ddr3_test_top_tb;
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// PHY Interface to DDR3 Device
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wire[1:0] ddr3_cke; // CKE
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wire[1:0] ddr3_cs_n; // chip select signal
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wire[1:0] ddr3_odt; // on-die termination
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wire ddr3_ras_n; // RAS#
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wire ddr3_cas_n; // CAS#
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wire ddr3_we_n; // WE#
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wire ddr3_reset_n;
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wire[$bits(DUT.ddr3_addr)-1:0] ddr3_addr;
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wire[$bits(DUT.ddr3_ba)-1:0] ddr3_ba;
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wire[$bits(DUT.ddr3_dm)-1:0] ddr3_dm;
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wire[$bits(DUT.ddr3_dq)-1:0] ddr3_dq;
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wire[$bits(DUT.ddr3_dqs_p)-1:0] ddr3_dqs_p;
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wire[$bits(DUT.ddr3_dqs_n)-1:0] ddr3_dqs_n;
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wire[1:0] ddr3_clk_p, ddr3_clk_n;
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// clocks and reset
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reg i_clk200_p;
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reg i_rst_n;
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initial begin
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i_clk200_p = 0;
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i_rst_n = 0;
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#1000;
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i_rst_n = 1;
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end
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always #2_500 i_clk200_p = !i_clk200_p; // 200MHz
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enclustra_ddr3_test #(
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.MICRON_SIM(1),
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.ODELAY_SUPPORTED(1),
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.DATA_MASK(1)
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)
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DUT (
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.i_clk200_p(i_clk200_p),
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.i_clk200_n(!i_clk200_p),
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.i_rst_n(i_rst_n),
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// DDR3 I/O Interface
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.ddr3_clk_p(ddr3_clk_p),
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.ddr3_clk_n(ddr3_clk_n),
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.ddr3_reset_n(ddr3_reset_n),
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.ddr3_cke(ddr3_cke),
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.ddr3_cs_n(ddr3_cs_n),
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.ddr3_ras_n(ddr3_ras_n),
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.ddr3_cas_n(ddr3_cas_n),
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.ddr3_we_n(ddr3_we_n),
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.ddr3_addr(ddr3_addr),
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.ddr3_ba(ddr3_ba),
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.ddr3_dq(ddr3_dq),
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.ddr3_dqs_p(ddr3_dqs_p),
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.ddr3_dqs_n(ddr3_dqs_n),
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.ddr3_dm(ddr3_dm),
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.ddr3_odt(ddr3_odt),
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// UART line
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.rx(0),
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.tx(),
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// Debug LEDs
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.led()
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);
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// DDR3 Device
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ddr3_module ddr3_module(
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.reset_n(ddr3_reset_n),
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.ck(ddr3_clk_p), //[1:0]
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.ck_n(ddr3_clk_n), //[1:0]
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.cke(ddr3_cke), //[1:0]
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.s_n(ddr3_cs_n), //[1:0]
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.ras_n(ddr3_ras_n),
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.cas_n(ddr3_cas_n),
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.we_n(ddr3_we_n),
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.ba(ddr3_ba),
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.addr({0,ddr3_addr}),
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.odt(ddr3_odt), //[1:0]
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.dqs({ddr3_dm[0], ddr3_dm,ddr3_dm[0],ddr3_dqs_p}), //ddr3_module uses last 8 MSB [16:9] as datamask
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.dqs_n(ddr3_dqs_n),
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.dq(ddr3_dq)
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);
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assign ddr3_cke[1]=0,
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ddr3_cs_n[1]=1,
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ddr3_odt[1]=0,
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ddr3_clk_p[1]=0,
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ddr3_clk_n[1]=0;
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endmodule
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