221 lines
9.3 KiB
Verilog
221 lines
9.3 KiB
Verilog
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: ddr3_test_top.v
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// Project: Top level module instantiating the ddr3 test and UberDDR3.
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//
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// Engineer: Angelo C. Jacobo
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2023-2025 Angelo Jacobo
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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//
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////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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module enclustra_ddr3_test
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(
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input wire i_clk200_p, i_clk200_n,
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input wire i_rst_n,
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// DDR3 I/O Interface
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output wire ddr3_clk_p, ddr3_clk_n,
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output wire ddr3_reset_n,
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output wire ddr3_cke,
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output wire ddr3_cs_n,
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output wire ddr3_ras_n,
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output wire ddr3_cas_n,
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output wire ddr3_we_n,
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output wire[15-1:0] ddr3_addr,
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output wire[3-1:0] ddr3_ba,
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inout wire[64-1:0] ddr3_dq,
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inout wire[8-1:0] ddr3_dqs_p, ddr3_dqs_n,
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output wire[8-1:0] ddr3_dm,
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output wire ddr3_odt,
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// UART line
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input wire rx,
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output wire tx,
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//Debug LEDs
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output wire[3:0] led,
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// Button for fault injection
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input wire btn
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);
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localparam CONTROLLER_CLK_PERIOD = 5_000, // ps, clock period of the controller interface
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DDR3_CLK_PERIOD = 1_250, // ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
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ROW_BITS = 15, // Width of row address
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COL_BITS = 10, // Width of column address
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BA_BITS = 3, // Width of bank address
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BYTE_LANES = 8, // Number of DDR3 modules to be controlled
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AUX_WIDTH = 16, // Width of aux line (must be >= 4)
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BIST_MODE = 0; // Don't perform BIST, go straight to external DDR3 test
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parameter MICRON_SIM = 0, // Enable faster simulation for Micron DDR3 model
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ODELAY_SUPPORTED = 1, // Set to 1 when ODELAYE2 is supported
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DATA_MASK = 1; // enable test on datamask
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localparam WB_ADDR_BITS = ROW_BITS + COL_BITS + BA_BITS - 3,
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WB_DATA_BITS = 8*BYTE_LANES*8,
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WB_SEL_BITS = WB_DATA_BITS / 8;
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wire sys_clk_200MHz;
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wire i_controller_clk, i_ddr3_clk, i_ref_clk,i_clk100;
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wire clk_locked;
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wire timer_pulse, wrong_data_counter_non_zero;
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// Wishbone output signals
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wire o_wb_cyc; // Bus cycle active (1 = normal operation, 0 = cancel all ongoing transactions)
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wire o_wb_stb; // Request a transfer
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wire o_wb_we; // Write-enable (1 = write, 0 = read)
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wire [WB_ADDR_BITS - 1:0] o_wb_addr; // Burst-addressable {row, bank, col}
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wire [WB_DATA_BITS - 1:0] o_wb_data; // Write data (depends on controller width)
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wire [WB_SEL_BITS - 1:0] o_wb_sel; // Byte strobe for write (1 = write the byte)
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wire [AUX_WIDTH - 1:0] o_aux; // AXI-interface compatibility (given upon strobe)
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// Wishbone input signals
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wire i_wb_stall; // 1 = Busy, cannot accept requests
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wire i_wb_ack; // 1 = Read/write request completed
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wire [WB_DATA_BITS - 1:0] i_wb_data; // Read data
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wire [AUX_WIDTH - 1:0] i_aux; // AXI-interface compatibility (given upon strobe)
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(* mark_debug = "true" *) wire calib_complete;
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assign led[0] = !calib_complete; //light up if at DONE_CALIBRATE
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assign led[1] = !wrong_data_counter_non_zero; //light up if at there is wrong data
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assign led[2] = !timer_pulse; //light up at timer pulse
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assign led[3] = !timer_pulse; //light up at timer pulse
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IBUFDS sys_clk_ibufgds
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(
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.O(sys_clk_200MHz),
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.I(i_clk200_p),
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.IB(i_clk200_n)
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);
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clk_wiz_0 clk_wiz_inst
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(
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// Clock out ports
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.controller_clk(i_controller_clk),
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.ddr3_clk(i_ddr3_clk),
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.ref200_clk(i_ref_clk),
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.clk100(i_clk100),
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// Status and control signals
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.reset(!i_rst_n),
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.locked(clk_locked),
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// Clock in ports
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.clk_in1(sys_clk_200MHz)
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);
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// DDR3 Controller
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ddr3_top #(
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.CONTROLLER_CLK_PERIOD(CONTROLLER_CLK_PERIOD), //ps, clock period of the controller interface
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.DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
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.ROW_BITS(ROW_BITS), //width of row address
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.COL_BITS(COL_BITS), //width of column address
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.BA_BITS(BA_BITS), //width of bank address
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.BYTE_LANES(BYTE_LANES), //number of DDR3 modules to be controlled
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.AUX_WIDTH(AUX_WIDTH), //width of aux line (must be >= 4)
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.MICRON_SIM(MICRON_SIM), //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
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.ODELAY_SUPPORTED(ODELAY_SUPPORTED), //set to 1 when ODELAYE2 is supported
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.BIST_MODE(BIST_MODE)
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) ddr3_top_inst
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(
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//clock and reset
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.i_controller_clk(i_controller_clk),
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.i_ddr3_clk(i_ddr3_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD, i_ddr3_clk has period of DDR3_CLK_PERIOD
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.i_ref_clk(i_ref_clk),
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.i_ddr3_clk_90(),
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.i_rst_n(i_rst_n && clk_locked),
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// Wishbone inputs
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.i_wb_cyc(o_wb_cyc), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
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.i_wb_stb(o_wb_stb), //request a transfer
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.i_wb_we(o_wb_we), //write-enable (1 = write, 0 = read)
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.i_wb_addr(o_wb_addr), //burst-addressable {row,bank,col}
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.i_wb_data(o_wb_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
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.i_wb_sel(o_wb_sel), //byte strobe for write (1 = write the byte)
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.i_aux(o_aux), //for AXI-interface compatibility (given upon strobe)
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// Wishbone outputs
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.o_wb_stall(i_wb_stall), //1 = busy, cannot accept requests
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.o_wb_ack(i_wb_ack), //1 = read/write request has completed
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.o_wb_data(i_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
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.o_aux(i_aux),
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// PHY Interface (to be added later)
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// DDR3 I/O Interface
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.o_ddr3_clk_p(ddr3_clk_p),
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.o_ddr3_clk_n(ddr3_clk_n),
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.o_ddr3_reset_n(ddr3_reset_n),
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.o_ddr3_cke(ddr3_cke), // CKE
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.o_ddr3_cs_n(ddr3_cs_n), // chip select signal (controls rank 1 only)
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.o_ddr3_ras_n(ddr3_ras_n), // RAS#
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.o_ddr3_cas_n(ddr3_cas_n), // CAS#
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.o_ddr3_we_n(ddr3_we_n), // WE#
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.o_ddr3_addr(ddr3_addr),
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.o_ddr3_ba_addr(ddr3_ba),
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.io_ddr3_dq(ddr3_dq),
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.io_ddr3_dqs(ddr3_dqs_p),
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.io_ddr3_dqs_n(ddr3_dqs_n),
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.o_ddr3_dm(ddr3_dm),
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.o_ddr3_odt(ddr3_odt), // on-die termination
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// debug
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.o_calib_complete(calib_complete)
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);
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ddr3_test #(
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.WB_ADDR_BITS(WB_ADDR_BITS),
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.WB_DATA_BITS(WB_DATA_BITS),
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.WB_SEL_BITS(WB_SEL_BITS),
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.AUX_WIDTH(AUX_WIDTH),
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.DATA_MASK(DATA_MASK),
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.MICRON_SIM(MICRON_SIM)
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) ddr3_test_inst
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(
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.i_clk(i_controller_clk),
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.i_clk100(i_clk100),
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.i_rst_n(i_rst_n),
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//
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// Wishbone inputs
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.o_wb_cyc(o_wb_cyc), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
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.o_wb_stb(o_wb_stb), //request a transfer
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.o_wb_we(o_wb_we), //write-enable (1 = write, 0 = read)
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.o_wb_addr(o_wb_addr), //burst-addressable {row,bank,col}
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.o_wb_data(o_wb_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
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.o_wb_sel(o_wb_sel), //byte strobe for write (1 = write the byte)
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.o_aux(o_aux), //for AXI-interface compatibility (given upon strobe)
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//
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// Wishbone outputs
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.i_wb_stall(i_wb_stall), //1 = busy, cannot accept requests
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.i_wb_ack(i_wb_ack), //1 = read/write request has completed
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.i_wb_err(0), //1 = Error due to ECC double bit error (fixed to 0 if WB_ERROR = 0)
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.i_wb_data(i_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
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.i_aux(i_aux), //for AXI-interface compatibility (given upon strobe)
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//
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// Done Calibration pin
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.i_calib_complete(calib_complete),
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//
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// UART line
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.rx(rx),
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.tx(tx),
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// Button for fault injection
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.btn(!btn),
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// Debug
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.timer_pulse(timer_pulse),
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.wrong_data_counter_non_zero(wrong_data_counter_non_zero)
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);
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endmodule
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