224 lines
8.8 KiB
Verilog
224 lines
8.8 KiB
Verilog
`timescale 1ns / 1ps
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module nexysvideo_ddr3
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(
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input wire i_clk,
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input wire i_rst,
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// DDR3 I/O Interface
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output wire ddr3_clk_p, ddr3_clk_n,
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output wire ddr3_reset_n,
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output wire ddr3_cke, // CKE
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output wire ddr3_cs_n, // chip select signal
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output wire ddr3_ras_n, // RAS#
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output wire ddr3_cas_n, // CAS#
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output wire ddr3_we_n, // WE#
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output wire[14-1:0] ddr3_addr,
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output wire[3-1:0] ddr3_ba,
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inout wire[16-1:0] ddr3_dq,
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inout wire[1-1:0] ddr3_dqs_p, ddr3_dqs_n,
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output wire[2-1:0] ddr3_dm,
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output wire ddr3_odt, // on-die termination
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// UART line
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input wire rx,
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output wire tx,
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//Debug LEDs
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output reg[7:0] led,
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input wire[3:0] btn
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);
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wire i_controller_clk, i_ddr3_clk, i_ref_clk, i_ddr3_clk_90;
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wire m_axis_tvalid;
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wire rx_empty;
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wire tx_full;
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wire o_wb_ack;
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wire[7:0] o_wb_data;
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wire o_aux;
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wire[7:0] rd_data;
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wire o_wb_stall;
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reg i_wb_stb = 0, i_wb_we;
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wire[63:0] o_debug1;
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wire[31:0] o_debug2;
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reg[7:0] i_wb_data;
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reg[7:0] i_wb_addr;
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assign ddr3_cs_n = 0; //tie cs_n to ground (same as disabling the chip-select)
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reg [24:0]c;
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always @ (posedge i_controller_clk) begin
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if (!i_rst) c <= c + 1;
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else c <= 0;
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end
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reg [4:0]od1_last;
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reg bitt = 0;
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always @ (posedge i_controller_clk) begin
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od1_last <= o_debug1[4:0];
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if (btn[1]) begin
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if (od1_last != o_debug1[4:0]) bitt <= 1;
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end else
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bitt <= 0;
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end
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always @(*) begin
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if (btn[0]) begin
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led <= {c[24:23], o_debug1[4:0], bitt};
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end else begin
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if (!btn[2])
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led <= o_debug2[7:0];
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else
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led <= {4'b0, o_debug2[11:8]};
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end
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end
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always @(posedge i_controller_clk) begin
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begin
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i_wb_stb <= 0;
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i_wb_we <= 0;
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i_wb_addr <= 0;
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i_wb_data <= 0;
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if(!o_wb_stall && m_axis_tvalid) begin
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if(rd_data >= 97 && rd_data <= 122) begin //write to DDR3 if ASCII is small letter
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i_wb_stb <= 1;
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i_wb_we <= 1;
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i_wb_addr <= ~rd_data ;
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i_wb_data <= rd_data;
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end
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else if(rd_data >= 65 && rd_data <= 90) begin //read from DDR3 if ASCII is capital letter
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i_wb_stb <= 1; //make request
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i_wb_we <= 0; //read
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i_wb_addr <= ~(rd_data + 8'd32);
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end
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end
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end
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end
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(* mark_debug = "true" *) wire clk_locked;
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clk_wiz clk_wiz_inst
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(
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// Clock out ports
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.clk_out1(i_controller_clk), //83.333 Mhz
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.clk_out2(i_ddr3_clk), // 333.333 MHz
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.clk_out3(i_ref_clk), //200MHz
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.clk_out4(i_ddr3_clk_90), // 333.333 MHz with 90degree shift
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// Status and control signals
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.reset(i_rst),
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.locked(clk_locked),
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// Clock in ports
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.clk_in1(i_clk)
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);
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// UART TX/RXmodule from https://github.com/ben-marshall/uart
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uart_tx #(
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.BIT_RATE(9600),
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.CLK_HZ(83_333_333),
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.PAYLOAD_BITS(8),
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.STOP_BITS(1)
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) uart_tx_inst (
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.clk(i_controller_clk), // Top level system clock input.
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.resetn(!i_rst && clk_locked && o_debug1[4:0] == 23), // Asynchronous active low reset.
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.uart_txd(tx), // UART transmit pin.
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.uart_tx_busy(), // Module busy sending previous item.
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.uart_tx_en(o_wb_ack), // Send the data on uart_tx_data
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.uart_tx_data(o_wb_data) // The data to be sent
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);
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uart_rx #(
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.BIT_RATE(9600),
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.CLK_HZ(83_333_333),
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.PAYLOAD_BITS(8),
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.STOP_BITS(1)
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) uart_rx_inst (
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.clk(i_controller_clk), // Top level system clock input.
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.resetn(!i_rst && clk_locked && o_debug1[4:0] == 23), // Asynchronous active low reset.
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.uart_rxd(rx), // UART Recieve pin.
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.uart_rx_en(o_debug1[4:0] == 23), // Recieve enable
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.uart_rx_break(), // Did we get a BREAK message?
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.uart_rx_valid(m_axis_tvalid), // Valid data recieved/available.
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.uart_rx_data(rd_data) // The recieved data.
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);
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// UART module from https://github.com/alexforencich/verilog-uart (DOES NOT WORK ON OPENXC7, UberDDR3 cannot finish calibration when this UART is used)
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// uart #(.DATA_WIDTH(8)) uart_m
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// (
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// .clk(i_controller_clk),
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// .rst(i_rst),
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// .s_axis_tdata(o_wb_data),
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// .s_axis_tvalid(o_wb_ack),
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// .s_axis_tready(),
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// .m_axis_tdata(rd_data),
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// .m_axis_tvalid(m_axis_tvalid),
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// .m_axis_tready(1),
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// .rxd(rx),
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// .txd(tx),
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// .prescale(1085) //9600 Baud Rate (83.33MHz/(8*9600))
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// );
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// DDR3 Controller
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ddr3_top #(
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.CONTROLLER_CLK_PERIOD(12_000), //12_000ps, clock period of the controller interface
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.DDR3_CLK_PERIOD(3_000), //3_000ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
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.ROW_BITS(14), //width of row address
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.COL_BITS(10), //width of column address
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.BA_BITS(3), //width of bank address
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.DQ_BITS(8), //width of DQ
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.BYTE_LANES(1), //number of DDR3 modules to be controlled
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.AUX_WIDTH(4), //width of aux line (must be >= 4)
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.WB2_ADDR_BITS(32), //width of 2nd wishbone address bus
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.WB2_DATA_BITS(32), //width of 2nd wishbone data bus
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.MICRON_SIM(0), //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
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.ODELAY_SUPPORTED(0), //set to 1 when ODELAYE2 is supported
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.SECOND_WISHBONE(0) //set to 1 if 2nd wishbone is needed
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) ddr3_top_inst
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(
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//clock and reset
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.i_controller_clk(i_controller_clk),
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.i_ddr3_clk(i_ddr3_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD, i_ddr3_clk has period of DDR3_CLK_PERIOD
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.i_ref_clk(i_ref_clk),
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.i_ddr3_clk_90(i_ddr3_clk_90),
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.i_rst_n(!i_rst && clk_locked),
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// Wishbone inputs
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.i_wb_cyc(1), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
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.i_wb_stb(i_wb_stb), //request a transfer
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.i_wb_we(i_wb_we), //write-enable (1 = write, 0 = read)
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.i_wb_addr(i_wb_addr), //burst-addressable {row,bank,col}
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.i_wb_data(i_wb_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
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.i_wb_sel(16'hffff), //byte strobe for write (1 = write the byte)
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.i_aux(i_wb_we), //for AXI-interface compatibility (given upon strobe)
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// Wishbone outputs
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.o_wb_stall(o_wb_stall), //1 = busy, cannot accept requests
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.o_wb_ack(o_wb_ack), //1 = read/write request has completed
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.o_wb_data(o_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
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.o_aux(o_aux),
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// Wishbone 2 (PHY) inputs
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.i_wb2_cyc(), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
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.i_wb2_stb(), //request a transfer
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.i_wb2_we(), //write-enable (1 = write, 0 = read)
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.i_wb2_addr(), //burst-addressable {row,bank,col}
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.i_wb2_data(), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
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.i_wb2_sel(), //byte strobe for write (1 = write the byte)
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// Wishbone 2 (Controller) outputs
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.o_wb2_stall(), //1 = busy, cannot accept requests
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.o_wb2_ack(), //1 = read/write request has completed
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.o_wb2_data(), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
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// PHY Interface (to be added later)
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// DDR3 I/O Interface
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.o_ddr3_clk_p(ddr3_clk_p),
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.o_ddr3_clk_n(ddr3_clk_n),
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.o_ddr3_reset_n(ddr3_reset_n),
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.o_ddr3_cke(ddr3_cke), // CKE
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.o_ddr3_cs_n(/*ddr3_cs_n*/), // chip select signal (controls rank 1 only)
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.o_ddr3_ras_n(ddr3_ras_n), // RAS#
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.o_ddr3_cas_n(ddr3_cas_n), // CAS#
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.o_ddr3_we_n(ddr3_we_n), // WE#
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.o_ddr3_addr(ddr3_addr),
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.o_ddr3_ba_addr(ddr3_ba),
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.io_ddr3_dq(ddr3_dq),
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.io_ddr3_dqs(ddr3_dqs_p),
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.io_ddr3_dqs_n(ddr3_dqs_n),
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.o_ddr3_dm(ddr3_dm),
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.o_ddr3_odt(ddr3_odt), // on-die termination
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.o_debug1(o_debug1)
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);
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endmodule
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