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ecp5_phy

main

openxc7_run

pass_verilator_lint

run_iverilog_sim

#1

#12

#14

#17

#19

#2

#20

#21

#22

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#31

#32

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Mono Color

• a56e6a8a24
  changed write calibration pattern with high autocorrel stat Angelo Jacobo 2023-05-29 16:40:41 +0800
• 400a277cdc
  added 52ns sync reset (IDELAYCTRL requirement) Angelo Jacobo 2023-05-29 16:19:32 +0800
• f4f0a5c11c
  Update run.sh with the new ddr3 files Angelo Jacobo 2023-05-28 16:24:22 +0800
• 7480704b3d
  Delete kluster.xdc Angelo Jacobo 2023-05-28 16:21:43 +0800
• 02d512df55
  Delete sdram.txt Angelo Jacobo 2023-05-28 16:20:52 +0800
• 12b533a9d1
  added top module which instantiates the controller and phy Angelo Jacobo 2023-05-28 16:20:22 +0800
• f648035e4e
  added phy interface (separated from controller) Angelo Jacobo 2023-05-28 16:19:47 +0800
• ab26902f7a
  include only the controller (phy is now a separate module) Angelo Jacobo 2023-05-28 16:18:14 +0800
• 854839dde9
  readme file from Micron Angelo Jacobo 2023-05-28 16:14:21 +0800
• b9154a38bb
  Delete rtl/DDR3 directory Angelo Jacobo 2023-05-28 16:11:49 +0800
• fb8dd029e3
  Delete ug586_7Series_MIS.pdf Angelo Jacobo 2023-05-28 16:08:40 +0800
• 5092543e74
  Add files via upload Angelo Jacobo 2023-05-25 19:45:06 +0800
• 30b5675b41
  Update README.md Angelo Jacobo 2023-05-25 19:41:51 +0800
• 6710b5b62b
  Add files via upload Angelo Jacobo 2023-05-25 19:14:12 +0800
• 1e89a236df
  fixed implementation errors in Vivado Angelo Jacobo 2023-05-25 19:13:30 +0800
• 4e07df4018
  Update README.md Angelo Jacobo 2023-05-22 19:59:17 +0800
• a7de749ddf
  Add files via upload Angelo Jacobo 2023-05-22 19:53:20 +0800
• f91e5ea75d
  Update README.md Angelo Jacobo 2023-05-18 11:51:19 +0800
• 94d6253069
  Add files via upload Angelo Jacobo 2023-05-18 11:02:40 +0800
• 991dcad40b
  Add files via upload Angelo Jacobo 2023-05-18 10:50:30 +0800
• 8e6c422689
  complete read and write calibration Angelo Jacobo 2023-05-18 10:45:26 +0800
• ee990dd647
  Update README.md Angelo Jacobo 2023-05-11 19:36:56 +0800
• 9602a4225d
  Update README.md Angelo Jacobo 2023-05-11 19:23:11 +0800
• 614fd7dfe2
  Update README.md Angelo Jacobo 2023-05-11 19:22:34 +0800
• 520300ecb0
  Update README.md Angelo Jacobo 2023-05-11 19:12:16 +0800
• f280ba3efd
  Update README.md Angelo Jacobo 2023-05-11 19:07:17 +0800
• 233b89dafb
  Update README.md Angelo Jacobo 2023-05-11 18:58:25 +0800
• c21879c165
  Update README.md Angelo Jacobo 2023-05-11 18:50:59 +0800
• b631fe7ebc
  Update README.md Angelo Jacobo 2023-05-11 18:24:12 +0800
• ec8d957291
  Update README.md Angelo Jacobo 2023-05-11 18:03:30 +0800
• c33bc40bd3
  Update ddr3_controller.v Angelo Jacobo 2023-05-11 15:35:34 +0800
• 9be5b5a616
  Update ddr3_controller.v Angelo Jacobo 2023-05-11 14:49:47 +0800
• f3c4b1b465
  Update ddr3_controller.v Angelo Jacobo 2023-05-10 15:23:48 +0800
• 6c67942a80
  Update README.md Angelo Jacobo 2023-04-27 20:02:37 +0800
• d7db0d33e0
  Update README.md Angelo Jacobo 2023-04-27 19:56:43 +0800
• fd09ce2ed9
  Update README.md Angelo Jacobo 2023-04-27 19:48:59 +0800
• c0172c24a3
  added read phy interface Angelo Jacobo 2023-04-27 19:40:35 +0800
• 7debc3a4ce
  Update README.md Angelo Jacobo 2023-04-20 22:20:44 +0800
• 4c503e7225
  Update README.md Angelo Jacobo 2023-04-20 19:59:55 +0800
• a5b14accf4
  added PHY interface Angelo Jacobo 2023-04-20 19:37:15 +0800
• 92b9d4b909
  Update README.md Angelo Jacobo 2023-04-20 19:20:47 +0800
• 060a0373e9
  Update ddr3_controller.v Angelo Jacobo 2023-04-06 19:56:55 +0800
• 9a0b0cde36
  Add files via upload Angelo Jacobo 2023-04-06 19:45:09 +0800
• 7c47580d4d
  Delete formal_cover.gtkw Angelo Jacobo 2023-04-06 19:44:30 +0800
• 3b110018c7
  Update ddr3_controller.v Angelo Jacobo 2023-04-06 19:43:32 +0800
• 328bcf761a
  Update README.md Angelo Jacobo 2023-04-06 19:41:57 +0800
• 5b22cf3f3b
  Update README.md Angelo Jacobo 2023-04-06 19:22:22 +0800
• fec8b5b3fc
  Update ddr3_controller.v Angelo Jacobo 2023-04-06 19:01:02 +0800
• b7dc38c510
  Update README.md Angelo Jacobo 2023-04-06 17:54:16 +0800
• 7bb755b9d5
  Update README.md Angelo Jacobo 2023-04-06 17:34:05 +0800
• 1380c03c85
  Update README.md Angelo Jacobo 2023-04-06 17:31:23 +0800
• ae201bfd04
  removed irrelevant comments Angelo Jacobo 2023-03-30 19:18:55 +0800
• 192a9950e4
  applied :retab Angelo Jacobo 2023-03-30 18:27:58 +0800
• 7e1a145238
  added gtkwave template Angelo Jacobo 2023-03-30 18:19:14 +0800
• fa5fcc2615
  use a 4-bit counter plus a 4-bit mask for tracking delay in every bank Angelo Jacobo 2023-03-30 18:17:46 +0800
• fa3f5e0d65
  use 32-bit shift reg for tracking delay inside every bank Angelo Jacobo 2023-03-30 18:14:09 +0800
• 73e5f6b3de
  added begin-end in short if-else statement Angelo Jacobo 2023-03-23 20:35:37 +0800
• 2018aa7ef7
  changed license to Apache 2.0 Angelo Jacobo 2023-03-23 20:18:46 +0800
• 97092cf869
  added logic for refresh sequence and bank access Angelo Jacobo 2023-03-23 20:17:12 +0800
• 59ac654990
  Delete LICENSE Angelo Jacobo 2023-03-23 20:10:22 +0800
• 973e0a5df1
  Update README.md Angelo Jacobo 2023-03-13 14:40:46 +0800
• 7282e2565d
  removed parameter file "ddr3_parameters.vh" Angelo Jacobo 2023-03-09 18:16:01 +0800
• adb21070d4
  used :retab and fixed tab spacing Angelo Jacobo 2023-03-09 18:14:58 +0800
• c5d387fa24
  added reset sequence and formal assertions Angelo Jacobo 2023-03-09 18:06:53 +0800
• 71df6f7515
  moved all parameters to the main verilog file Angelo Jacobo 2023-03-09 18:01:58 +0800
• 86e01b060e
  Update README.md Angelo Jacobo 2023-03-02 20:32:12 +0800
• 084a681644
  include directory on iverilog command Angelo Jacobo 2023-03-02 20:20:14 +0800
• 3633613c47
  Update ddr3_controller.v Angelo Jacobo 2023-03-02 20:12:28 +0800
• 6b9607563e
  added sby file for formal verif Angelo Jacobo 2023-03-02 20:11:10 +0800
• 0f6f52390c
  added shell script for compiling RTL Angelo Jacobo 2023-03-02 20:07:08 +0800
• 38109d8297
  added initial RTLs Angelo Jacobo 2023-03-02 20:04:37 +0800
• 23d946c51c
  Initial commit Angelo Jacobo 2023-03-02 19:44:58 +0800