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UberDDR3
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  • 7142dd9cdb added more registers and formal assertions to wb2 AngeloJacobo 2023-07-19 18:46:36 +0800
  • 137e30ba36 resolve vivado warnings AngeloJacobo 2023-07-17 21:39:07 +0800
  • 97e740139f resolved vivado warnings AngeloJacobo 2023-07-17 21:38:20 +0800
  • 983919d9df removed unneeded .* files AngeloJacobo 2023-07-16 08:52:10 +0800
  • 12c947afb1 Merge branch 'main' of https://github.com/AngeloJacobo/DDR3_Controller into main AngeloJacobo 2023-07-16 08:46:27 +0800
  • 4f857e08f4 add files back after git rm -r cached . AngeloJacobo 2023-07-16 08:46:16 +0800
  • 4e61060927 update wcfg AngeloJacobo 2023-07-16 08:40:04 +0800
  • b16c4d56cd fixed error due to missing port dm and incorrect IO type for aux AngeloJacobo 2023-07-16 08:39:24 +0800
  • b80bda4a46 resolve warning from verilator linting AngeloJacobo 2023-07-16 08:38:20 +0800
  • 019722bc70 resolve warnings and errors from verilator linting AngeloJacobo 2023-07-16 08:17:55 +0800
  • 9a29fba26b
         Update formal.gtkw Angelo Jacobo 2023-07-13 19:35:18 +0800
  • c45fd85ee4
         Update formal_wb2.gtkw Angelo Jacobo 2023-07-13 19:34:56 +0800
  • bd23827864
         delete, replace with much cleaner xsim/ Angelo Jacobo 2023-07-13 19:29:20 +0800
  • 352205c970 test test AngeloJacobo 2023-07-13 19:26:36 +0800
  • bad4ca3086 delete AngeloJacobo 2023-07-13 19:25:51 +0800
  • fb7f48b3b8 add git ignore AngeloJacobo 2023-07-13 19:19:43 +0800
  • b2fd0bf4fe add formal gtkw files AngeloJacobo 2023-07-13 19:18:35 +0800
  • ac3af7f23f deleted AngeloJacobo 2023-07-13 19:17:25 +0800
  • 17e7040626 set different FLY_BY_DELAY for each lanes AngeloJacobo 2023-07-13 19:04:43 +0800
  • 4273a172f5 add wishbone 2 interface AngeloJacobo 2023-07-13 18:57:35 +0800
  • 29ef663d87 set parameter FLY_BY_DELAY for each instantiated ddr3, the delay value is retrieved from 8192Mb_ddr3_parameters.vh AngeloJacobo 2023-07-13 18:55:57 +0800
  • 6655959514 set different fly_by_delays for each lanes AngeloJacobo 2023-07-13 18:54:25 +0800
  • ecb4cb5b2c moved FLY_BY_DELAY to this module so multiple instantiated ddr3 can have different set FLY_BY_DELAY AngeloJacobo 2023-07-13 18:52:43 +0800
  • ee3d9d4be7 moved phy to TOP and controller to MAIN, removed constraints for xdc file AngeloJacobo 2023-07-13 18:50:56 +0800
  • ee83028986 make stall and accessible outside, removed added assumptions with i_slave_busy AngeloJacobo 2023-07-13 18:48:34 +0800
  • 2541d0afcc added wishbone 2 ports AngeloJacobo 2023-07-13 18:45:43 +0800
  • 6fef8081ce delete copy AngeloJacobo 2023-07-13 18:45:00 +0800
  • 89c2b8fbd7 set depth to 7 (minimum) AngeloJacobo 2023-07-13 18:43:47 +0800
  • 47766cb8e8 added wishbone 2 and formally verified it AngeloJacobo 2023-07-13 18:41:25 +0800
  • 5904a4910d shortened formal depth from 9 to 7 AngeloJacobo 2023-07-09 09:34:03 +0800
  • b03ca1864f shortened formal depth from 17 to 9 AngeloJacobo 2023-07-08 10:19:58 +0800
  • 25d7f3bffd update gtkw AngeloJacobo 2023-07-06 20:33:48 +0800
  • a4d4e3a099 change all to non-blocking AngeloJacobo 2023-07-06 20:32:12 +0800
  • b3c9bdb650 pass test for timing params with depth of 9 AngeloJacobo 2023-07-06 20:29:50 +0800
  • 69c34dbf8f update logs AngeloJacobo 2023-07-05 19:48:14 +0800
  • 1881e059bc add summary log of regression test (not yet complete) AngeloJacobo 2023-07-05 19:47:00 +0800
  • 10c290f9f8 temp newest version AngeloJacobo 2023-07-05 19:46:18 +0800
  • 122e2a2d3c exported simulation scripts from Vivado AngeloJacobo 2023-07-05 16:50:40 +0800
  • ec6488f68f gtkw for testing time parameters AngeloJacobo 2023-07-05 16:48:40 +0800
  • ab17b8012b add average rate in report AngeloJacobo 2023-07-05 16:44:31 +0800
  • 7af3358162 update vivado wcfg file AngeloJacobo 2023-07-05 16:42:48 +0800
  • 3250d8d368 write dqs toggles for half slow clk cycle at the end, needed when DQ is set to be delayed (non-zero flyby delay) AngeloJacobo 2023-07-05 16:41:55 +0800
  • ce3ca7e158 pre-refresh delay is now flexible and not fixed. Separated formal properties for testing time parameters AngeloJacobo 2023-07-05 16:35:57 +0800
  • 217770b977 verified precharge and activate cmds, fixed bug in write_calib cmd AngeloJacobo 2023-07-02 06:38:33 +0800
  • 3c32501ffd log before passing fwb_slave AngeloJacobo 2023-06-29 19:37:49 +0800
  • bf7f9142b8 log after passing fwb_slave AngeloJacobo 2023-06-29 19:24:06 +0800
  • d6f9614295 update gtkw AngeloJacobo 2023-06-29 13:03:08 +0800
  • 3251dda112 added gtkw for cover AngeloJacobo 2023-06-29 13:00:52 +0800
  • ba00cb9063 changed to non-blocking simulation AngeloJacobo 2023-06-29 12:59:57 +0800
  • 188b26ee12 assume no request when slave busy (calibration or at refresh) AngeloJacobo 2023-06-29 12:58:41 +0800
  • 2ca5a15c30 add cover AngeloJacobo 2023-06-29 12:56:58 +0800
  • 760c75d238 passes optimized pipeline stall control and passed fwb_slave properties AngeloJacobo 2023-06-29 12:56:24 +0800
  • 463707a07c sim log before passing fwb_slave AngeloJacobo 2023-06-28 21:16:56 +0800
  • 2cfbba6d28 change ff to unix AngeloJacobo 2023-06-24 08:04:21 +0800
  • 6f90bc165c passes all test with no violations AngeloJacobo 2023-06-24 07:59:05 +0800
  • 4ecf119454 add error injections and use aux to determine ack request type AngeloJacobo 2023-06-24 07:56:05 +0800
  • c9e29935a0 add more pins in gtkw AngeloJacobo 2023-06-24 07:54:17 +0800
  • 310f2d5af8 update wcfg AngeloJacobo 2023-06-24 07:53:28 +0800
  • a42a13ecab Merge branch 'main' of https://github.com/AngeloJacobo/DDR3_Controller into main AngeloJacobo 2023-06-24 07:52:02 +0800
  • 2221a739db add 2 clocks in prestall delay to pass tWR violation, add more asserts for fwb_slave AngeloJacobo 2023-06-24 07:46:09 +0800
  • e97dae7d5b
         Update README.md Angelo Jacobo 2023-06-22 20:01:01 +0800
  • b0e3b83e96 added wb properties from zipcpu repo AngeloJacobo 2023-06-22 19:54:39 +0800
  • d93cf9fb4e fixed delay for data mask as same delay as dq AngeloJacobo 2023-06-22 19:53:37 +0800
  • ef10bfd455 add data mask port AngeloJacobo 2023-06-22 19:52:45 +0800
  • 272711762e add phy for data mask (oserdes -> odelay -> obuf) AngeloJacobo 2023-06-22 19:51:06 +0800
  • 0ffdacf6e7 add logic for write wb_ack, wb_sel, and aux AngeloJacobo 2023-06-22 19:49:05 +0800
  • f4b138ff77 Merge branch 'main' of https://github.com/AngeloJacobo/DDR3_Controller into main AngeloJacobo 2023-06-22 19:45:16 +0800
  • 96f4edd3e8 add wb properties module AngeloJacobo 2023-06-22 19:44:37 +0800
  • 4cb3b4a4b5
         Update README.md Angelo Jacobo 2023-06-15 18:54:42 +0800
  • 4786c77176
         Update temp.log Angelo Jacobo 2023-06-15 18:52:08 +0800
  • a98364dd1e added gtkw for formal AngeloJacobo 2023-06-15 17:46:58 +0800
  • 1937d34565 create test 1(sequential access to first,middle,last rows) and test 2(random access) AngeloJacobo 2023-06-15 17:46:14 +0800
  • 0923fdc0b6 add formal assertions using fifo to prove every wb request has a corresponding read/write command output AngeloJacobo 2023-06-15 17:43:15 +0800
  • fd897b76bb update size of command_used AngeloJacobo 2023-06-15 17:33:09 +0800
  • 7c8b8af71f add minimum depth requirement for possible clock periods AngeloJacobo 2023-06-15 17:24:48 +0800
  • 60c9d5ae85 added command type to be displayed in ASCII, changed all to posedge AngeloJacobo 2023-06-10 08:41:37 +0800
  • acedb1310b added delay counters for debugging AngeloJacobo 2023-06-10 08:40:13 +0800
  • 366238b374 Merge branch 'main' of https://github.com/AngeloJacobo/DDR3_Controller into main AngeloJacobo 2023-06-10 08:27:45 +0800
  • 053a511144 set write-to-read delay for all banks for every write AngeloJacobo 2023-06-10 08:19:16 +0800
  • f80837491d
         Update README.md Angelo Jacobo 2023-06-08 14:16:27 +0800
  • 0bdef3092e
         Create temp.log for sim output Angelo Jacobo 2023-06-08 14:12:40 +0800
  • 806b49ebd5 changed folder name with underscore AngeloJacobo 2023-06-08 14:05:35 +0800
  • f3e15e9ea4 added test 1: Sequential write then sequential read AngeloJacobo 2023-06-08 13:56:54 +0800
  • 2e6c2183aa added sim duration for possible bus delays AngeloJacobo 2023-06-08 13:55:20 +0800
  • de37c5a972 added wires for loadingg delay tap AngeloJacobo 2023-06-08 13:53:07 +0800
  • b9204332b1 made delay tap loadable AngeloJacobo 2023-06-08 13:52:04 +0800
  • c3707dab53 made delay tap loadable and made delay more flexible to use all 32 taps for both dqs and dq AngeloJacobo 2023-06-08 11:01:56 +0800
  • 0e5d95098e added more pins to be debugged AngeloJacobo 2023-06-08 10:55:32 +0800
  • 710d477014
         added vivado gtkw for micron model simulation Angelo Jacobo 2023-06-03 14:31:29 +0800
  • 98ed92a65b
         added testbench for a single ddr3 device sim Angelo Jacobo 2023-06-03 14:28:55 +0800
  • 9a19f82377
         added testbench for model simulation Angelo Jacobo 2023-06-03 14:24:11 +0800
  • 884fd2bcad
         Add files via upload Angelo Jacobo 2023-06-01 19:59:45 +0800
  • 35c992d6fd
         uploaded model.log Angelo Jacobo 2023-06-01 19:30:16 +0800
  • 748274ffff
         Update README.md Angelo Jacobo 2023-06-01 19:27:25 +0800
  • 6127bba77a
         fixed data alignment for write operation, fixed CL and CWL for 100MHz:400MHz clk Angelo Jacobo 2023-06-01 19:18:41 +0800
  • 26af4960e9
         fixed display for prev_cmd and time difference Angelo Jacobo 2023-06-01 19:15:36 +0800
  • 0a43b04f9e
         added phy for generating differential o_ddr3_clk Angelo Jacobo 2023-05-29 21:51:48 +0800
  • d6b6c0b9a4
         added o_ddr3_clk port Angelo Jacobo 2023-05-29 21:48:44 +0800
  • d674b1c9c2
         added autofpga text file for including the controller Angelo Jacobo 2023-05-29 20:59:12 +0800
  • 9e529131c0
         fixed error "added_read_pipe has multiple drivers" Angelo Jacobo 2023-05-29 20:52:48 +0800