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UberDDR3
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  • cf3bc8c629
         added more comments Angelo Jacobo 2024-03-22 18:30:51 +0800
  • 666f98d6c1
         Update LICENSE to GPL 3.0 Angelo Jacobo 2024-02-23 19:00:14 +0800
  • 3311775af9
         Update README.md Angelo Jacobo 2023-11-29 19:52:02 +0800
  • 2d5c6a9e02
         Update README.md Angelo Jacobo 2023-11-29 19:50:16 +0800
  • c4b40229a0
         Update README.md Angelo Jacobo 2023-11-29 19:48:13 +0800
  • 234c1c417f
         Update README.md Angelo Jacobo 2023-11-29 19:43:39 +0800
  • 9e1d329617
         Update README.md Angelo Jacobo 2023-11-29 19:40:21 +0800
  • b2c0cb86ac
         Update README.md Angelo Jacobo 2023-11-29 19:18:51 +0800
  • a4e775a112
         Update README.md Angelo Jacobo 2023-11-29 19:17:06 +0800
  • be08a478ac
         move user documentation to this README Angelo Jacobo 2023-11-29 18:23:19 +0800
  • a566ef1960 fix clock periods AngeloJacobo 2023-11-26 15:07:22 +0800
  • 5b3aa21ccc renamed folder AngeloJacobo 2023-11-26 14:32:40 +0800
  • 2a926cfc91 moved ARTY-S7 project files AngeloJacobo 2023-11-26 14:04:15 +0800
  • 8d20a6f4d0 moved wcfg file inside testbench AngeloJacobo 2023-11-26 13:53:43 +0800
  • ba98139c56 changed the extension of all simulation files to systemverilog AngeloJacobo 2023-11-26 13:53:02 +0800
  • dcb48b75d3 changed the extension of all simulation files to systemverilog AngeloJacobo 2023-11-26 13:51:30 +0800
  • 15fe5af5d9 add extra line AngeloJacobo 2023-11-26 13:35:59 +0800
  • 9a88f5540c fix displayed report AngeloJacobo 2023-11-26 13:21:15 +0800
  • b54000f5f0 fix instantiation AngeloJacobo 2023-11-18 13:41:39 +0800
  • 6d594a0dbb use multiple-task sby with summary at end AngeloJacobo 2023-11-18 13:36:29 +0800
  • efc194a633 add instantiation template AngeloJacobo 2023-11-18 13:35:38 +0800
  • 292f94c530 make 2nd wishbone removable via cyc line AngeloJacobo 2023-11-18 13:34:27 +0800
  • c2fc70fb6c changed to picosecond-based instead of nanoseconds AngeloJacobo 2023-11-14 14:14:16 +0800
  • 29ec2d0714 changed to picosecond-based instead of nanoseconds AngeloJacobo 2023-11-14 14:13:41 +0800
  • c514d492f1 changed to picosecond-based instead of nanoseconds AngeloJacobo 2023-11-14 14:11:40 +0800
  • c4a03632ff change param to picoseconds, opt_200MHz is not passing due to very high depth required thus removed for now AngeloJacobo 2023-11-14 14:07:02 +0800
  • 0cfd8243ab remove all IODELAY_GROUP lines AngeloJacobo 2023-11-11 11:32:14 +0800
  • 62f2088d0b fix bug when running multiple verification tasks AngeloJacobo 2023-11-11 11:20:57 +0800
  • 33ec101b79 resolve bug "Conflicting initialization values for \index" AngeloJacobo 2023-11-11 10:18:15 +0800
  • b9b49d67ab add xdc file used to test controller in Arty-S7 AngeloJacobo 2023-11-09 14:16:46 +0800
  • 0b7d07e133 delete old bit and debug files AngeloJacobo 2023-11-09 14:14:27 +0800
  • 2037044fb4 fixed reset logic of _top, changed address accessed by ~ AngeloJacobo 2023-11-09 14:13:08 +0800
  • 896d3f4f23 clean description,and added missing parameters AngeloJacobo 2023-11-09 13:49:41 +0800
  • 20953ee65f fixed bug when ODELAY is not supported, clean file header and description AngeloJacobo 2023-11-09 13:25:39 +0800
  • a1e6ca6656
         Update README.md Angelo Jacobo 2023-09-21 21:27:53 +0800
  • 72b249a862
         Update README.md Angelo Jacobo 2023-09-21 06:07:03 +0800
  • 87fa29fcfe
         Update README.md Angelo Jacobo 2023-09-21 06:04:41 +0800
  • d640e52221 add wbscope AngeloJacobo 2023-09-15 20:05:31 +0800
  • 57e9f1b3f9 update simulation files AngeloJacobo 2023-09-15 20:04:55 +0800
  • 0ba4f433e5 add delay option to misalign dq from dqs AngeloJacobo 2023-09-15 20:02:05 +0800
  • d834a4d67d update wave files AngeloJacobo 2023-09-15 20:00:29 +0800
  • a80bacb718 add reset control from controller to phy AngeloJacobo 2023-09-15 19:59:39 +0800
  • 922d185643 now passes internal test calibration on klusterboard AngeloJacobo 2023-09-15 19:58:36 +0800
  • 8c5c5e30cc now passes internal test calibration on klusterboard AngeloJacobo 2023-09-15 19:58:12 +0800
  • 98b22f79f4 delete extra xdc file AngeloJacobo 2023-09-15 19:56:01 +0800
  • 43939ba837 update autodata files and xdc file AngeloJacobo 2023-09-15 19:51:21 +0800
  • 20db6352e2 added write read test after calibration AngeloJacobo 2023-09-08 17:15:34 +0800
  • de4fb994b4 add debug lines and update wb2 registers AngeloJacobo 2023-09-05 20:17:10 +0800
  • 92c25f394f add wire for cue when write leveling starts AngeloJacobo 2023-09-05 18:33:20 +0800
  • 2ee7e35bc5 add dci reset and optional DCIEN IO buffers AngeloJacobo 2023-09-05 18:32:30 +0800
  • 03a1da2ce7 add calibration when DQS toggles early than DQ AngeloJacobo 2023-09-05 18:31:10 +0800
  • 4fa30574ef not yet working when real parameter is used AngeloJacobo 2023-08-24 18:03:12 +0800
  • dc641c188b copied settings from litedram AngeloJacobo 2023-08-24 18:01:58 +0800
  • 47e68d05e1 added xdc file that uses DCI AngeloJacobo 2023-08-24 18:01:24 +0800
  • 8f3d673e3d fixed bug when issue write calibration has to be repeated AngeloJacobo 2023-08-22 16:40:44 +0800
  • fd443ddefd add wb2 width AngeloJacobo 2023-08-20 13:23:48 +0800
  • 83b7b95af4 pass verilator warning AngeloJacobo 2023-08-20 12:32:51 +0800
  • a8aec13ed9 using different address now finally works! AngeloJacobo 2023-08-20 11:52:54 +0800
  • 00757338da update wcfg AngeloJacobo 2023-08-20 11:21:16 +0800
  • 5df83b8182 added working bitfiles for arty s7 AngeloJacobo 2023-08-20 11:20:41 +0800
  • 989e8dd9e7 use macro for defining the ddr3 config (EIGHT_LANES_x8 or TWO_LANES_x8) and the source of clk (if clock wizard or not) AngeloJacobo 2023-08-20 11:13:50 +0800
  • 7c68bee5e8 changed for x8 config AngeloJacobo 2023-08-20 11:10:15 +0800
  • e2653d5793 reset for IO is released only after IDELAYCTRL is ready, added also IODELAY_GROUP AngeloJacobo 2023-08-20 11:09:38 +0800
  • 9769a7cfaa pass formal for 8-lane config and pass verilator linting AngeloJacobo 2023-08-20 11:07:22 +0800
  • e839e220c3 ddr3 model fails when ROW_BITS less than 16 (has Z value in address) AngeloJacobo 2023-08-17 11:42:09 +0800
  • ef8b1b84fc update wcfg AngeloJacobo 2023-08-17 11:41:05 +0800
  • c97e5a8c1f added test for testing design in ARTY-S7 AngeloJacobo 2023-08-17 11:40:41 +0800
  • c9b19ac887 added uart submodule AngeloJacobo 2023-08-17 11:36:15 +0800
  • 36c93689e5 redo read/write calibration if data read is wrong AngeloJacobo 2023-08-17 11:27:23 +0800
  • a8bf429bc8 allow tdqs off and use dm AngeloJacobo 2023-08-15 21:17:13 +0800
  • f296d08c6b add option for ODELAY_SUPPORTED=0 and added port for i_ddr3_clk_90 AngeloJacobo 2023-08-15 19:37:28 +0800
  • 411febc1a8 add option for ODELAY_SUPPORTED=0 (for FPGAs without ODELAY) AngeloJacobo 2023-08-15 19:35:44 +0800
  • b3ab21a6d5 add option for ODELAY_SUPPORTED=0 (for FPGAs without ODELAY) AngeloJacobo 2023-08-15 19:12:49 +0800
  • b762c464f6
         add images for hardware debug Angelo Jacobo 2023-08-04 19:18:47 +0800
  • a7ebaefbdb add autofpga text file for wbscope AngeloJacobo 2023-08-04 18:57:03 +0800
  • 80f12d1663 move to kintex_switch_files folder AngeloJacobo 2023-08-04 16:37:48 +0800
  • 69768da1c8 added files for kintex switch project (autofpga files, xdc, wbscope cpp) AngeloJacobo 2023-08-04 16:37:10 +0800
  • e9f1ab4971 modify debug port logic for wbscope AngeloJacobo 2023-08-04 07:57:09 +0800
  • bc66655ca7 just fixed delay AngeloJacobo 2023-08-04 07:54:20 +0800
  • 0753e6e157 fixed localparam value for wb_addr_bits AngeloJacobo 2023-08-04 07:53:12 +0800
  • 72dc00742b correct generate indexes AngeloJacobo 2023-08-04 07:52:31 +0800
  • 1bfd851a6e pass formal with LANES either 1,2,4,8 AngeloJacobo 2023-08-04 07:49:25 +0800
  • 7c76a15087 update wcfg AngeloJacobo 2023-08-01 15:59:34 +0800
  • 2c73f38f99 added debug port and max function for int type AngeloJacobo 2023-08-01 15:58:58 +0800
  • e4bd0ac09c delete| AngeloJacobo 2023-07-24 19:46:23 +0800
  • 92dcb0990a update gitignore AngeloJacobo 2023-07-24 17:37:07 +0800
  • d2ae29c26a simulation file for SODIMM AngeloJacobo 2023-07-24 17:34:40 +0800
  • 4589fc3dfe script for running verilator, yosys, iverilog, and then symbiyosys AngeloJacobo 2023-07-24 17:33:56 +0800
  • 4e5b98f485 use SODIMM instead of DIMM in simulation AngeloJacobo 2023-07-24 17:32:56 +0800
  • da10a5f5d1 Merge branch 'main' of https://github.com/AngeloJacobo/DDR3_Controller into main AngeloJacobo 2023-07-24 17:30:45 +0800
  • d5f1d600ea resolve verilator warnings and add option YOSYS for not using input real in functions AngeloJacobo 2023-07-24 17:27:17 +0800
  • 47ba90962a delete this later AngeloJacobo 2023-07-23 10:16:19 +0800
  • 1c5e9213b0
         Update README.md Angelo Jacobo 2023-07-20 18:47:32 +0800
  • 1f57ee841e
         Update README.md Angelo Jacobo 2023-07-20 18:31:03 +0800
  • 234c587229 working txt for autofpga AngeloJacobo 2023-07-19 18:58:51 +0800
  • 5486aa4429 removed old AngeloJacobo 2023-07-19 18:58:31 +0800
  • 487b026f6c add test to wb2 AngeloJacobo 2023-07-19 18:50:23 +0800
  • c885e3286c update wcfg AngeloJacobo 2023-07-19 18:48:59 +0800
  • 60e40f9d35 less simulation warning AngeloJacobo 2023-07-19 18:48:31 +0800
  • e38859ef78 resolved warning from vivado on IOBDELAY AngeloJacobo 2023-07-19 18:47:24 +0800