formally verify only the controller

2024-05-26 20:27:18 +08:00 · 2024-05-26 20:27:18 +08:00 · fe6919c987
parent 57aebc6eef
commit fe6919c987
1 changed files with 2 additions and 1 deletions
--- a/run_compile.sh
+++ b/run_compile.sh
@ -1,6 +1,7 @@
 # run verilator lint
 echo -e "\e[32mRun Verilator Lint:\e[0m"
-verilator --lint-only ddr3_top.v -Irtl/
+verilator --lint-only rtl/ddr3_controller.v -Irtl/ -Wall
+echo "DONE!"
    

 # run yosys compile