fixed LANES

2024-05-05 21:18:05 +08:00 · 2024-05-05 21:18:05 +08:00 · f1aa850c9c
parent 1d1fd96893
commit f1aa850c9c
1 changed files with 1 additions and 1 deletions
--- a/arty_s7/arty_ddr3.v
+++ b/arty_s7/arty_ddr3.v
@ -112,7 +112,7 @@
        .COL_BITS(10), //width of column address
        .BA_BITS(3), //width of bank address
        .DQ_BITS(8),  //width of DQ
-        .LANES(2), //number of DDR3 modules to be controlled
+        .BYTE_LANES(2), //number of DDR3 modules to be controlled
        .AUX_WIDTH(4), //width of aux line (must be >= 4) 
        .WB2_ADDR_BITS(32), //width of 2nd wishbone address bus 
        .WB2_DATA_BITS(32), //width of 2nd wishbone data bus