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fixed delay for data mask as same delay as dq

This commit is contained in:
AngeloJacobo 2023-06-22 19:53:37 +08:00
parent ef10bfd455
commit d93cf9fb4e
1 changed files with 1 additions and 1 deletions
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testbench/ddr3.v
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@ -508,7 +508,7 @@ module ddr3 (
always @(ras_n ) ras_n_in <= #(BUS_DELAY+FLY_BY_DELAY) ras_n; always @(ras_n ) ras_n_in <= #(BUS_DELAY+FLY_BY_DELAY) ras_n;
always @(cas_n ) cas_n_in <= #(BUS_DELAY+FLY_BY_DELAY) cas_n; always @(cas_n ) cas_n_in <= #(BUS_DELAY+FLY_BY_DELAY) cas_n;
always @(we_n ) we_n_in <= #(BUS_DELAY+FLY_BY_DELAY) we_n; always @(we_n ) we_n_in <= #(BUS_DELAY+FLY_BY_DELAY) we_n;
always @(dm_tdqs) dm_in <= #(BUS_DELAY+FLY_BY_DELAY) dm_tdqs; always @(dm_tdqs) dm_in <= #(BUS_DELAY) dm_tdqs;
always @(ba ) ba_in <= #(BUS_DELAY+FLY_BY_DELAY) ba; always @(ba ) ba_in <= #(BUS_DELAY+FLY_BY_DELAY) ba;
always @(addr ) addr_in <= #(BUS_DELAY+FLY_BY_DELAY) addr; always @(addr ) addr_in <= #(BUS_DELAY+FLY_BY_DELAY) addr;
always @(dq ) dq_in <= #(BUS_DELAY) dq; always @(dq ) dq_in <= #(BUS_DELAY) dq;