luke
/
UberDDR3
mirror of https://github.com/AngeloJacobo/UberDDR3.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

correct clock periods to ps

This commit is contained in:
Angelo Jacobo 2024-04-20 12:26:39 +08:00 committed by GitHub
parent 25685e5769
commit d2f0fd046b
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
1 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
testbench/ddr3_dimm_micron_sim.sv
View File

@ -53,8 +53,8 @@ module ddr3_dimm_micron_sim;
`endif `endif
localparam CONTROLLER_CLK_PERIOD = 10, //ns, period of clock input to this DDR3 controller module localparam CONTROLLER_CLK_PERIOD = 10_000, //ps, period of clock input to this DDR3 controller module
DDR3_CLK_PERIOD = 2.5, //ns, period of clock input to DDR3 RAM device DDR3_CLK_PERIOD = 2500, //ps, period of clock input to DDR3 RAM device
AUX_WIDTH = 16, // AUX lines AUX_WIDTH = 16, // AUX lines
OPT_LOWPOWER = 1, //1 = low power, 0 = low logic OPT_LOWPOWER = 1, //1 = low power, 0 = low logic
OPT_BUS_ABORT = 1; OPT_BUS_ABORT = 1;
@ -126,13 +126,13 @@ module ddr3_dimm_micron_sim;
`else `else
assign clk_locked = 1; assign clk_locked = 1;
always #(CONTROLLER_CLK_PERIOD*1000/2) i_controller_clk = !i_controller_clk; always #(CONTROLLER_CLK_PERIOD/2) i_controller_clk = !i_controller_clk;
always #(DDR3_CLK_PERIOD*1000/2) i_ddr3_clk = !i_ddr3_clk; always #(DDR3_CLK_PERIOD/2) i_ddr3_clk = !i_ddr3_clk;
always #2500 i_ref_clk = !i_ref_clk; always #2500 i_ref_clk = !i_ref_clk;
initial begin //90 degree phase shifted ddr3_clk initial begin //90 degree phase shifted ddr3_clk
#(DDR3_CLK_PERIOD*1000/4); #(DDR3_CLK_PERIOD/4);
while(1) begin while(1) begin
#(DDR3_CLK_PERIOD*1000/2) i_ddr3_clk_90 = !i_ddr3_clk_90; #(DDR3_CLK_PERIOD/2) i_ddr3_clk_90 = !i_ddr3_clk_90;
end end
end end
initial begin initial begin