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changed to picosecond-based instead of nanoseconds

This commit is contained in:
AngeloJacobo 2023-11-14 14:14:16 +08:00
parent 29ec2d0714
commit c2fc70fb6c
1 changed files with 7 additions and 7 deletions
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14
rtl/ddr3_top.v
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@ -2,9 +2,9 @@
`timescale 1ps / 1ps `timescale 1ps / 1ps
module ddr3_top #( module ddr3_top #(
parameter real CONTROLLER_CLK_PERIOD = 10, //ns, clock period of the controller interface parameter CONTROLLER_CLK_PERIOD = 10_000, //ps, clock period of the controller interface
DDR3_CLK_PERIOD = 2.5, //ns, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) DDR3_CLK_PERIOD = 2_500, //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
parameter ROW_BITS = 14, //width of row address ROW_BITS = 14, //width of row address
COL_BITS = 10, //width of column address COL_BITS = 10, //width of column address
BA_BITS = 3, //width of bank address BA_BITS = 3, //width of bank address
DQ_BITS = 8, //width of DQ DQ_BITS = 8, //width of DQ
@ -97,8 +97,8 @@ module ddr3_top #(
//module instantiations //module instantiations
ddr3_controller #( ddr3_controller #(
.CONTROLLER_CLK_PERIOD(CONTROLLER_CLK_PERIOD), //ns, clock period of the controller interface .CONTROLLER_CLK_PERIOD(CONTROLLER_CLK_PERIOD), //ps, clock period of the controller interface
.DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ns, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) .DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
.ODELAY_SUPPORTED(ODELAY_SUPPORTED), //set to 1 when ODELAYE2 is supported .ODELAY_SUPPORTED(ODELAY_SUPPORTED), //set to 1 when ODELAYE2 is supported
.ROW_BITS(ROW_BITS), //width of row address .ROW_BITS(ROW_BITS), //width of row address
.COL_BITS(COL_BITS), //width of column address .COL_BITS(COL_BITS), //width of column address
@ -171,8 +171,8 @@ module ddr3_top #(
.BA_BITS(BA_BITS), //width of bank address .BA_BITS(BA_BITS), //width of bank address
.DQ_BITS(DQ_BITS), //width of DQ .DQ_BITS(DQ_BITS), //width of DQ
.LANES(LANES), //8 lanes of DQ .LANES(LANES), //8 lanes of DQ
.CONTROLLER_CLK_PERIOD(CONTROLLER_CLK_PERIOD), //ns, period of clock input to this DDR3 controller module .CONTROLLER_CLK_PERIOD(CONTROLLER_CLK_PERIOD), //ps, period of clock input to this DDR3 controller module
.DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ns, period of clock input to DDR3 RAM device .DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ps, period of clock input to DDR3 RAM device
.ODELAY_SUPPORTED(ODELAY_SUPPORTED) .ODELAY_SUPPORTED(ODELAY_SUPPORTED)
) ddr3_phy_inst ( ) ddr3_phy_inst (
.i_controller_clk(i_controller_clk), .i_controller_clk(i_controller_clk),