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UberDDR3
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resolve warning from verilator linting

This commit is contained in:
AngeloJacobo 2023-07-16 08:38:20 +08:00
parent 019722bc70
commit b80bda4a46
1 changed files with 1 additions and 1 deletions
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2
rtl/ddr3_phy.v
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@ -99,7 +99,7 @@ module ddr3_phy #(
always @(posedge i_controller_clk, negedge i_rst_n) begin always @(posedge i_controller_clk, negedge i_rst_n) begin
if(!i_rst_n) begin if(!i_rst_n) begin
sync_rst <= 1'b1; sync_rst <= 1'b1;
delay_before_release_reset <= SYNC_RESET_DELAY; delay_before_release_reset <= SYNC_RESET_DELAY[$clog2(SYNC_RESET_DELAY):0];
toggle_dqs_q <= 0; toggle_dqs_q <= 0;
end end
else begin else begin