luke
/
UberDDR3
mirror of https://github.com/AngeloJacobo/UberDDR3.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

clean repo

This commit is contained in:
AngeloJacobo 2024-06-09 11:12:52 +08:00
parent 1ce369cc1f
commit 75531be3c2
15 changed files with 371 additions and 825 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
.gitmodules vendored
View File

@ -1,3 +0,0 @@
[submodule "testbench/ARTY_S7/verilog-uart"]
path = arty_s7/verilog-uart
url = https://github.com/alexforencich/verilog-uart.git

113
arty_s7/uart.v Normal file
View File

@ -0,0 +1,113 @@
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream UART
*/
module uart #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
output wire s_axis_tready,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
input wire m_axis_tready,
/*
* UART interface
*/
input wire rxd,
output wire txd,
/*
* Status
*/
output wire tx_busy,
output wire rx_busy,
output wire rx_overrun_error,
output wire rx_frame_error,
/*
* Configuration
*/
input wire [15:0] prescale
);
uart_tx #(
.DATA_WIDTH(DATA_WIDTH)
)
uart_tx_inst (
.clk(clk),
.rst(rst),
// axi input
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
// output
.txd(txd),
// status
.busy(tx_busy),
// configuration
.prescale(prescale)
);
uart_rx #(
.DATA_WIDTH(DATA_WIDTH)
)
uart_rx_inst (
.clk(clk),
.rst(rst),
// axi output
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
// input
.rxd(rxd),
// status
.busy(rx_busy),
.overrun_error(rx_overrun_error),
.frame_error(rx_frame_error),
// configuration
.prescale(prescale)
);
endmodule

142
arty_s7/uart_rx.v Normal file
View File

@ -0,0 +1,142 @@
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream UART
*/
module uart_rx #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
input wire m_axis_tready,
/*
* UART interface
*/
input wire rxd,
/*
* Status
*/
output wire busy,
output wire overrun_error,
output wire frame_error,
/*
* Configuration
*/
input wire [15:0] prescale
);
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = 0;
reg m_axis_tvalid_reg = 0;
reg rxd_reg = 1;
reg busy_reg = 0;
reg overrun_error_reg = 0;
reg frame_error_reg = 0;
reg [DATA_WIDTH-1:0] data_reg = 0;
reg [18:0] prescale_reg = 0;
reg [3:0] bit_cnt = 0;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tvalid = m_axis_tvalid_reg;
assign busy = busy_reg;
assign overrun_error = overrun_error_reg;
assign frame_error = frame_error_reg;
always @(posedge clk) begin
if (rst) begin
m_axis_tdata_reg <= 0;
m_axis_tvalid_reg <= 0;
rxd_reg <= 1;
prescale_reg <= 0;
bit_cnt <= 0;
busy_reg <= 0;
overrun_error_reg <= 0;
frame_error_reg <= 0;
end else begin
rxd_reg <= rxd;
overrun_error_reg <= 0;
frame_error_reg <= 0;
if (m_axis_tvalid && m_axis_tready) begin
m_axis_tvalid_reg <= 0;
end
if (prescale_reg > 0) begin
prescale_reg <= prescale_reg - 1;
end else if (bit_cnt > 0) begin
if (bit_cnt > DATA_WIDTH+1) begin
if (!rxd_reg) begin
bit_cnt <= bit_cnt - 1;
prescale_reg <= (prescale << 3)-1;
end else begin
bit_cnt <= 0;
prescale_reg <= 0;
end
end else if (bit_cnt > 1) begin
bit_cnt <= bit_cnt - 1;
prescale_reg <= (prescale << 3)-1;
data_reg <= {rxd_reg, data_reg[DATA_WIDTH-1:1]};
end else if (bit_cnt == 1) begin
bit_cnt <= bit_cnt - 1;
if (rxd_reg) begin
m_axis_tdata_reg <= data_reg;
m_axis_tvalid_reg <= 1;
overrun_error_reg <= m_axis_tvalid_reg;
end else begin
frame_error_reg <= 1;
end
end
end else begin
busy_reg <= 0;
if (!rxd_reg) begin
prescale_reg <= (prescale << 2)-2;
bit_cnt <= DATA_WIDTH+2;
data_reg <= 0;
busy_reg <= 1;
end
end
end
end
endmodule

115
arty_s7/uart_tx.v Normal file
View File

@ -0,0 +1,115 @@
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream UART
*/
module uart_tx #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
output wire s_axis_tready,
/*
* UART interface
*/
output wire txd,
/*
* Status
*/
output wire busy,
/*
* Configuration
*/
input wire [15:0] prescale
);
reg s_axis_tready_reg = 0;
reg txd_reg = 1;
reg busy_reg = 0;
reg [DATA_WIDTH:0] data_reg = 0;
reg [18:0] prescale_reg = 0;
reg [3:0] bit_cnt = 0;
assign s_axis_tready = s_axis_tready_reg;
assign txd = txd_reg;
assign busy = busy_reg;
always @(posedge clk) begin
if (rst) begin
s_axis_tready_reg <= 0;
txd_reg <= 1;
prescale_reg <= 0;
bit_cnt <= 0;
busy_reg <= 0;
end else begin
if (prescale_reg > 0) begin
s_axis_tready_reg <= 0;
prescale_reg <= prescale_reg - 1;
end else if (bit_cnt == 0) begin
s_axis_tready_reg <= 1;
busy_reg <= 0;
if (s_axis_tvalid) begin
s_axis_tready_reg <= !s_axis_tready_reg;
prescale_reg <= (prescale << 3)-1;
bit_cnt <= DATA_WIDTH+1;
data_reg <= {1'b1, s_axis_tdata};
txd_reg <= 0;
busy_reg <= 1;
end
end else begin
if (bit_cnt > 1) begin
bit_cnt <= bit_cnt - 1;
prescale_reg <= (prescale << 3)-1;
{data_reg, txd_reg} <= {1'b0, data_reg};
end else if (bit_cnt == 1) begin
bit_cnt <= bit_cnt - 1;
prescale_reg <= (prescale << 3);
txd_reg <= 1;
end
end
end
end
endmodule

1
arty_s7/verilog-uart

@ -1 +0,0 @@
Subproject commit 1363dc76788527bf6017dd5294593f42162133e2

0
ddr3.sby → ddr3_multiconfig.sby
View File

660
formal.gtkw
View File

@ -1,660 +0,0 @@
[*]
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
[*] Thu Sep 14 06:23:44 2023
[*]
[dumpfile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/ddr3_controller/engine_0/trace_induct.vcd"
[dumpfile_mtime] "Thu Sep 14 06:21:18 2023"
[dumpfile_size] 165043
[savefile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/formal.gtkw"
[timestart] 0
[size] 1848 1126
[pos] -1 -1
*-4.925239 67 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] ddr3_controller.
[treeopen] ddr3_controller.wb_properties.
[sst_width] 391
[signals_width] 541
[sst_expanded] 1
[sst_vpaned_height] 743
@420
smt_step
@28
ddr3_controller.i_controller_clk
ddr3_controller.i_rst_n
ddr3_controller.reset_done
@24
ddr3_controller.instruction_address[4:0]
ddr3_controller.delay_counter[15:0]
@28
ddr3_controller.o_wb_stall_q
ddr3_controller.i_wb_cyc
@22
ddr3_controller.stage2_aux[15:0]
@28
ddr3_controller.pause_counter
@24
ddr3_controller.state_calibrate[5:0]
@28
ddr3_controller.past_sync_rst_controller
ddr3_controller.sync_rst_controller
@29
+{ddr3_controller.[ACT] cmd_d<0>[23:0]} ddr3_controller.cmd_d<0>[23:0]
@c00029
+{ddr3_controller.[PRE] cmd_d<1>[23:0]} ddr3_controller.cmd_d<1>[23:0]
@29
(0)ddr3_controller.cmd_d<1>[23:0]
(1)ddr3_controller.cmd_d<1>[23:0]
(2)ddr3_controller.cmd_d<1>[23:0]
(3)ddr3_controller.cmd_d<1>[23:0]
(4)ddr3_controller.cmd_d<1>[23:0]
(5)ddr3_controller.cmd_d<1>[23:0]
(6)ddr3_controller.cmd_d<1>[23:0]
(7)ddr3_controller.cmd_d<1>[23:0]
(8)ddr3_controller.cmd_d<1>[23:0]
(9)ddr3_controller.cmd_d<1>[23:0]
(10)ddr3_controller.cmd_d<1>[23:0]
(11)ddr3_controller.cmd_d<1>[23:0]
(12)ddr3_controller.cmd_d<1>[23:0]
(13)ddr3_controller.cmd_d<1>[23:0]
(14)ddr3_controller.cmd_d<1>[23:0]
(15)ddr3_controller.cmd_d<1>[23:0]
(16)ddr3_controller.cmd_d<1>[23:0]
(17)ddr3_controller.cmd_d<1>[23:0]
(18)ddr3_controller.cmd_d<1>[23:0]
(19)ddr3_controller.cmd_d<1>[23:0]
(20)ddr3_controller.cmd_d<1>[23:0]
(21)ddr3_controller.cmd_d<1>[23:0]
(22)ddr3_controller.cmd_d<1>[23:0]
(23)ddr3_controller.cmd_d<1>[23:0]
@1401201
-group_end
@c00029
+{ddr3_controller.[RD] cmd_d<2>[23:0]} ddr3_controller.cmd_d<2>[23:0]
@29
(0)ddr3_controller.cmd_d<2>[23:0]
(1)ddr3_controller.cmd_d<2>[23:0]
(2)ddr3_controller.cmd_d<2>[23:0]
(3)ddr3_controller.cmd_d<2>[23:0]
(4)ddr3_controller.cmd_d<2>[23:0]
(5)ddr3_controller.cmd_d<2>[23:0]
(6)ddr3_controller.cmd_d<2>[23:0]
(7)ddr3_controller.cmd_d<2>[23:0]
(8)ddr3_controller.cmd_d<2>[23:0]
(9)ddr3_controller.cmd_d<2>[23:0]
(10)ddr3_controller.cmd_d<2>[23:0]
(11)ddr3_controller.cmd_d<2>[23:0]
(12)ddr3_controller.cmd_d<2>[23:0]
(13)ddr3_controller.cmd_d<2>[23:0]
(14)ddr3_controller.cmd_d<2>[23:0]
(15)ddr3_controller.cmd_d<2>[23:0]
(16)ddr3_controller.cmd_d<2>[23:0]
(17)ddr3_controller.cmd_d<2>[23:0]
(18)ddr3_controller.cmd_d<2>[23:0]
(19)ddr3_controller.cmd_d<2>[23:0]
(20)ddr3_controller.cmd_d<2>[23:0]
(21)ddr3_controller.cmd_d<2>[23:0]
(22)ddr3_controller.cmd_d<2>[23:0]
(23)ddr3_controller.cmd_d<2>[23:0]
@1401201
-group_end
@29
+{ddr3_controller.[WR] cmd_d<3>[23:0]} ddr3_controller.cmd_d<3>[23:0]
@28
ddr3_controller.f_aux_ack_pipe_after_stage2<0>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<1>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<2>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<3>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<4>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<5>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<6>[16:0]
@22
ddr3_controller.o_wb_ack_read_q<0>[16:0]
ddr3_controller.o_wb_ack_read_q<1>[16:0]
ddr3_controller.o_wb_ack_read_q<2>[16:0]
ddr3_controller.o_wb_ack_read_q<3>[16:0]
ddr3_controller.o_wb_ack_read_q<4>[16:0]
ddr3_controller.o_wb_ack_read_q<5>[16:0]
ddr3_controller.o_wb_ack_read_q<6>[16:0]
ddr3_controller.o_wb_ack_read_q<7>[16:0]
ddr3_controller.o_wb_ack_read_q<8>[16:0]
ddr3_controller.o_wb_ack_read_q<9>[16:0]
ddr3_controller.o_wb_ack_read_q<a>[16:0]
ddr3_controller.o_wb_ack_read_q<b>[16:0]
ddr3_controller.o_wb_ack_read_q<c>[16:0]
ddr3_controller.o_wb_ack_read_q<d>[16:0]
ddr3_controller.o_wb_ack_read_q<e>[16:0]
ddr3_controller.o_wb_ack_read_q<f>[16:0]
@24
ddr3_controller.f_sum_of_pending_acks[15:0]
@28
ddr3_controller.stage1_pending
ddr3_controller.stage2_pending
@22
ddr3_controller.o_wb_ack_read_q<0>[16:0]
ddr3_controller.o_wb_ack_read_q<1>[16:0]
ddr3_controller.o_wb_ack_read_q<2>[16:0]
ddr3_controller.calib_addr[23:0]
ddr3_controller.calib_addr_plus_anticipate[23:0]
ddr3_controller.calib_aux[15:0]
ddr3_controller.calib_data[511:0]
ddr3_controller.calib_sel[63:0]
@28
ddr3_controller.calib_stb
ddr3_controller.calib_we
@200
-
@28
ddr3_controller.wb_properties.i_wb_cyc
@22
ddr3_controller.wb_properties.f_outstanding[3:0]
ddr3_controller.wb_properties.f_nacks[3:0]
ddr3_controller.wb_properties.f_nreqs[3:0]
@28
ddr3_controller.wb_properties.i_wb_ack
ddr3_controller.wb_properties.i_wb_err
@200
-
@28
ddr3_controller.fifo_1.empty
@24
ddr3_controller.fifo_1.fifo_reg<0>[24:0]
ddr3_controller.fifo_1.fifo_reg<1>[24:0]
@28
ddr3_controller.fifo_1.full
ddr3_controller.fifo_1.i_clk
ddr3_controller.fifo_1.i_rst_n
@22
ddr3_controller.fifo_1.read_data[24:0]
ddr3_controller.fifo_1.read_data_next[24:0]
@28
ddr3_controller.fifo_1.read_fifo
ddr3_controller.fifo_1.read_pointer
@22
ddr3_controller.fifo_1.write_data[24:0]
@28
ddr3_controller.fifo_1.write_fifo
ddr3_controller.fifo_1.write_pointer
@200
-
@28
ddr3_controller.f_read_fifo
ddr3_controller.f_write_fifo
ddr3_controller.o_wb_stall
ddr3_controller.i_wb_stb
ddr3_controller.stage1_pending
ddr3_controller.stage2_pending
@200
-
@28
ddr3_controller.f_empty
@22
ddr3_controller.calib_aux[15:0]
ddr3_controller.calib_data[511:0]
ddr3_controller.calib_sel[63:0]
@28
ddr3_controller.calib_stb
ddr3_controller.calib_we
@24
ddr3_controller.calib_addr[23:0]
@28
ddr3_controller.bank_status_q[7:0]
ddr3_controller.f_bank_status[7:0]
@200
-
@22
ddr3_controller.delay_before_activate_counter_q<1>[3:0]
ddr3_controller.delay_before_precharge_counter_q<1>[3:0]
ddr3_controller.delay_before_read_counter_q<1>[3:0]
ddr3_controller.delay_before_write_counter_q<1>[3:0]
@200
-
@24
ddr3_controller.stage1_bank[2:0]
ddr3_controller.stage2_bank[2:0]
@c00024
ddr3_controller.stage1_next_bank[2:0]
@28
(0)ddr3_controller.stage1_next_bank[2:0]
(1)ddr3_controller.stage1_next_bank[2:0]
(2)ddr3_controller.stage1_next_bank[2:0]
@1401200
-group_end
@200
-
@24
ddr3_controller.f_sum_of_pending_acks[15:0]
ddr3_controller.wb_properties.f_ackwait_count[3:0]
@28
ddr3_controller.f_ack_pipe_after_stage2[6:0]
ddr3_controller.delay_counter_is_zero
@200
-
@28
ddr3_controller.stage1_pending
ddr3_controller.stage2_pending
ddr3_controller.shift_reg_read_pipe_q<4>[16:0]
ddr3_controller.shift_reg_read_pipe_q<3>[16:0]
@c00028
ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
@28
(0)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(1)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(2)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(3)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(4)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(5)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(6)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(7)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(8)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(9)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(10)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(11)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(12)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(13)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(14)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(15)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(16)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
@1401200
-group_end
@c00028
ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
@28
(0)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(1)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(2)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(3)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(4)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(5)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(6)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(7)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(8)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(9)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(10)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(11)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(12)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(13)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(14)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(15)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(16)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
@1401200
-group_end
@28
ddr3_controller.shift_reg_read_pipe_q<0>[16:0]
@22
ddr3_controller.o_wb_ack_read_q<1>[16:0]
ddr3_controller.o_wb_ack_read_q<0>[16:0]
@200
-
@28
ddr3_controller.f_bank_status[7:0]
ddr3_controller.bank_status_q[7:0]
@22
ddr3_controller.bank[31:0]
@200
-
@22
ddr3_controller.bank[31:0]
@200
-
@28
ddr3_controller.fifo_1.read_pointer
ddr3_controller.fifo_1.write_pointer
@24
ddr3_controller.wb_properties.f_outstanding[3:0]
ddr3_controller.f_sum_of_pending_acks[15:0]
@28
ddr3_controller.wb_properties.i_wb_cyc
@200
-
@28
ddr3_controller.i_wb_stb
ddr3_controller.o_wb_stall
ddr3_controller.i_wb_cyc
ddr3_controller.o_wb_ack
ddr3_controller.o_wb_stall_d
ddr3_controller.o_wb_stall_q
ddr3_controller.delay_counter_is_zero
@200
-
@28
ddr3_controller.stage1_stall
ddr3_controller.stage1_pending
ddr3_controller.stage1_we
@22
ddr3_controller.stage1_aux[15:0]
@24
ddr3_controller.stage1_bank[2:0]
@22
ddr3_controller.stage1_col[9:0]
ddr3_controller.stage1_row[13:0]
@200
-
@28
ddr3_controller.stage2_stall
ddr3_controller.stage2_pending
ddr3_controller.stage2_update
ddr3_controller.stage2_we
@c00022
ddr3_controller.stage2_aux[15:0]
@28
(0)ddr3_controller.stage2_aux[15:0]
(1)ddr3_controller.stage2_aux[15:0]
(2)ddr3_controller.stage2_aux[15:0]
(3)ddr3_controller.stage2_aux[15:0]
(4)ddr3_controller.stage2_aux[15:0]
(5)ddr3_controller.stage2_aux[15:0]
(6)ddr3_controller.stage2_aux[15:0]
(7)ddr3_controller.stage2_aux[15:0]
(8)ddr3_controller.stage2_aux[15:0]
(9)ddr3_controller.stage2_aux[15:0]
(10)ddr3_controller.stage2_aux[15:0]
(11)ddr3_controller.stage2_aux[15:0]
(12)ddr3_controller.stage2_aux[15:0]
(13)ddr3_controller.stage2_aux[15:0]
(14)ddr3_controller.stage2_aux[15:0]
(15)ddr3_controller.stage2_aux[15:0]
@1401200
-group_end
@24
ddr3_controller.stage2_bank[2:0]
@22
ddr3_controller.stage2_col[9:0]
ddr3_controller.stage2_row[13:0]
@200
-
@28
+{ddr3_controller.[ACT] cmd_d<0>[23:0]} ddr3_controller.cmd_d<0>[23:0]
@c00028
+{ddr3_controller.[PRE] cmd_d<1>[23:0]} ddr3_controller.cmd_d<1>[23:0]
@28
(0)ddr3_controller.cmd_d<1>[23:0]
(1)ddr3_controller.cmd_d<1>[23:0]
(2)ddr3_controller.cmd_d<1>[23:0]
(3)ddr3_controller.cmd_d<1>[23:0]
(4)ddr3_controller.cmd_d<1>[23:0]
(5)ddr3_controller.cmd_d<1>[23:0]
(6)ddr3_controller.cmd_d<1>[23:0]
(7)ddr3_controller.cmd_d<1>[23:0]
(8)ddr3_controller.cmd_d<1>[23:0]
(9)ddr3_controller.cmd_d<1>[23:0]
(10)ddr3_controller.cmd_d<1>[23:0]
(11)ddr3_controller.cmd_d<1>[23:0]
(12)ddr3_controller.cmd_d<1>[23:0]
(13)ddr3_controller.cmd_d<1>[23:0]
(14)ddr3_controller.cmd_d<1>[23:0]
(15)ddr3_controller.cmd_d<1>[23:0]
(16)ddr3_controller.cmd_d<1>[23:0]
(17)ddr3_controller.cmd_d<1>[23:0]
(18)ddr3_controller.cmd_d<1>[23:0]
(19)ddr3_controller.cmd_d<1>[23:0]
(20)ddr3_controller.cmd_d<1>[23:0]
(21)ddr3_controller.cmd_d<1>[23:0]
(22)ddr3_controller.cmd_d<1>[23:0]
(23)ddr3_controller.cmd_d<1>[23:0]
@1401200
-group_end
@c00028
+{ddr3_controller.[RD] cmd_d<2>[23:0]} ddr3_controller.cmd_d<2>[23:0]
@28
(0)ddr3_controller.cmd_d<2>[23:0]
(1)ddr3_controller.cmd_d<2>[23:0]
(2)ddr3_controller.cmd_d<2>[23:0]
(3)ddr3_controller.cmd_d<2>[23:0]
(4)ddr3_controller.cmd_d<2>[23:0]
(5)ddr3_controller.cmd_d<2>[23:0]
(6)ddr3_controller.cmd_d<2>[23:0]
(7)ddr3_controller.cmd_d<2>[23:0]
(8)ddr3_controller.cmd_d<2>[23:0]
(9)ddr3_controller.cmd_d<2>[23:0]
(10)ddr3_controller.cmd_d<2>[23:0]
(11)ddr3_controller.cmd_d<2>[23:0]
(12)ddr3_controller.cmd_d<2>[23:0]
(13)ddr3_controller.cmd_d<2>[23:0]
(14)ddr3_controller.cmd_d<2>[23:0]
(15)ddr3_controller.cmd_d<2>[23:0]
(16)ddr3_controller.cmd_d<2>[23:0]
(17)ddr3_controller.cmd_d<2>[23:0]
(18)ddr3_controller.cmd_d<2>[23:0]
(19)ddr3_controller.cmd_d<2>[23:0]
(20)ddr3_controller.cmd_d<2>[23:0]
(21)ddr3_controller.cmd_d<2>[23:0]
(22)ddr3_controller.cmd_d<2>[23:0]
(23)ddr3_controller.cmd_d<2>[23:0]
@1401200
-group_end
@28
+{ddr3_controller.[WR] cmd_d<3>[23:0]} ddr3_controller.cmd_d<3>[23:0]
@200
-
@24
ddr3_controller.wb_properties.f_nacks[3:0]
ddr3_controller.wb_properties.f_nreqs[3:0]
@28
ddr3_controller.stage2_update
@200
-
-
@22
ddr3_controller.f_aux_ack_pipe_after_stage2<0>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<1>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<2>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<3>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<4>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<5>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<6>[16:0]
@200
-
@22
ddr3_controller.o_wb_ack_read_q<2>[16:0]
ddr3_controller.o_wb_ack_read_q<3>[16:0]
ddr3_controller.o_wb_ack_read_q<4>[16:0]
ddr3_controller.o_wb_ack_read_q<5>[16:0]
ddr3_controller.o_wb_ack_read_q<6>[16:0]
ddr3_controller.o_wb_ack_read_q<7>[16:0]
ddr3_controller.o_wb_ack_read_q<8>[16:0]
ddr3_controller.o_wb_ack_read_q<9>[16:0]
@24
ddr3_controller.added_read_pipe_max[3:0]
@28
ddr3_controller.o_wb_ack
@200
-
@28
ddr3_controller.o_wb_ack
ddr3_controller.fifo_1.empty
ddr3_controller.fifo_1.full
ddr3_controller.fifo_1.empty
ddr3_controller.fifo_1.full
ddr3_controller.fifo_1.read_fifo
ddr3_controller.fifo_1.write_fifo
ddr3_controller.fifo_1.read_pointer
ddr3_controller.fifo_1.write_pointer
@200
-
@24
ddr3_controller.added_read_pipe_max[3:0]
@200
-
@22
ddr3_controller.i_aux[15:0]
ddr3_controller.o_aux[15:0]
@200
-
@22
ddr3_controller.stage1_aux[15:0]
ddr3_controller.stage2_aux[15:0]
ddr3_controller.write_pattern[127:0]
ddr3_controller.o_wb_ack_read_q<0>[16:0]
ddr3_controller.o_wb_ack_read_q<1>[16:0]
ddr3_controller.shift_reg_read_pipe_q<0>[16:0]
ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
ddr3_controller.shift_reg_read_pipe_q<3>[16:0]
ddr3_controller.shift_reg_read_pipe_q<4>[16:0]
ddr3_controller.shift_reg_read_pipe_d<0>[16:0]
ddr3_controller.shift_reg_read_pipe_d<1>[16:0]
ddr3_controller.shift_reg_read_pipe_d<2>[16:0]
ddr3_controller.shift_reg_read_pipe_d<3>[16:0]
@200
-
@28
ddr3_controller.fifo_1.i_rst_n
@200
-
@28
ddr3_controller.o_wb_stall
ddr3_controller.o_wb_stall_d
ddr3_controller.i_wb_cyc
ddr3_controller.i_wb_stb
ddr3_controller.i_wb_we
@24
ddr3_controller.o_wb_ack
@200
-
@24
ddr3_controller.f_activate_slot[1:0]
ddr3_controller.f_precharge_slot[1:0]
ddr3_controller.f_read_slot[1:0]
ddr3_controller.f_write_slot[1:0]
@28
ddr3_controller.f_read_fifo
ddr3_controller.f_write_fifo
ddr3_controller.i_wb_cyc
ddr3_controller.f_empty
ddr3_controller.fifo_1.empty
ddr3_controller.f_full
@200
-
@24
ddr3_controller.delay_counter[15:0]
ddr3_controller.stage1_bank[2:0]
ddr3_controller.stage2_bank[2:0]
@28
ddr3_controller.stage1_we
ddr3_controller.stage2_we
ddr3_controller.issue_read_command
ddr3_controller.issue_write_command
@200
-
@28
ddr3_controller.bank_status_q[7:0]
@22
ddr3_controller.delay_before_write_counter_q<1>[3:0]
ddr3_controller.delay_before_read_counter_q<7>[3:0]
ddr3_controller.delay_before_write_counter_q<7>[3:0]
ddr3_controller.delay_before_activate_counter_q<7>[3:0]
ddr3_controller.delay_before_write_counter_q<7>[3:0]
ddr3_controller.delay_before_precharge_counter_q<7>[3:0]
@200
-
@22
ddr3_controller.delay_before_activate_counter_q<0>[3:0]
ddr3_controller.delay_before_activate_counter_q<1>[3:0]
ddr3_controller.delay_before_activate_counter_q<2>[3:0]
ddr3_controller.delay_before_activate_counter_q<3>[3:0]
ddr3_controller.delay_before_activate_counter_q<4>[3:0]
ddr3_controller.delay_before_activate_counter_q<5>[3:0]
ddr3_controller.delay_before_activate_counter_q<6>[3:0]
ddr3_controller.delay_before_activate_counter_q<7>[3:0]
ddr3_controller.delay_before_precharge_counter_q<0>[3:0]
ddr3_controller.delay_before_precharge_counter_q<1>[3:0]
ddr3_controller.delay_before_precharge_counter_q<2>[3:0]
ddr3_controller.delay_before_precharge_counter_q<3>[3:0]
ddr3_controller.delay_before_precharge_counter_q<4>[3:0]
ddr3_controller.delay_before_precharge_counter_q<5>[3:0]
ddr3_controller.delay_before_precharge_counter_q<6>[3:0]
ddr3_controller.delay_before_precharge_counter_q<7>[3:0]
ddr3_controller.delay_before_read_counter_q<0>[3:0]
ddr3_controller.delay_before_read_counter_q<1>[3:0]
ddr3_controller.delay_before_read_counter_q<2>[3:0]
ddr3_controller.delay_before_read_counter_q<3>[3:0]
ddr3_controller.delay_before_read_counter_q<4>[3:0]
ddr3_controller.delay_before_read_counter_q<5>[3:0]
ddr3_controller.delay_before_read_counter_q<6>[3:0]
ddr3_controller.delay_before_read_counter_q<7>[3:0]
ddr3_controller.delay_before_write_counter_q<0>[3:0]
ddr3_controller.delay_before_write_counter_q<1>[3:0]
ddr3_controller.delay_before_write_counter_q<2>[3:0]
ddr3_controller.delay_before_write_counter_q<3>[3:0]
ddr3_controller.delay_before_write_counter_q<4>[3:0]
ddr3_controller.delay_before_write_counter_q<5>[3:0]
ddr3_controller.delay_before_write_counter_q<6>[3:0]
ddr3_controller.delay_before_write_counter_q<7>[3:0]
@200
-
@22
ddr3_controller.delay_before_activate_counter_q<4>[3:0]
ddr3_controller.delay_before_precharge_counter_q<4>[3:0]
ddr3_controller.delay_before_read_counter_q<4>[3:0]
ddr3_controller.delay_before_write_counter_q<4>[3:0]
@200
-
@28
ddr3_controller.cmd_odt
@24
ddr3_controller.instruction_address[4:0]
@28
ddr3_controller.stage1_pending
ddr3_controller.stage1_we
ddr3_controller.stage2_pending
ddr3_controller.stage2_we
@24
ddr3_controller.stage1_bank[2:0]
ddr3_controller.stage2_bank[2:0]
@22
ddr3_controller.delay_before_write_counter_q<4>[3:0]
ddr3_controller.delay_before_read_counter_q<4>[3:0]
@28
ddr3_controller.o_wb_stall_d
@24
ddr3_controller.stage1_col[9:0]
ddr3_controller.stage1_row[13:0]
ddr3_controller.stage2_row[13:0]
ddr3_controller.stage1_next_bank[2:0]
@c00024
ddr3_controller.stage1_next_row[13:0]
@28
(0)ddr3_controller.stage1_next_row[13:0]
(1)ddr3_controller.stage1_next_row[13:0]
(2)ddr3_controller.stage1_next_row[13:0]
(3)ddr3_controller.stage1_next_row[13:0]
(4)ddr3_controller.stage1_next_row[13:0]
(5)ddr3_controller.stage1_next_row[13:0]
(6)ddr3_controller.stage1_next_row[13:0]
(7)ddr3_controller.stage1_next_row[13:0]
(8)ddr3_controller.stage1_next_row[13:0]
(9)ddr3_controller.stage1_next_row[13:0]
(10)ddr3_controller.stage1_next_row[13:0]
(11)ddr3_controller.stage1_next_row[13:0]
(12)ddr3_controller.stage1_next_row[13:0]
(13)ddr3_controller.stage1_next_row[13:0]
@1401200
-group_end
@200
-
@22
ddr3_controller.delay_before_activate_counter_q<0>[3:0]
ddr3_controller.delay_before_activate_counter_q<1>[3:0]
@200
-
@22
ddr3_controller.delay_before_precharge_counter_q<0>[3:0]
ddr3_controller.delay_before_precharge_counter_q<1>[3:0]
@200
-
@22
ddr3_controller.delay_before_read_counter_q<0>[3:0]
ddr3_controller.delay_before_read_counter_q<1>[3:0]
@200
-
@24
ddr3_controller.bank_active_row_q<0>[13:0]
ddr3_controller.bank_active_row_q<1>[13:0]
ddr3_controller.bank_active_row_q<2>[13:0]
ddr3_controller.bank_active_row_q<3>[13:0]
ddr3_controller.bank_active_row_q<4>[13:0]
ddr3_controller.bank_active_row_q<5>[13:0]
ddr3_controller.bank_active_row_q<6>[13:0]
ddr3_controller.bank_active_row_q<7>[13:0]
[pattern_trace] 1
[pattern_trace] 0

160
formal_wb2.gtkw
View File

@ -1,160 +0,0 @@
[*]
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
[*] Tue Jul 11 12:39:11 2023
[*]
[timestart] 0
[size] 1848 1126
[pos] -1 -1
*-4.757294 10 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] ddr3_controller.
[sst_width] 297
[signals_width] 395
[sst_expanded] 1
[sst_vpaned_height] 743
@28
ddr3_controller.i_controller_clk
ddr3_controller.i_rst_n
@24
ddr3_controller.state_calibrate[4:0]
@200
-
@28
ddr3_controller.wb2_properties.i_wb_cyc
@22
ddr3_controller.wb2_properties.f_nacks[3:0]
ddr3_controller.wb2_properties.f_nreqs[3:0]
ddr3_controller.wb2_properties.f_outstanding[3:0]
ddr3_controller.f_outstanding_2[3:0]
@200
-
-
@28
ddr3_controller.i_wb2_addr[31:0]
[color] 2
ddr3_controller.i_wb2_cyc
ddr3_controller.i_wb2_data[31:0]
[color] 2
ddr3_controller.i_wb2_stb
[color] 2
ddr3_controller.i_wb2_we
[color] 2
ddr3_controller.o_wb2_ack
ddr3_controller.o_wb2_data[31:0]
ddr3_controller.o_wb2_stall
@200
-
@28
[color] 4
ddr3_controller.f_delay_ld[7:0]
[color] 4
ddr3_controller.o_phy_idelay_data_ld[7:0]
[color] 4
ddr3_controller.o_phy_idelay_dqs_ld[7:0]
[color] 4
ddr3_controller.o_phy_odelay_data_ld[7:0]
[color] 4
ddr3_controller.o_phy_odelay_dqs_ld[7:0]
ddr3_controller.o_phy_idelay_data_cntvaluein[4:0]
ddr3_controller.o_phy_idelay_dqs_cntvaluein[4:0]
ddr3_controller.o_phy_odelay_data_cntvaluein[4:0]
ddr3_controller.o_phy_odelay_dqs_cntvaluein[4:0]
@200
-
@22
ddr3_controller.odelay_data_cntvaluein<0>[4:0]
ddr3_controller.odelay_data_cntvaluein<1>[4:0]
ddr3_controller.odelay_data_cntvaluein<2>[4:0]
ddr3_controller.odelay_data_cntvaluein<3>[4:0]
ddr3_controller.odelay_data_cntvaluein<4>[4:0]
ddr3_controller.odelay_data_cntvaluein<5>[4:0]
@28
ddr3_controller.odelay_data_cntvaluein<6>[4:0]
@22
ddr3_controller.odelay_data_cntvaluein<7>[4:0]
@200
-
@28
[color] 4
ddr3_controller.wb2_addr[31:0]
[color] 4
ddr3_controller.wb2_data[31:0]
@22
[color] 4
ddr3_controller.wb2_phy_idelay_data_cntvaluein[4:0]
@28
[color] 4
ddr3_controller.wb2_phy_idelay_data_ld[7:0]
@22
[color] 4
ddr3_controller.wb2_phy_idelay_dqs_cntvaluein[4:0]
@c00028
[color] 4
ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
@28
(0)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
(1)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
(2)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
(3)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
(4)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
(5)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
(6)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
(7)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
@1401200
-group_end
@22
[color] 4
ddr3_controller.wb2_phy_odelay_data_cntvaluein[4:0]
@28
[color] 4
ddr3_controller.wb2_phy_odelay_data_ld[7:0]
@c00028
[color] 4
ddr3_controller.f_delay_ld[7:0]
@28
(0)ddr3_controller.f_delay_ld[7:0]
(1)ddr3_controller.f_delay_ld[7:0]
(2)ddr3_controller.f_delay_ld[7:0]
(3)ddr3_controller.f_delay_ld[7:0]
(4)ddr3_controller.f_delay_ld[7:0]
(5)ddr3_controller.f_delay_ld[7:0]
(6)ddr3_controller.f_delay_ld[7:0]
(7)ddr3_controller.f_delay_ld[7:0]
@1401200
-group_end
@22
[color] 4
ddr3_controller.wb2_phy_odelay_dqs_cntvaluein[4:0]
@28
[color] 4
ddr3_controller.wb2_phy_odelay_dqs_ld[7:0]
[color] 2
ddr3_controller.wb2_stb
[color] 4
ddr3_controller.wb2_update
[color] 2
ddr3_controller.wb2_we
[color] 4
ddr3_controller.wb2_write_lane[2:0]
[color] 2
ddr3_controller.f_o_wb2_ack_q
ddr3_controller.f_read_data_2[12:0]
ddr3_controller.f_read_data_2_q[12:0]
@200
-
@28
ddr3_controller.fifo_2.read_fifo
ddr3_controller.f_read_fifo_2
[color] 2
ddr3_controller.fifo_2.write_fifo
[color] 2
ddr3_controller.fifo_2.empty
[color] 2
ddr3_controller.fifo_2.full
@29
ddr3_controller.f_full_2
@28
ddr3_controller.fifo_2.read_pointer
ddr3_controller.fifo_2.write_pointer
[pattern_trace] 1
[pattern_trace] 0

0
kintex_switch_files/ddr3.txt → klusterlab/ddr3.txt
View File

0
kintex_switch_files/ddr3scope.txt → klusterlab/ddr3scope.txt
View File

0
kintex_switch_files/ddr3scope1.cpp → klusterlab/ddr3scope1.cpp
View File

0
kintex_switch_files/ddr3scope2.cpp → klusterlab/ddr3scope2.cpp
View File

0
kintex_switch_files/ddr3scope3.cpp → klusterlab/ddr3scope3.cpp
View File

0
kintex_switch_files/kluster.xdc → klusterlab/kluster.xdc
View File

2
run_compile.sh
View File

@ -25,7 +25,7 @@ echo
echo "" echo ""
echo -e "\e[32mRun Symbiyosys Formal Verification:\e[0m" echo -e "\e[32mRun Symbiyosys Formal Verification:\e[0m"
echo "---------------------------------------" echo "---------------------------------------"
sby -f ddr3.sby sby -f ddr3_multiconfig.sby
# ANSI color codes # ANSI color codes