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UberDDR3
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less simulation warning

This commit is contained in:
AngeloJacobo 2023-07-19 18:48:31 +08:00
parent e38859ef78
commit 60e40f9d35
1 changed files with 2 additions and 1 deletions
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rtl/ddr3_top.v
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@ -1,5 +1,6 @@
`default_nettype none `default_nettype none
`timescale 1ps / 1ps
module ddr3_top #( module ddr3_top #(
parameter real CONTROLLER_CLK_PERIOD = 10, //ns, period of clock input to this DDR3 controller module parameter real CONTROLLER_CLK_PERIOD = 10, //ns, period of clock input to this DDR3 controller module
DDR3_CLK_PERIOD = 2.5, //ns, period of clock input to DDR3 RAM device DDR3_CLK_PERIOD = 2.5, //ns, period of clock input to DDR3 RAM device