luke
/
UberDDR3
mirror of https://github.com/AngeloJacobo/UberDDR3.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

add UART to ax7325b board, make openFPGAloader works on ax7325b board

This commit is contained in:
AngeloJacobo 2025-03-14 15:23:34 +08:00
parent 75e42476f5
commit 5ab1ac5d42
2 changed files with 31 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
example_demo/alinx_ax7325b/Makefile
View File

@ -26,7 +26,7 @@ TOP_VERILOG ?= ${TOP}.v
PNR_DEBUG ?= # --verbose --debug
BOARD ?= UNKNOWN
JTAG_LINK ?= --board ${BOARD}
JTAG_LINK ?= -c digilent_hs2
XDC ?= ${PROJECT}.xdc

46
example_demo/alinx_ax7325b/ax7325b_ddr3.v
View File

@ -85,7 +85,7 @@
//assign ddr3_cs_n[1] = 1'b1;
//===========================================================================
//Differentia system clock to single end clock
//Differential system clock to single end clock
//===========================================================================
wire sys_clk; // 200MHz
IBUFDS u_ibufg_sys_clk
@ -132,21 +132,35 @@
.clk_in1(sys_clk)
);
// // UART module from https://github.com/alexforencich/verilog-uart
// uart #(.DATA_WIDTH(8)) uart_m
// (
// .clk(i_controller_clk),
// .rst(!i_rst_n),
// .s_axis_tdata(o_wb_data),
// .s_axis_tvalid(o_wb_ack),
// .s_axis_tready(),
// .m_axis_tdata(rd_data),
// .m_axis_tvalid(m_axis_tvalid),
// .m_axis_tready(1),
// .rxd(rx),
// .txd(tx),
// .prescale(1085) //9600 Baud Rate: 83.3333MHz/(8*9600)
// );
// UART TX/RX module from https://github.com/ben-marshall/uart
uart_tx #(
.BIT_RATE(9600),
.CLK_HZ(83_333_333),
.PAYLOAD_BITS(8),
.STOP_BITS(1)
) uart_tx_inst (
.clk(i_controller_clk), // Top level system clock input.
.resetn(i_rst_n && clk_locked && o_debug1[4:0] == 23), // Asynchronous active low reset.
.uart_txd(tx), // UART transmit pin.
.uart_tx_busy(), // Module busy sending previous item.
.uart_tx_en(o_wb_ack), // Send the data on uart_tx_data
.uart_tx_data(o_wb_data) // The data to be sent
);
uart_rx #(
.BIT_RATE(9600),
.CLK_HZ(83_333_333),
.PAYLOAD_BITS(8),
.STOP_BITS(1)
) uart_rx_inst (
.clk(i_controller_clk), // Top level system clock input.
.resetn(i_rst_n && clk_locked && o_debug1[4:0] == 23), // Asynchronous active low reset.
.uart_rxd(rx), // UART Recieve pin.
.uart_rx_en(o_debug1[4:0] == 23), // Recieve enable
.uart_rx_break(), // Did we get a BREAK message?
.uart_rx_valid(m_axis_tvalid), // Valid data recieved/available.
.uart_rx_data(rd_data) // The recieved data.
);
// DDR3 Controller
ddr3_top #(