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UberDDR3
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resolve warning in implementation: not connected to load

This commit is contained in:
AngeloJacobo 2024-06-02 19:20:10 +08:00
parent 9c440d535f
commit 593f56ac4a
1 changed files with 2 additions and 2 deletions
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4
rtl/ddr3_phy.v
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@ -912,7 +912,7 @@ module ddr3_phy #(
); // End of IOBUFDS_inst instantiation ); // End of IOBUFDS_inst instantiation
end end
(* mark_debug = "true" *) wire[4:0] IDELAYE2_dqs_CNTVALUEOUT; // (* mark_debug = "true" *) wire[4:0] IDELAYE2_dqs_CNTVALUEOUT;
// IDELAYE2: Input Fixed or Variable Delay Element // IDELAYE2: Input Fixed or Variable Delay Element
// 7 Series // 7 Series
// Xilinx HDL Libraries Guide, version 13.4 // Xilinx HDL Libraries Guide, version 13.4
@ -926,7 +926,7 @@ module ddr3_phy #(
.SIGNAL_PATTERN("CLOCK") //DATA, CLOCK input signal .SIGNAL_PATTERN("CLOCK") //DATA, CLOCK input signal
) )
IDELAYE2_dqs ( IDELAYE2_dqs (
.CNTVALUEOUT(IDELAYE2_dqs_CNTVALUEOUT), // 5-bit output: Counter value output .CNTVALUEOUT(), // 5-bit output: Counter value output
.DATAOUT(idelay_dqs[gen_index]), // 1-bit output: Delayed data output .DATAOUT(idelay_dqs[gen_index]), // 1-bit output: Delayed data output
.C(i_controller_clk), // 1-bit input: Clock input .C(i_controller_clk), // 1-bit input: Clock input
.CE(1'b0), // 1-bit input: Active high enable increment/decrement input .CE(1'b0), // 1-bit input: Active high enable increment/decrement input