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UberDDR3
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update simulation files

This commit is contained in:
AngeloJacobo 2023-09-15 20:04:55 +08:00
parent 0ba4f433e5
commit 57e9f1b3f9
2 changed files with 35 additions and 59 deletions
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16
testbench/8192Mb_ddr3_parameters.vh
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@ -425,15 +425,15 @@
parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout
parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors
parameter DEBUG = 0; // Turn on Debug messages parameter DEBUG = 0; // Turn on Debug messages
parameter BUS_DELAY = 0; // delay in picoseconds parameter BUS_DELAY = 625; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_0 = 0; // delay in picoseconds parameter FLY_BY_DELAY_LANE_0 = 100; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_1 = 0; // delay in picoseconds parameter FLY_BY_DELAY_LANE_1 = 200; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_2 = 0; // delay in picoseconds parameter FLY_BY_DELAY_LANE_2 = 100; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_3 = 0; // delay in picoseconds parameter FLY_BY_DELAY_LANE_3 = 300; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_4 = 0; // delay in picoseconds parameter FLY_BY_DELAY_LANE_4 = 200; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_5 = 0; // delay in picoseconds parameter FLY_BY_DELAY_LANE_5 = 50; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_6 = 0; // delay in picoseconds parameter FLY_BY_DELAY_LANE_6 = 0; // delay in picoseconds
parameter FLY_BY_DELAY_LANE_7 = 0; // delay in picoseconds parameter FLY_BY_DELAY_LANE_7 = 250; // delay in picoseconds
parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads
parameter RANDOM_SEED = 31913; //seed value for random generator. parameter RANDOM_SEED = 31913; //seed value for random generator.

76
testbench/ddr3_dimm_micron_sim.v
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@ -21,10 +21,10 @@
`timescale 1ps / 1ps `timescale 1ps / 1ps
`define den8192Mb `define den8192Mb
`define sg125 `define sg125
`define x8 `define x16
//`define USE_CLOCK_WIZARD //`define USE_CLOCK_WIZARD
//`define TWO_LANES_x8 `define TWO_LANES_x8
`define EIGHT_LANES_x8 //`define EIGHT_LANES_x8
`define RAM_8Gb `define RAM_8Gb
module ddr3_dimm_micron_sim; module ddr3_dimm_micron_sim;
@ -44,7 +44,7 @@ module ddr3_dimm_micron_sim;
`ifdef TWO_LANES_x8 `ifdef TWO_LANES_x8
localparam LANES = 2, localparam LANES = 2,
ODELAY_SUPPORTED = 0; ODELAY_SUPPORTED = 1;
`endif `endif
`ifdef EIGHT_LANES_x8 `ifdef EIGHT_LANES_x8
@ -269,7 +269,7 @@ ddr3_top #(
@(posedge i_controller_clk) begin @(posedge i_controller_clk) begin
i_rst_n <= 0; i_rst_n <= 0;
// Wishbone 1 // Wishbone 1
i_wb_cyc <= 0; i_wb_cyc <= 1;
i_wb_stb <= 0; i_wb_stb <= 0;
i_wb_we <= 0; i_wb_we <= 0;
i_wb_sel <= -1; //write to all lanes i_wb_sel <= -1; //write to all lanes
@ -342,21 +342,24 @@ ddr3_top #(
end end
#1; //just to make sure the non-blocking are assignments are all over #1; //just to make sure the non-blocking are assignments are all over
end end
while(i_wb_stb) begin /*while(i_wb_stb) begin
@(posedge i_controller_clk) begin @(posedge i_controller_clk) begin
if (!o_wb_stall) i_wb_stb <= 1'b0; if (!o_wb_stall) i_wb_stb <= 1'b0;
end end
end end*/
$display("\n--------------------------------\nDONE TEST 1: FIRST ROW\nNumber of Operations: %0d\nTime Started: %0d ns\nTime Done: %0d ns\nAverage Rate: %0d ns/request\n--------------------------------\n\n", $display("\n--------------------------------\nDONE TEST 1: FIRST ROW\nNumber of Operations: %0d\nTime Started: %0d ns\nTime Done: %0d ns\nAverage Rate: %0d ns/request\n--------------------------------\n\n",
number_of_op,time_started/1000, $time/1000, ($time-time_started)/(number_of_op*1000)); number_of_op,time_started/1000, $time/1000, ($time-time_started)/(number_of_op*1000));
#100_000; // #100_000;
@(posedge i_controller_clk) begin /*@(posedge i_controller_clk) begin
// write to middle row // write to middle row
start_address <= ((2**COL_BITS)*(2**ROW_BITS)*(2**BA_BITS)/2)*($bits(ddr3_top.i_wb_data)/32)/8; //start at the middle row start_address <= ((2**COL_BITS)*(2**ROW_BITS)*(2**BA_BITS)/2)*($bits(ddr3_top.i_wb_data)/32)/8; //start at the middle row
end end*/
#1; //just to make sure the non-blocking are assignments are all over #1; //just to make sure the non-blocking are assignments are all over
start_address <= ((2**COL_BITS)*(2**ROW_BITS)*(2**BA_BITS)/2)*($bits(ddr3_top.i_wb_data)/32)/8; //start at the middle row
#1;
address <= start_address; address <= start_address;
number_of_op <= 0; number_of_op <= 0;
time_started <= $time; time_started <= $time;
@ -404,14 +407,14 @@ ddr3_top #(
end end
#1; //just to make sure the non-blocking are assignments are all over #1; //just to make sure the non-blocking are assignments are all over
end end
while(i_wb_stb) begin /*while(i_wb_stb) begin
@(posedge i_controller_clk) begin @(posedge i_controller_clk) begin
if (!o_wb_stall) i_wb_stb <= 1'b0; if (!o_wb_stall) i_wb_stb <= 1'b0;
end end
end end*/
$display("\n--------------------------------\nDONE TEST 1: MIDDLE ROW\nNumber of Operations: %0d\nTime Started: %0d ns\nTime Done: %0d ns\nAverage Rate: %0d ns/request\n--------------------------------\n\n", $display("\n--------------------------------\nDONE TEST 1: MIDDLE ROW\nNumber of Operations: %0d\nTime Started: %0d ns\nTime Done: %0d ns\nAverage Rate: %0d ns/request\n--------------------------------\n\n",
number_of_op,time_started/1000, $time/1000, ($time-time_started)/(number_of_op*1000)); number_of_op,time_started/1000, $time/1000, ($time-time_started)/(number_of_op*1000));
#100_000; //#100_000;
// write to last row (then go back to first row) // write to last row (then go back to first row)
@ -464,14 +467,14 @@ ddr3_top #(
end end
#1; //just to make sure the non-blocking are assignments are all over #1; //just to make sure the non-blocking are assignments are all over
end end
while(i_wb_stb) begin /*while(i_wb_stb) begin
@(posedge i_controller_clk) begin @(posedge i_controller_clk) begin
if (!o_wb_stall) i_wb_stb <= 1'b0; if (!o_wb_stall) i_wb_stb <= 1'b0;
end end
end end*/
$display("\n--------------------------------\nDONE TEST 1: LAST ROW\nNumber of Operations: %0d\nTime Started: %0d ns\nTime Done: %0d ns\nAverage Rate: %0d ns/request\n--------------------------------\n\n", $display("\n--------------------------------\nDONE TEST 1: LAST ROW\nNumber of Operations: %0d\nTime Started: %0d ns\nTime Done: %0d ns\nAverage Rate: %0d ns/request\n--------------------------------\n\n",
number_of_op,time_started/1000, $time/1000, ($time-time_started)/(number_of_op*1000)); number_of_op,time_started/1000, $time/1000, ($time-time_started)/(number_of_op*1000));
#100_000; //#100_000;
@ -585,47 +588,19 @@ ddr3_top #(
#1; //just to make sure the non-blocking are assignments are all over #1; //just to make sure the non-blocking are assignments are all over
end end
while(i_wb_stb) begin while(i_wb2_stb) begin
@(posedge i_controller_clk) begin @(posedge i_controller_clk) begin
if (!o_wb_stall) i_wb_stb <= 1'b0; if (!o_wb2_stall) i_wb2_stb <= 1'b0;
end end
end end
#100_000;
/*
// write
//wait until ready to access
wait(!o_wb_stall);
@(negedge i_controller_clk);
i_wb_cyc = 1;
i_wb_stb = 1;
i_wb_we = 1;
i_wb_addr = 0;
i_wb_data = "BURST_8 BURST_7 BURST_6 BURST_5 BURST_4 BURST_3 BURST_2 BURST_1 ";
//i_wb_data = 512'h77777777_77777777__66666666_66666666__55555555_55555555__44444444_44444444__33333333_33333333__22222222_22222222__11111111_11111111__00000000_00000000;
@(negedge i_controller_clk);
i_wb_addr = 1;
i_wb_data = "SAMPLE8 SAMPLE7 SAMPLE6 SAMPLE5 SAMPLE4 SAMPLE3 SAMPLE2 SAMPLE1 SAMPLE0";
//i_wb_data = 512'h77665544_33221100__77665544_33221100__77665544_33221100__77665544_33221100__77665544_33221100__77665544_33221100__77665544_33221100__77665544_33221100;
@(negedge i_controller_clk);
i_wb_stb = 0;
i_wb_data = 0;
//read
wait(!o_wb_stall);
@(negedge i_controller_clk);
i_wb_stb = 1;
i_wb_we = 0;
i_wb_addr = 0;
@(negedge i_controller_clk);
i_wb_addr = 1;
@(negedge i_controller_clk);
i_wb_stb = 0;
*/
#1000_000; #1000_000;
$display("\n\n------- SUMMARY -------\nNumber of Writes = %0d\nNumber of Reads = %0d\nNumber of Success = %0d\nNumber of Fails = %0d\nNumber of Injected Errors = %0d\n", $display("\n\n------- SUMMARY -------\nNumber of Writes = %0d\nNumber of Reads = %0d\nNumber of Success = %0d\nNumber of Fails = %0d\nNumber of Injected Errors = %0d\n",
number_of_writes, number_of_reads,number_of_successful, number_of_failed, number_of_injected_errors); number_of_writes, number_of_reads,number_of_successful, number_of_failed, number_of_injected_errors);
$display("\n\nTEST CALIBRATION\n[-]: write_test_address_counter = %0d", ddr3_top.ddr3_controller_inst.write_test_address_counter);
$display("[-]: read_test_address_counter = %0d", ddr3_top.ddr3_controller_inst.read_test_address_counter);
$display("[-]: correct_read_data = %0d", ddr3_top.ddr3_controller_inst.correct_read_data);
$display("[-]: wrong_read_data = %0d", ddr3_top.ddr3_controller_inst.wrong_read_data);
$stop; $stop;
end end
@ -799,6 +774,7 @@ ddr3_top #(
end end
end end
end end
reg[8*3-1:0] command_used; //store command in ASCII reg[8*3-1:0] command_used; //store command in ASCII