luke
/
UberDDR3
mirror of https://github.com/AngeloJacobo/UberDDR3.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

verilator now passing lint even with older verilator version

This commit is contained in:
AngeloJacobo 2025-05-11 20:02:13 +08:00
parent 5b0c48ca0a
commit 50c0a6488d
1 changed files with 84 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

123
rtl/ddr3_controller.v
View File

@ -401,7 +401,7 @@ module ddr3_controller #(
localparam[18:0] MR3_MPR_DIS = {MR3_SEL, 13'b0_0000_0000_0000, !MPR_EN, MPR_LOC}; localparam[18:0] MR3_MPR_DIS = {MR3_SEL, 13'b0_0000_0000_0000, !MPR_EN, MPR_LOC};
// MR1 (JEDEC DDR3 doc pg. 27) // MR1 (JEDEC DDR3 doc pg. 27)
localparam DLL_EN = DLL_OFF? 1'b0 : 1'b1; //DLL Enable/Disable: Enabled(0) localparam DLL_EN = DLL_OFF? 1'b1 : 1'b0; //DLL Enable/Disable: Enabled(0)
// localparam[1:0] DIC = 2'b01; //Output Driver Impedance Control (RZQ/7) (elevate this to parameter) // localparam[1:0] DIC = 2'b01; //Output Driver Impedance Control (RZQ/7) (elevate this to parameter)
// localparam[2:0] RTT_NOM = 3'b001; //RTT Nominal: RZQ/4 (elevate this to parameter) // localparam[2:0] RTT_NOM = 3'b001; //RTT Nominal: RZQ/4 (elevate this to parameter)
localparam[0:0] WL_EN = 1'b1; //Write Leveling Enable: Disabled localparam[0:0] WL_EN = 1'b1; //Write Leveling Enable: Disabled
@ -491,13 +491,31 @@ module ddr3_controller #(
wire[wb_addr_bits-1:0] wb_addr_plus_anticipate, calib_addr_plus_anticipate; wire[wb_addr_bits-1:0] wb_addr_plus_anticipate, calib_addr_plus_anticipate;
//pipeline stage 2 regs //pipeline stage 2 regs
/* verilator lint_off UNUSEDSIGNAL */
// if STAGE2_DATA_DEPTH == 2, then stage2_dm_2 and stage2_data_2 will be unused
reg[wb_sel_bits - 1:0] stage2_dm_0, stage2_dm_1, stage2_dm_2, stage2_dm_last;
reg[wb_data_bits - 1:0] stage2_data_0, stage2_data_1, stage2_data_2, stage2_data_last;
generate
if(STAGE2_DATA_DEPTH == 3) begin : stage2_data_depth_3_all
always @(posedge i_controller_clk) begin
if(sync_rst_controller) begin
stage2_data_2 <= 0;
stage2_dm_2 <= 0;
end
else begin
stage2_data_2 <= stage2_data_1;
stage2_dm_2 <= stage2_dm_1;
end
end
end
endgenerate
/* verilator lint_on UNUSEDSIGNAL */
reg stage2_pending = 0; reg stage2_pending = 0;
reg[AUX_WIDTH-1:0] stage2_aux = 0; reg[AUX_WIDTH-1:0] stage2_aux = 0;
reg stage2_we = 0; reg stage2_we = 0;
reg[wb_sel_bits - 1:0] stage2_dm_unaligned = 0, stage2_dm_unaligned_temp = 0; reg[wb_sel_bits - 1:0] stage2_dm_unaligned = 0, stage2_dm_unaligned_temp = 0;
reg[wb_sel_bits - 1:0] stage2_dm[STAGE2_DATA_DEPTH-1:0];
reg[wb_data_bits - 1:0] stage2_data_unaligned = 0, stage2_data_unaligned_temp = 0; reg[wb_data_bits - 1:0] stage2_data_unaligned = 0, stage2_data_unaligned_temp = 0;
reg[wb_data_bits - 1:0] stage2_data[STAGE2_DATA_DEPTH-1:0];
reg [DQ_BITS*8 - 1:0] unaligned_data[LANES-1:0]; reg [DQ_BITS*8 - 1:0] unaligned_data[LANES-1:0];
reg [8 - 1:0] unaligned_dm[LANES-1:0]; reg [8 - 1:0] unaligned_dm[LANES-1:0];
reg[COL_BITS-1:0] stage2_col = 0; reg[COL_BITS-1:0] stage2_col = 0;
@ -649,9 +667,14 @@ module ddr3_controller #(
reg[1:0] shift_read_pipe = 0; reg[1:0] shift_read_pipe = 0;
reg[wb_data_bits-1:0] wrong_data = 0, expected_data=0; reg[wb_data_bits-1:0] wrong_data = 0, expected_data=0;
wire[wb_data_bits-1:0] correct_data; wire[wb_data_bits-1:0] correct_data;
// initial block for all regs // initial block for all regs
initial begin initial begin
o_wb_stall = 1; o_wb_stall = 1;
stage2_data_0 = 0;
stage2_data_1 = 0;
stage2_dm_0 = 0;
stage2_dm_1 = 0;
for(index = 0; index < MAX_ADDED_READ_ACK_DELAY; index = index + 1) begin for(index = 0; index < MAX_ADDED_READ_ACK_DELAY; index = index + 1) begin
o_wb_ack_read_q[index] = 0; o_wb_ack_read_q[index] = 0;
end end
@ -663,11 +686,6 @@ module ddr3_controller #(
bank_active_row_d[index] = 0; bank_active_row_d[index] = 0;
end end
for(index = 0; index < STAGE2_DATA_DEPTH; index = index+1) begin
stage2_data[index] = 0;
stage2_dm[index] = 0;
end
for(index=0; index <(1<<(BA_BITS+DUAL_RANK_DIMM)); index=index+1) begin for(index=0; index <(1<<(BA_BITS+DUAL_RANK_DIMM)); index=index+1) begin
delay_before_precharge_counter_q[index] = 0; delay_before_precharge_counter_q[index] = 0;
delay_before_activate_counter_q[index] = 0; delay_before_activate_counter_q[index] = 0;
@ -959,11 +977,11 @@ module ddr3_controller #(
bank_status_q[index] <= 0; bank_status_q[index] <= 0;
bank_active_row_q[index] <= 0; bank_active_row_q[index] <= 0;
end end
//reset data
for(index = 0; index < STAGE2_DATA_DEPTH; index = index+1) begin stage2_data_0 <= 0;
stage2_data[index] <= 0; stage2_data_1 <= 0;
stage2_dm[index] <= 0; stage2_dm_0 <= 0;
end stage2_dm_1 <= 0;
end end
// can only start accepting requests when reset is done // can only start accepting requests when reset is done
@ -1231,10 +1249,8 @@ module ddr3_controller #(
end end
// stage2 can have multiple pipelined stages inside it which acts as delay before issuing the write data (after issuing write command) // stage2 can have multiple pipelined stages inside it which acts as delay before issuing the write data (after issuing write command)
for(index = 0; index < STAGE2_DATA_DEPTH-1; index = index+1) begin stage2_data_1 <= stage2_data_0;
stage2_data[index+1] <= stage2_data[index]; // 0->1, 1->2 stage2_dm_1 <= stage2_dm_0;
stage2_dm[index+1] <= stage2_dm[index];
end
for(index = 0; index < LANES; index = index + 1) begin for(index = 0; index < LANES; index = index + 1) begin
/* verilator lint_off WIDTH */ /* verilator lint_off WIDTH */
@ -1243,10 +1259,10 @@ module ddr3_controller #(
// checks if the DQ for this lane is late (index being zero while write_dq_late high means we will try 2nd assumption), if yes then we forward stage2_data_unaligned directly to stage2_data[1] // checks if the DQ for this lane is late (index being zero while write_dq_late high means we will try 2nd assumption), if yes then we forward stage2_data_unaligned directly to stage2_data[1]
if((lane_write_dq_late[index] && (data_start_index[index] != 0)) && (STAGE2_DATA_DEPTH > 1)) begin if((lane_write_dq_late[index] && (data_start_index[index] != 0)) && (STAGE2_DATA_DEPTH > 1)) begin
{unaligned_data[index], { {unaligned_data[index], {
stage2_data[1][((DQ_BITS*LANES)*7 + 8*index) +: 8], stage2_data[1][((DQ_BITS*LANES)*6 + 8*index) +: 8], stage2_data_1[((DQ_BITS*LANES)*7 + 8*index) +: 8], stage2_data_1[((DQ_BITS*LANES)*6 + 8*index) +: 8],
stage2_data[1][((DQ_BITS*LANES)*5 + 8*index) +: 8], stage2_data[1][((DQ_BITS*LANES)*4 + 8*index) +: 8], stage2_data_1[((DQ_BITS*LANES)*5 + 8*index) +: 8], stage2_data_1[((DQ_BITS*LANES)*4 + 8*index) +: 8],
stage2_data[1][((DQ_BITS*LANES)*3 + 8*index) +: 8], stage2_data[1][((DQ_BITS*LANES)*2 + 8*index) +: 8], stage2_data_1[((DQ_BITS*LANES)*3 + 8*index) +: 8], stage2_data_1[((DQ_BITS*LANES)*2 + 8*index) +: 8],
stage2_data[1][((DQ_BITS*LANES)*1 + 8*index) +: 8], stage2_data[1][((DQ_BITS*LANES)*0 + 8*index) +: 8] }} stage2_data_1[((DQ_BITS*LANES)*1 + 8*index) +: 8], stage2_data_1[((DQ_BITS*LANES)*0 + 8*index) +: 8] }}
<= ( { stage2_data_unaligned[((DQ_BITS*LANES)*7 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*6 + 8*index) +: 8], <= ( { stage2_data_unaligned[((DQ_BITS*LANES)*7 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*6 + 8*index) +: 8],
stage2_data_unaligned[((DQ_BITS*LANES)*5 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*4 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*5 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*4 + 8*index) +: 8],
stage2_data_unaligned[((DQ_BITS*LANES)*3 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*2 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*3 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*2 + 8*index) +: 8],
@ -1255,10 +1271,10 @@ module ddr3_controller #(
// data_start_index is set to 1 so this if statement will pass, but shift left is zero (lsb of data_start_index is removed) which means // data_start_index is set to 1 so this if statement will pass, but shift left is zero (lsb of data_start_index is removed) which means
// DQ is 1 whole controller cycle early (happens in Kintex-7 with OpenXC7) // DQ is 1 whole controller cycle early (happens in Kintex-7 with OpenXC7)
{unaligned_dm[index], { {unaligned_dm[index], {
stage2_dm[1][LANES*7 + index], stage2_dm[1][LANES*6 + index], stage2_dm_1[LANES*7 + index], stage2_dm_1[LANES*6 + index],
stage2_dm[1][LANES*5 + index], stage2_dm[1][LANES*4 + index], stage2_dm_1[LANES*5 + index], stage2_dm_1[LANES*4 + index],
stage2_dm[1][LANES*3 + index], stage2_dm[1][LANES*2 + index], stage2_dm_1[LANES*3 + index], stage2_dm_1[LANES*2 + index],
stage2_dm[1][LANES*1 + index], stage2_dm[1][LANES*0 + index] }} stage2_dm_1[LANES*1 + index], stage2_dm_1[LANES*0 + index] }}
<= ( { stage2_dm_unaligned[LANES*7 + index], stage2_dm_unaligned[LANES*6 + index], <= ( { stage2_dm_unaligned[LANES*7 + index], stage2_dm_unaligned[LANES*6 + index],
stage2_dm_unaligned[LANES*5 + index], stage2_dm_unaligned[LANES*4 + index], stage2_dm_unaligned[LANES*5 + index], stage2_dm_unaligned[LANES*4 + index],
stage2_dm_unaligned[LANES*3 + index], stage2_dm_unaligned[LANES*2 + index], stage2_dm_unaligned[LANES*3 + index], stage2_dm_unaligned[LANES*2 + index],
@ -1272,10 +1288,10 @@ module ddr3_controller #(
// stage2_data_unaligned is the DQ_BITS*LANES*8 raw data from stage 1 so not yet aligned // stage2_data_unaligned is the DQ_BITS*LANES*8 raw data from stage 1 so not yet aligned
// unaligned_data is 64 bits // unaligned_data is 64 bits
{unaligned_data[index], { {unaligned_data[index], {
stage2_data[0][((DQ_BITS*LANES)*7 + 8*index) +: 8], stage2_data[0][((DQ_BITS*LANES)*6 + 8*index) +: 8], stage2_data_0[((DQ_BITS*LANES)*7 + 8*index) +: 8], stage2_data_0[((DQ_BITS*LANES)*6 + 8*index) +: 8],
stage2_data[0][((DQ_BITS*LANES)*5 + 8*index) +: 8], stage2_data[0][((DQ_BITS*LANES)*4 + 8*index) +: 8], stage2_data_0[((DQ_BITS*LANES)*5 + 8*index) +: 8], stage2_data_0[((DQ_BITS*LANES)*4 + 8*index) +: 8],
stage2_data[0][((DQ_BITS*LANES)*3 + 8*index) +: 8], stage2_data[0][((DQ_BITS*LANES)*2 + 8*index) +: 8], stage2_data_0[((DQ_BITS*LANES)*3 + 8*index) +: 8], stage2_data_0[((DQ_BITS*LANES)*2 + 8*index) +: 8],
stage2_data[0][((DQ_BITS*LANES)*1 + 8*index) +: 8], stage2_data[0][((DQ_BITS*LANES)*0 + 8*index) +: 8] }} stage2_data_0[((DQ_BITS*LANES)*1 + 8*index) +: 8], stage2_data_0[((DQ_BITS*LANES)*0 + 8*index) +: 8] }}
<= ( { stage2_data_unaligned[((DQ_BITS*LANES)*7 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*6 + 8*index) +: 8], <= ( { stage2_data_unaligned[((DQ_BITS*LANES)*7 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*6 + 8*index) +: 8],
stage2_data_unaligned[((DQ_BITS*LANES)*5 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*4 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*5 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*4 + 8*index) +: 8],
stage2_data_unaligned[((DQ_BITS*LANES)*3 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*2 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*3 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*2 + 8*index) +: 8],
@ -1313,10 +1329,10 @@ module ddr3_controller #(
// The same alignment logic is done with data mask // The same alignment logic is done with data mask
{unaligned_dm[index], { {unaligned_dm[index], {
stage2_dm[0][LANES*7 + index], stage2_dm[0][LANES*6 + index], stage2_dm_0[LANES*7 + index], stage2_dm_0[LANES*6 + index],
stage2_dm[0][LANES*5 + index], stage2_dm[0][LANES*4 + index], stage2_dm_0[LANES*5 + index], stage2_dm_0[LANES*4 + index],
stage2_dm[0][LANES*3 + index], stage2_dm[0][LANES*2 + index], stage2_dm_0[LANES*3 + index], stage2_dm_0[LANES*2 + index],
stage2_dm[0][LANES*1 + index], stage2_dm[0][LANES*0 + index] }} stage2_dm_0[LANES*1 + index], stage2_dm_0[LANES*0 + index] }}
<= ( { stage2_dm_unaligned[LANES*7 + index], stage2_dm_unaligned[LANES*6 + index], <= ( { stage2_dm_unaligned[LANES*7 + index], stage2_dm_unaligned[LANES*6 + index],
stage2_dm_unaligned[LANES*5 + index], stage2_dm_unaligned[LANES*4 + index], stage2_dm_unaligned[LANES*5 + index], stage2_dm_unaligned[LANES*4 + index],
stage2_dm_unaligned[LANES*3 + index], stage2_dm_unaligned[LANES*2 + index], stage2_dm_unaligned[LANES*3 + index], stage2_dm_unaligned[LANES*2 + index],
@ -1475,18 +1491,37 @@ module ddr3_controller #(
end end
endgenerate endgenerate
generate generate
// determine which stage2_data will be the last and will sent to o_phy_data
if(STAGE2_DATA_DEPTH == 1) begin : stage2_data_depth_1
always @* begin
stage2_data_last = stage2_data_0;
stage2_dm_last = stage2_dm_0;
end
end
else if(STAGE2_DATA_DEPTH == 2) begin : stage2_data_depth_2
always @* begin
stage2_data_last = stage2_data_1;
stage2_dm_last = stage2_dm_1;
end
end
else if(STAGE2_DATA_DEPTH == 3) begin : stage2_data_depth_3
always @* begin
stage2_data_last = stage2_data_2;
stage2_dm_last = stage2_dm_2;
end
end
// If DLL off, add 1 more cycle of delay since PHY is faster for DLL OFF // If DLL off, add 1 more cycle of delay since PHY is faster for DLL OFF
if(DLL_OFF) begin : dll_off_out_phy if(DLL_OFF) begin : dll_off_out_phy
always @(posedge i_controller_clk) begin always @(posedge i_controller_clk) begin
o_phy_data <= stage2_data[STAGE2_DATA_DEPTH-1]; // the data sent to PHY is the last stage of of stage 2 (since stage 2 can have multiple pipelined stages inside it_ o_phy_data <= stage2_data_last; // the data sent to PHY is the last stage of of stage 2 (since stage 2 can have multiple pipelined stages inside it_
o_phy_dm <= stage2_dm[STAGE2_DATA_DEPTH-1]; o_phy_dm <= stage2_dm_last;
o_phy_cmd <= {cmd_d[3], cmd_d[2], cmd_d[1], cmd_d[0]}; o_phy_cmd <= {cmd_d[3], cmd_d[2], cmd_d[1], cmd_d[0]};
end end
end end
else begin : dll_on_out_phy else begin : dll_on_out_phy
always @* begin always @* begin
o_phy_data = stage2_data[STAGE2_DATA_DEPTH-1]; // the data sent to PHY is the last stage of of stage 2 (since stage 2 can have multiple pipelined stages inside it_ o_phy_data = stage2_data_last; // the data sent to PHY is the last stage of of stage 2 (since stage 2 can have multiple pipelined stages inside it_
o_phy_dm = stage2_dm[STAGE2_DATA_DEPTH-1]; o_phy_dm = stage2_dm_last;
o_phy_cmd = {cmd_d[3], cmd_d[2], cmd_d[1], cmd_d[0]}; o_phy_cmd = {cmd_d[3], cmd_d[2], cmd_d[1], cmd_d[0]};
end end
end end
@ -2870,7 +2905,12 @@ module ddr3_controller #(
state_calibrate <= CHECK_STARTING_DATA; state_calibrate <= CHECK_STARTING_DATA;
`ifdef UART_DEBUG_ALIGN `ifdef UART_DEBUG_ALIGN
uart_start_send <= 1'b1; uart_start_send <= 1'b1;
uart_text <= {"state=ANALYZE_DATA, lane=",hex_to_ascii(lane), ", First Assumption wrong, Start second assumption: Read too early",8'h0a,8'h0a}; uart_text <= {"state=ANALYZE_DATA, lane=",hex_to_ascii(lane), ", First Assumption wrong, Start second assumption: Read too early",8'h0a,8'h0a,
8'h0a,8'h0a,
{read_data_store[((DQ_BITS*LANES)*7 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*6 + 8*lane) +: 8],
read_data_store[((DQ_BITS*LANES)*5 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*4 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*3 + 8*lane) +: 8],
read_data_store[((DQ_BITS*LANES)*2 + 8*lane) +: 8],read_data_store[((DQ_BITS*LANES)*1 + 8*lane) +: 8],read_data_store[((DQ_BITS*LANES)*0 + 8*lane) +: 8] },
8'h0a,8'h0a,8'h0a,8'h0a};
state_calibrate <= WAIT_UART; state_calibrate <= WAIT_UART;
state_calibrate_next <= CHECK_STARTING_DATA; state_calibrate_next <= CHECK_STARTING_DATA;
`endif `endif
@ -2895,7 +2935,12 @@ module ddr3_controller #(
else begin else begin
uart_start_send <= 1'b1; uart_start_send <= 1'b1;
uart_text <= {"state=ANALYZE_DATA, lane=",hex_to_ascii(lane), ", data_start_index[lane]=0x", uart_text <= {"state=ANALYZE_DATA, lane=",hex_to_ascii(lane), ", data_start_index[lane]=0x",
hex_to_ascii(data_start_index[lane][6:4]),hex_to_ascii(data_start_index[lane][3:0]),8'h0a}; hex_to_ascii(data_start_index[lane][6:4]),hex_to_ascii(data_start_index[lane][3:0]),8'h0a,8'h0a,8'h0a,8'h0a,
{read_data_store[((DQ_BITS*LANES)*7 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*6 + 8*lane) +: 8],
read_data_store[((DQ_BITS*LANES)*5 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*4 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*3 + 8*lane) +: 8],
read_data_store[((DQ_BITS*LANES)*2 + 8*lane) +: 8],read_data_store[((DQ_BITS*LANES)*1 + 8*lane) +: 8],read_data_store[((DQ_BITS*LANES)*0 + 8*lane) +: 8] },
8'h0a,8'h0a,8'h0a,8'h0a
};
state_calibrate <= WAIT_UART; state_calibrate <= WAIT_UART;
state_calibrate_next <= ANALYZE_DATA; state_calibrate_next <= ANALYZE_DATA;
end end