separated multiconfigs to prevent system crash when running
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AngeloJacobo
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aad75f936c
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[tasks]
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prf2lanes_83MHz prf opt_2lanes opt_83MHz opt_with_ODELAY
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prf4lanes_83MHz prf opt_4lanes opt_83MHz opt_with_ODELAY
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prf8lanes_83MHz prf opt_8lanes opt_83MHz opt_with_ODELAY opt_WB_ERR
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prf2lanes_100MHz prf opt_2lanes opt_100MHz opt_with_ODELAY opt_WB_ERR
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prf4lanes_100MHz prf opt_4lanes opt_100MHz opt_with_ODELAY
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prf8lanes_100MHz prf opt_8lanes opt_100MHz opt_with_ODELAY
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prf_no_ODELAY prf opt_8lanes opt_100MHz
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[options]
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prf: mode prove
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prf: depth 7
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[engines]
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prf: smtbmc
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[script]
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read -formal ddr3_controller.v
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read -formal fwb_slave.v
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--pycode-begin--
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# Number of Lanes
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if "opt_2lanes" in tags:
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cmd = "chparam -set LANES 2 ddr3_controller\n"
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elif "opt_4lanes" in tags:
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cmd = "chparam -set LANES 4 ddr3_controller\n"
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elif "opt_8lanes" in tags:
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cmd = "chparam -set LANES 8 ddr3_controller\n"
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else:
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cmd = "chparam -set LANES 8 ddr3_controller\n"
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# Clock period
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if "opt_83MHz" in tags:
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cmd += "chparam -set CONTROLLER_CLK_PERIOD 12000 ddr3_controller\n"
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cmd += "chparam -set DDR3_CLK_PERIOD 3000 ddr3_controller\n"
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elif "opt_100MHz" in tags:
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cmd += "chparam -set CONTROLLER_CLK_PERIOD 10000 ddr3_controller\n"
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cmd += "chparam -set DDR3_CLK_PERIOD 2500 ddr3_controller\n"
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else:
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cmd += "chparam -set CONTROLLER_CLK_PERIOD 10000 ddr3_controller\n"
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cmd += "chparam -set DDR3_CLK_PERIOD 2500 ddr3_controller\n"
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# ODELAY support
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if "opt_with_ODELAY" in tags:
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cmd += "chparam -set ODELAY_SUPPORTED 1 ddr3_controller\n"
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else:
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cmd += "chparam -set ODELAY_SUPPORTED 0 ddr3_controller\n"
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# Wishbone Error
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if "opt_WB_ERR" in tags:
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cmd += "chparam -set WB_ERROR 1 ddr3_controller\n"
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else:
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cmd += "chparam -set WB_ERROR 0 ddr3_controller\n"
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output(cmd)
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--pycode-end--
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prep -top ddr3_controller
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[files]
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./rtl/ddr3_controller.v
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./formal/fwb_slave.v
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@ -0,0 +1,83 @@
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[tasks]
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prf2lanes_83MHz_ECC_1 prf opt_2lanes opt_83MHz opt_with_ODELAY opt_ECC_1
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prf8lanes_100MHz_ECC_1 prf opt_8lanes opt_100MHz opt_ECC_1
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prf8lanes_100MHz_ECC_1_err prf opt_8lanes opt_100MHz opt_with_ODELAY opt_ECC_1 opt_WB_ERR
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prf2lanes_83MHz_ECC_2_err prf opt_2lanes opt_83MHz opt_with_ODELAY opt_ECC_2 opt_WB_ERR
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prf2lanes_83MHz_ECC_3 prf_ECC3 opt_2lanes opt_100MHz opt_with_ODELAY opt_ECC_3
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prf8lanes_100MHz_ECC_3 prf_ECC3 opt_8lanes opt_83MHz opt_ECC_3
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prf8lanes_100MHz_ECC_3_err prf_ECC3 opt_8lanes opt_100MHz opt_ECC_3 opt_WB_ERR
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[options]
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prf: mode prove
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prf: depth 7
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prf_ECC3: mode prove
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prf_ECC3: depth 5
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[engines]
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prf: smtbmc
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prf_ECC3: smtbmc
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[script]
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read -formal ddr3_controller.v
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read -formal fwb_slave.v
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read -formal ecc_dec.sv
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read -formal ecc_enc.sv
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--pycode-begin--
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# Number of Lanes
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if "opt_2lanes" in tags:
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cmd = "chparam -set LANES 2 ddr3_controller\n"
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elif "opt_4lanes" in tags:
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cmd = "chparam -set LANES 4 ddr3_controller\n"
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elif "opt_8lanes" in tags:
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cmd = "chparam -set LANES 8 ddr3_controller\n"
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else:
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cmd = "chparam -set LANES 8 ddr3_controller\n"
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# Clock period
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if "opt_83MHz" in tags:
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cmd += "chparam -set CONTROLLER_CLK_PERIOD 12000 ddr3_controller\n"
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cmd += "chparam -set DDR3_CLK_PERIOD 3000 ddr3_controller\n"
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elif "opt_100MHz" in tags:
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cmd += "chparam -set CONTROLLER_CLK_PERIOD 10000 ddr3_controller\n"
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cmd += "chparam -set DDR3_CLK_PERIOD 2500 ddr3_controller\n"
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else:
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cmd += "chparam -set CONTROLLER_CLK_PERIOD 10000 ddr3_controller\n"
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cmd += "chparam -set DDR3_CLK_PERIOD 2500 ddr3_controller\n"
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# ODELAY support
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if "opt_with_ODELAY" in tags:
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cmd += "chparam -set ODELAY_SUPPORTED 1 ddr3_controller\n"
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else:
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cmd += "chparam -set ODELAY_SUPPORTED 0 ddr3_controller\n"
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# ECC
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if "opt_ECC_3" in tags:
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cmd += "chparam -set ECC_ENABLE 3 ddr3_controller\n"
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elif "opt_ECC_2" in tags:
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cmd += "chparam -set ECC_ENABLE 2 ddr3_controller\n"
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elif "opt_ECC_1" in tags:
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cmd += "chparam -set ECC_ENABLE 1 ddr3_controller\n"
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else:
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cmd += "chparam -set ECC_ENABLE 0 ddr3_controller\n"
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# Wishbone Error
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if "opt_WB_ERR" in tags:
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cmd += "chparam -set WB_ERROR 1 ddr3_controller\n"
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else:
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cmd += "chparam -set WB_ERROR 0 ddr3_controller\n"
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output(cmd)
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--pycode-end--
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prep -top ddr3_controller
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[files]
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./rtl/ddr3_controller.v
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./formal/fwb_slave.v
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./rtl/ecc/ecc_dec.sv
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./rtl/ecc/ecc_enc.sv
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