moved ARTY-S7 project files

2023-11-26 14:04:15 +08:00 · 2023-11-26 14:04:15 +08:00 · 2a926cfc91
parent 8d20a6f4d0
commit 2a926cfc91
4 changed files with 1 additions and 1 deletions
--- a/.gitmodules
+++ b/.gitmodules
@ -1,3 +1,3 @@
 [submodule "testbench/ARTY_S7/verilog-uart"]
-	path = testbench/ARTY_S7/verilog-uart
+	path = ARTY_S7/verilog-uart
 	url = https://github.com/alexforencich/verilog-uart.git
--- a/testbench/ARTY_S7/Arty-S7-50-Master.xdc
+++ b/testbench/ARTY_S7/Arty-S7-50-Master.xdc
--- a/testbench/ARTY_S7/arty_ddr3.v
+++ b/testbench/ARTY_S7/arty_ddr3.v
--- a/testbench/ARTY_S7/verilog-uart
+++ b/testbench/ARTY_S7/verilog-uart