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UberDDR3
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fix flagged errors from openxc7

This commit is contained in:
AngeloJacobo 2025-03-02 14:34:59 +08:00
parent 94b4e0866b
commit 0c484d54f6
2 changed files with 3 additions and 3 deletions
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4
example_demo/arty_s7/arty_ddr3.v
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@ -146,14 +146,14 @@
.uart_rx_data(rd_data) // The recieved data. .uart_rx_data(rd_data) // The recieved data.
); );
`define XADC // `define XADC
`ifdef XADC `ifdef XADC
xadc_wiz_0 xadc_inst ( xadc_wiz_0 xadc_inst (
.dclk_in(i_controller_clk), // Clock input for the dynamic reconfiguration port .dclk_in(i_controller_clk), // Clock input for the dynamic reconfiguration port
.user_temp_alarm_out(user_temp_alarm_out) // Temperature-sensor alarm output .user_temp_alarm_out(user_temp_alarm_out) // Temperature-sensor alarm output
); );
`else `else
user_temp_alarm_out = 1'b0; assign user_temp_alarm_out = 1'b0;
`endif `endif
// UART module from https://github.com/alexforencich/verilog-uart (DOES NOT WORK ON OPENXC7, UberDDR3 cannot finish calibration when this UART is used) // UART module from https://github.com/alexforencich/verilog-uart (DOES NOT WORK ON OPENXC7, UberDDR3 cannot finish calibration when this UART is used)

2
example_demo/arty_s7/arty_ddr3.xdc
View File

@ -260,6 +260,6 @@ set_property CONFIG_MODE SPIx4 [current_design]
## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being ## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being
## used the internal reference is set to half that value (i.e. 0.675v). Note that ## used the internal reference is set to half that value (i.e. 0.675v). Note that
## this property must be set even if SW3 is not used in the design. ## this property must be set even if SW3 is not used in the design.
set_property INTERNAL_VREF 0.675 [get_iobanks 34] # set_property INTERNAL_VREF 0.675 [get_iobanks 34]