19 lines
273 B
Coq
19 lines
273 B
Coq
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`timescale 1 ns/1 ps
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module IDELAYCTRL_model (
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output reg RDY,
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input REFCLK,
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input RST
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);
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initial RDY = 0;
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always @(posedge RST) begin
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RDY <= 0;
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end
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always @(negedge RST) begin
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# 10; // 10ns delay before RDY assertion
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RDY <= 1;
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end
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endmodule
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