40 lines
1002 B
Coq
40 lines
1002 B
Coq
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`timescale 1ps/1ps
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module clk_wiz
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(
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input clk_in1,
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output clk_out1,
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input reset,
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output locked
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);
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wire clk_out1_clk_wiz_0;
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wire clkfbout;
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PLLE2_ADV
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#(.BANDWIDTH ("OPTIMIZED"),
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.COMPENSATION ("INTERNAL"),
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.STARTUP_WAIT ("FALSE"),
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.DIVCLK_DIVIDE (1),
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.CLKFBOUT_MULT (5), // 200 MHz * 5 = 1000 MHz
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.CLKFBOUT_PHASE (0.000),
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.CLKOUT0_DIVIDE (10), // 1000 MHz / 10 = 100 MHz
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.CLKOUT0_PHASE (0.000),
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.CLKOUT0_DUTY_CYCLE (0.500),
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.CLKIN1_PERIOD (5.000) // 200 MHz input
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)
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plle2_adv_inst
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(
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.CLKFBOUT (clkfbout),
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.CLKOUT0 (clk_out1_clk_wiz_0),
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.CLKFBIN (clkfbout),
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.CLKIN1 (clk_in1),
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.LOCKED (locked),
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.RST (reset)
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);
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BUFG clkout1_buf
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(.O (clk_out1),
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.I (clk_out1_clk_wiz_0));
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endmodule
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