113 lines
3.5 KiB
Tcl
113 lines
3.5 KiB
Tcl
# Test Levelize.cc and Sim.cc code paths
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog search_test1.v
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link_design search_test1
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_output_delay -clock clk 2.0 [get_ports out1]
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# Force timing first
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report_checks > /dev/null
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puts "--- levelize ---"
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sta::levelize
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puts "PASS: levelize"
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puts "--- report_loops ---"
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catch { sta::report_loops }
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puts "PASS: report_loops"
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puts "--- Sim logic values ---"
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set sv_and [sta::pin_sim_logic_value [get_pins and1/ZN]]
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set sv_buf [sta::pin_sim_logic_value [get_pins buf1/Z]]
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set sv_reg_d [sta::pin_sim_logic_value [get_pins reg1/D]]
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set sv_reg_q [sta::pin_sim_logic_value [get_pins reg1/Q]]
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set sv_and_a1 [sta::pin_sim_logic_value [get_pins and1/A1]]
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set sv_and_a2 [sta::pin_sim_logic_value [get_pins and1/A2]]
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puts "and1/A1=$sv_and_a1 and1/A2=$sv_and_a2 and1/ZN=$sv_and buf1/Z=$sv_buf reg1/D=$sv_reg_d reg1/Q=$sv_reg_q"
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puts "PASS: sim logic values"
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puts "--- Case analysis effects on simulation ---"
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set_case_analysis 0 [get_ports in1]
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set sv_and_0 [sta::pin_sim_logic_value [get_pins and1/ZN]]
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puts "in1=0: and1/ZN=$sv_and_0"
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unset_case_analysis [get_ports in1]
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set_case_analysis 1 [get_ports in1]
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set sv_a1_1 [sta::pin_sim_logic_value [get_pins and1/A1]]
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puts "in1=1: and1/A1=$sv_a1_1"
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unset_case_analysis [get_ports in1]
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set_case_analysis 0 [get_ports in2]
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set sv_and_02 [sta::pin_sim_logic_value [get_pins and1/ZN]]
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puts "in2=0: and1/ZN=$sv_and_02"
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# With both inputs set
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set_case_analysis 1 [get_ports in1]
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set sv_and_10 [sta::pin_sim_logic_value [get_pins and1/ZN]]
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puts "in1=1,in2=0: and1/ZN=$sv_and_10"
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unset_case_analysis [get_ports in1]
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unset_case_analysis [get_ports in2]
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set_case_analysis 1 [get_ports in1]
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set_case_analysis 1 [get_ports in2]
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set sv_and_11 [sta::pin_sim_logic_value [get_pins and1/ZN]]
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puts "in1=1,in2=1: and1/ZN=$sv_and_11"
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unset_case_analysis [get_ports in1]
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unset_case_analysis [get_ports in2]
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puts "PASS: case analysis sim"
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puts "--- report_constant after case analysis ---"
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set_case_analysis 0 [get_ports in1]
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report_checks -path_delay max
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report_constant [get_ports in1]
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report_constant [get_cells and1]
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unset_case_analysis [get_ports in1]
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puts "PASS: report_constant"
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puts "--- disable_timing and re-levelize ---"
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set_disable_timing [get_cells buf1]
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report_checks -path_delay max
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sta::levelize
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unset_disable_timing [get_cells buf1]
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report_checks -path_delay max
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sta::levelize
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puts "PASS: disable_timing levelize"
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puts "--- Timing after set_disable_timing on lib cell ---"
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set_disable_timing -from A -to Z [get_lib_cells Nangate45_typ/BUF_X1]
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report_checks -path_delay max
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report_disabled_edges
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unset_disable_timing -from A -to Z [get_lib_cells Nangate45_typ/BUF_X1]
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report_checks -path_delay max
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puts "PASS: lib cell disable"
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puts "--- Check timing after clear/rerun ---"
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sta::find_timing_cmd 1
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report_checks -path_delay max
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puts "PASS: find_timing full"
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puts "--- find_timing not full ---"
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sta::arrivals_invalid
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sta::find_timing_cmd 0
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report_checks -path_delay max
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puts "PASS: find_timing incremental"
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puts "--- Preset/clear arcs ---"
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sta::set_preset_clr_arcs_enabled 1
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report_checks -path_delay max
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sta::set_preset_clr_arcs_enabled 0
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report_checks -path_delay max
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puts "PASS: preset_clr_arcs"
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puts "--- Conditional default arcs ---"
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sta::set_cond_default_arcs_enabled 1
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report_checks -path_delay max
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sta::set_cond_default_arcs_enabled 0
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report_checks -path_delay max
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puts "PASS: cond_default_arcs"
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puts "ALL PASSED"
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