331 lines
16 KiB
Plaintext
331 lines
16 KiB
Plaintext
--- report_annotated_delay ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 0 6
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internal net arcs 3 0 3
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net arcs from primary inputs 3 0 3
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net arcs to primary outputs 1 0 1
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----------------------------------------------------------------
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13 0 13
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PASS: report_annotated_delay default
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--- report_annotated_delay -list_annotated ---
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Warning: search_annotated_write_verilog.tcl line 1, -list_annotated is deprecated. Use -report_annotated.
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 0 6
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internal net arcs 3 0 3
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net arcs from primary inputs 3 0 3
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net arcs to primary outputs 1 0 1
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----------------------------------------------------------------
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13 0 13
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Annotated Arcs
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PASS: report_annotated_delay list_annotated
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--- report_annotated_delay -list_not_annotated ---
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Warning: search_annotated_write_verilog.tcl line 1, -list_not_annotated is deprecated. Use -report_unannotated.
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 0 6
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internal net arcs 3 0 3
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net arcs from primary inputs 3 0 3
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net arcs to primary outputs 1 0 1
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----------------------------------------------------------------
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13 0 13
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Unannotated Arcs
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primary input net clk -> reg1/CK
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primary input net in1 -> and1/A1
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primary input net in2 -> and1/A2
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delay and1/A1 -> and1/ZN
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delay and1/A2 -> and1/ZN
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internal net and1/ZN -> buf1/A
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delay buf1/A -> buf1/Z
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internal net buf1/Z -> reg1/D
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delay buf2/A -> buf2/Z
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primary output net buf2/Z -> out1
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delay reg1/CK -> reg1/QN
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delay reg1/CK -> reg1/Q
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internal net reg1/Q -> buf2/A
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PASS: report_annotated_delay list_not_annotated
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--- report_annotated_delay -list_not_annotated -max_lines 5 ---
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Warning: search_annotated_write_verilog.tcl line 1, -list_not_annotated is deprecated. Use -report_unannotated.
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 0 6
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internal net arcs 3 0 3
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net arcs from primary inputs 3 0 3
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net arcs to primary outputs 1 0 1
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----------------------------------------------------------------
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13 0 13
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Unannotated Arcs
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primary input net clk -> reg1/CK
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primary input net in1 -> and1/A1
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primary input net in2 -> and1/A2
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delay and1/A1 -> and1/ZN
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delay and1/A2 -> and1/ZN
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PASS: report_annotated_delay max_lines
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--- report_annotated_delay -constant_arcs ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 0 6
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constant arcs 0 0
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internal net arcs 3 0 3
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constant arcs 0 0
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net arcs from primary inputs 3 0 3
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constant arcs 0 0
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net arcs to primary outputs 1 0 1
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constant arcs 0 0
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----------------------------------------------------------------
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13 0 13
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PASS: report_annotated_delay constant_arcs
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--- report_annotated_check ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 0 1
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cell hold arcs 1 0 1
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cell width arcs 1 0 1
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----------------------------------------------------------------
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3 0 3
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PASS: report_annotated_check default
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--- report_annotated_check -setup ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 0 1
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----------------------------------------------------------------
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1 0 1
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PASS: report_annotated_check setup
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--- report_annotated_check -hold ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell hold arcs 1 0 1
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----------------------------------------------------------------
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1 0 1
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PASS: report_annotated_check hold
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--- report_annotated_check -setup -hold ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 0 1
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cell hold arcs 1 0 1
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----------------------------------------------------------------
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2 0 2
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PASS: report_annotated_check setup+hold
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--- report_annotated_check -list_annotated ---
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Warning: search_annotated_write_verilog.tcl line 1, -list_annotated is deprecated. Use -report_annotated.
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 0 1
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cell hold arcs 1 0 1
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cell width arcs 1 0 1
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----------------------------------------------------------------
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3 0 3
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Annotated Arcs
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PASS: report_annotated_check list_annotated
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--- report_annotated_check -list_not_annotated ---
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Warning: search_annotated_write_verilog.tcl line 1, -list_not_annotated is deprecated. Use -report_unannotated.
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 0 1
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cell hold arcs 1 0 1
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cell width arcs 1 0 1
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----------------------------------------------------------------
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3 0 3
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Unannotated Arcs
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width reg1/CK -> reg1/CK
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setup reg1/CK -> reg1/D
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hold reg1/CK -> reg1/D
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PASS: report_annotated_check list_not_annotated
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--- report_annotated_check -recovery ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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PASS: report_annotated_check recovery
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--- report_annotated_check -removal ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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PASS: report_annotated_check removal
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--- report_annotated_check -width ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell width arcs 1 0 1
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----------------------------------------------------------------
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1 0 1
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PASS: report_annotated_check width
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--- report_annotated_check -period ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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PASS: report_annotated_check period
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--- report_annotated_check -max_skew ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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PASS: report_annotated_check max_skew
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--- report_annotated_check -nochange ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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PASS: report_annotated_check nochange
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--- report_disabled_edges ---
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PASS: report_disabled_edges default
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--- disable + report_disabled_edges ---
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buf1 A Z constraint
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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PASS: disable + report_disabled_edges
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--- disable lib cell + report_disabled_edges ---
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buf1 A Z constraint
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buf2 A Z constraint
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No paths found.
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PASS: disable lib cell + report_disabled_edges
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--- write_sdf divider . ---
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PASS: write_sdf divider .
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--- write_sdf divider / ---
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PASS: write_sdf divider /
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--- write_sdf include_typ ---
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PASS: write_sdf include_typ
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--- write_sdf digits 6 ---
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PASS: write_sdf digits 6
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--- write_sdf digits 1 ---
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PASS: write_sdf digits 1
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--- write_verilog ---
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PASS: write_verilog default
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--- write_verilog -include_pwr_gnd ---
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PASS: write_verilog include_pwr_gnd
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--- write_verilog -remove_cells ---
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PASS: write_verilog remove_cells
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--- read_sdf ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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PASS: read_sdf
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--- report_annotated_delay after read_sdf ---
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Warning: search_annotated_write_verilog.tcl line 1, -list_annotated is deprecated. Use -report_annotated.
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 6 0
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internal net arcs 3 3 0
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net arcs from primary inputs 3 3 0
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net arcs to primary outputs 1 1 0
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----------------------------------------------------------------
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13 13 0
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Annotated Arcs
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primary input net clk -> reg1/CK
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primary input net in1 -> and1/A1
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primary input net in2 -> and1/A2
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delay and1/A1 -> and1/ZN
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delay and1/A2 -> and1/ZN
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internal net and1/ZN -> buf1/A
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delay buf1/A -> buf1/Z
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internal net buf1/Z -> reg1/D
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delay buf2/A -> buf2/Z
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primary output net buf2/Z -> out1
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delay reg1/CK -> reg1/QN
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delay reg1/CK -> reg1/Q
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internal net reg1/Q -> buf2/A
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PASS: report_annotated after read_sdf
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--- report_annotated_check after read_sdf ---
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Warning: search_annotated_write_verilog.tcl line 1, -list_annotated is deprecated. Use -report_annotated.
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 1 0
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cell hold arcs 1 1 0
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----------------------------------------------------------------
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2 2 0
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Annotated Arcs
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setup reg1/CK -> reg1/D
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hold reg1/CK -> reg1/D
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PASS: report_annotated_check after read_sdf
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--- remove_delay_slew_annotations ---
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PASS: remove_delay_slew_annotations
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--- report_annotated_delay after remove ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 0 6
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internal net arcs 3 0 3
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net arcs from primary inputs 3 0 3
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net arcs to primary outputs 1 0 1
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----------------------------------------------------------------
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13 0 13
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PASS: report_annotated_delay after remove
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ALL PASSED
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