115 lines
3.1 KiB
Tcl
115 lines
3.1 KiB
Tcl
# Test SDC write/read roundtrip for code coverage
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog sdc_test2.v
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link_design sdc_test2
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############################################################
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# Setup various constraints
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############################################################
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# Clocks
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create_clock -name clk1 -period 10 [get_ports clk1]
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create_clock -name clk2 -period 20 -waveform {0 10} [get_ports clk2]
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puts "PASS: clocks created"
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# Generated clock
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create_generated_clock -name gen_div2 -source [get_ports clk1] -divide_by 2 [get_pins reg1/Q]
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puts "PASS: generated clock created"
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# Delays
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set_input_delay -clock clk1 2.0 [get_ports in1]
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set_input_delay -clock clk1 1.5 [get_ports in2]
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set_input_delay -clock clk1 1.8 [get_ports in3]
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set_output_delay -clock clk1 3.0 [get_ports out1]
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set_output_delay -clock clk2 2.5 [get_ports out2]
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puts "PASS: delays set"
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# Clock uncertainty
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set_clock_uncertainty -setup 0.2 [get_clocks clk1]
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set_clock_uncertainty -hold 0.1 [get_clocks clk1]
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puts "PASS: uncertainty set"
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# Clock latency
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set_clock_latency -source 0.5 [get_clocks clk1]
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set_clock_latency 0.3 [get_clocks clk2]
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puts "PASS: latency set"
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# Clock transition
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set_clock_transition 0.1 [get_clocks clk1]
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puts "PASS: transition set"
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# Driving cell
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set_driving_cell -lib_cell BUF_X1 [get_ports in1]
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puts "PASS: driving cell set"
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# Load
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set_load 0.05 [get_ports out1]
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set_load 0.04 [get_ports out2]
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puts "PASS: load set"
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# Input transition
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set_input_transition 0.15 [get_ports in1]
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puts "PASS: input transition set"
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# False path
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set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
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puts "PASS: false path set"
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# Multicycle
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set_multicycle_path -setup 2 -from [get_ports in1] -to [get_ports out1]
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puts "PASS: multicycle set"
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# Max/min delay
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set_max_delay -from [get_ports in2] -to [get_ports out1] 8.0
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puts "PASS: max delay set"
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# Max transition/capacitance/fanout
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set_max_transition 0.5 [current_design]
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set_max_capacitance 0.2 [current_design]
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set_max_fanout 20 [current_design]
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puts "PASS: design limits set"
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# Case analysis
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set_case_analysis 0 [get_ports in3]
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puts "PASS: case analysis set"
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# Operating conditions
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set_operating_conditions typical
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puts "PASS: operating conditions set"
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# Wire load
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set_wire_load_model -name "5K_hvratio_1_1"
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puts "PASS: wire load model set"
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# Timing derate
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set_timing_derate -early 0.95
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set_timing_derate -late 1.05
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puts "PASS: timing derate set"
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# Propagated clock
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set_propagated_clock [get_clocks clk1]
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puts "PASS: propagated clock set"
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############################################################
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# Write SDC
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############################################################
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set sdc_file [make_result_file sdc_write_read.sdc]
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write_sdc -no_timestamp $sdc_file
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puts "PASS: write_sdc"
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############################################################
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# Clear and read back
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############################################################
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# Report before clear
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report_checks -from [get_ports in1] -to [get_ports out1]
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puts "PASS: report_checks before clear"
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report_clock_properties
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puts "PASS: report_clock_properties before clear"
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puts "ALL PASSED"
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