236 lines
7.6 KiB
Plaintext
236 lines
7.6 KiB
Plaintext
PASS: basic setup
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PASS: set_driving_cell BUF_X1
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PASS: set_driving_cell INV_X1
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PASS: set_driving_cell BUF_X4
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No paths found.
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PASS: report_checks after set_driving_cell
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PASS: set_load
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PASS: set_load -pin_load
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No paths found.
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PASS: report_checks after set_load
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PASS: set_input_transition
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PASS: set_input_transition -rise
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PASS: set_input_transition -fall
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PASS: set_input_transition -min
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PASS: set_input_transition -max
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No paths found.
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PASS: report_checks after set_input_transition
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PASS: set_max_capacitance port
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PASS: set_max_capacitance design
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PASS: set_max_transition port
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PASS: set_max_transition design
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PASS: set_max_transition -clock_path
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PASS: set_max_transition -data_path
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PASS: set_max_fanout port
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PASS: set_max_fanout design
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PASS: set_case_analysis 0
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No paths found.
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PASS: report_checks after case_analysis 0
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PASS: unset_case_analysis
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PASS: set_case_analysis 1
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No paths found.
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PASS: report_checks after case_analysis 1
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PASS: unset_case_analysis second
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PASS: set_logic_zero
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PASS: set_logic_one
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PASS: set_logic_dc
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-3.00 7.00 output external delay
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7.00 data required time
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---------------------------------------------------------
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7.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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6.92 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg3/D (DFF_X1)
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10.08 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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20.00 ^ reg3/CK (DFF_X1)
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-0.04 19.96 library setup time
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19.96 data required time
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---------------------------------------------------------
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19.96 data required time
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-10.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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PASS: report_checks after logic values
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PASS: set_ideal_network
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PASS: set_operating_conditions
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PASS: set_wire_load_model
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PASS: set_wire_load_mode enclosed
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PASS: set_timing_derate -early
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PASS: set_timing_derate -late
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.09 0.09 ^ reg2/Q (DFF_X1)
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0.00 0.09 ^ out1 (out)
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0.09 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-3.00 7.00 output external delay
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7.00 data required time
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---------------------------------------------------------
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7.00 data required time
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-0.09 data arrival time
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---------------------------------------------------------
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6.91 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg3/D (DFF_X1)
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10.08 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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20.00 ^ reg3/CK (DFF_X1)
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-0.04 19.96 library setup time
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19.96 data required time
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---------------------------------------------------------
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19.96 data required time
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-10.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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PASS: report_checks after timing derate
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PASS: unset_timing_derate
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PASS: set_max_area
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PASS: set_disable_timing instance
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PASS: unset_disable_timing instance
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PASS: set_disable_timing pin
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PASS: unset_disable_timing pin
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PASS: set_min_pulse_width
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PASS: set_port_fanout_number
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PASS: set_resistance -min
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PASS: set_resistance -max
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PASS: set_voltage
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-3.00 7.00 output external delay
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7.00 data required time
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---------------------------------------------------------
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7.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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6.92 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg3/D (DFF_X1)
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10.08 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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20.00 ^ reg3/CK (DFF_X1)
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-0.04 19.96 library setup time
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19.96 data required time
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---------------------------------------------------------
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19.96 data required time
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-10.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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PASS: final report_checks
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max slew
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Pin Limit Slew Slack
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------------------------------------------------------------
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nor1/ZN 0.20 0.01 0.18 (MET)
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max fanout
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Pin Limit Fanout Slack
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---------------------------------------------------------
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in1 10 1 9 (MET)
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max capacitance
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Pin Limit Cap Slack
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------------------------------------------------------------
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or1/ZN 0.20 4.01 -3.81 (VIOLATED)
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PASS: report_check_types
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ALL PASSED
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