OpenSTA/sdc/test/sdc_capacitance_propagated.ok

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PASS: setup
PASS: set_load basic
PASS: set_load -pin_load
PASS: set_load -wire_load
PASS: set_load out2 pin
PASS: set_load rise/fall
PASS: set_load wire rise/fall
PASS: set_load min/max
PASS: set_load pin min/max
PASS: port fanout
PASS: set_load on nets
PASS: max_capacitance design
PASS: max_capacitance ports
PASS: min_capacitance ports
PASS: max_capacitance pin
PASS: max_transition
PASS: max_fanout
PASS: max_area
PASS: write_sdc with loads
PASS: set_propagated_clock clk1
PASS: set_propagated_clock port clk2
PASS: write_sdc with propagated
PASS: unset_propagated_clock clk1
PASS: unset_propagated_clock port clk2
PASS: write_sdc after unset propagated
PASS: case_analysis 0
PASS: case_analysis 1
PASS: case_analysis rising
PASS: write_sdc with case analysis
PASS: unset case_analysis in1
PASS: unset case_analysis in2
PASS: unset case_analysis in3
PASS: case_analysis falling
PASS: write_sdc with falling
PASS: unset falling
PASS: logic values
PASS: write_sdc with logic values
PASS: read_sdc
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
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0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.08 data arrival time
---------------------------------------------------------
6.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 ^ reg1/CK (DFF_X1)
0.08 10.08 v reg1/Q (DFF_X1)
0.00 10.08 v reg3/D (DFF_X1)
10.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ reg3/CK (DFF_X1)
-0.04 19.96 library setup time
19.96 data required time
---------------------------------------------------------
19.96 data required time
-10.08 data arrival time
---------------------------------------------------------
9.88 slack (MET)
PASS: report after read
PASS: write_sdc roundtrip
PASS: read_sdc propagated
PASS: write_sdc compatible roundtrip
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (propagated)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (propagated)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.08 data arrival time
---------------------------------------------------------
6.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (propagated)
0.00 10.00 ^ reg1/CK (DFF_X1)
0.08 10.08 v reg1/Q (DFF_X1)
0.00 10.08 v reg3/D (DFF_X1)
10.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (propagated)
0.00 20.00 clock reconvergence pessimism
20.00 ^ reg3/CK (DFF_X1)
-0.04 19.96 library setup time
19.96 data required time
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19.96 data required time
-10.08 data arrival time
---------------------------------------------------------
9.88 slack (MET)
PASS: final report
ALL PASSED