109 lines
3.4 KiB
Tcl
109 lines
3.4 KiB
Tcl
# Test design rules, limits, and WriteSdc.cc design rules paths.
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# Targets:
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# Sdc.cc: setSlewLimit (port, cell, clock with clk_data/rf),
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# setCapacitanceLimit (port, pin, cell),
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# setFanoutLimit (port, cell), setMaxArea,
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# slewLimit, capacitanceLimit, fanoutLimit,
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# setMinPulseWidth (global, pin, clock, instance),
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# setLatchBorrowLimit (pin, instance, clock)
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# WriteSdc.cc: writeDesignRules, writeMinPulseWidths,
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# writeLatchBorowLimits, writeSlewLimits, writeClkSlewLimits,
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# writeClkSlewLimit, writeCapLimits (min/max with port/pin),
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# writeFanoutLimits (min/max with port), writeMaxArea,
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# writeMinPulseWidth (hi/low variants)
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# Clock.cc: slewLimit with PathClkOrData
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog sdc_test2.v
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link_design sdc_test2
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create_clock -name clk1 -period 10 [get_ports clk1]
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create_clock -name clk2 -period 20 [get_ports clk2]
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set_input_delay -clock clk1 2.0 [get_ports in1]
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set_input_delay -clock clk1 2.0 [get_ports in2]
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set_input_delay -clock clk2 2.0 [get_ports in3]
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set_output_delay -clock clk1 3.0 [get_ports out1]
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set_output_delay -clock clk2 3.0 [get_ports out2]
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# Max/min transition limits on design, ports, and clocks
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set_max_transition 0.5 [current_design]
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set_max_transition 0.3 [get_ports out1]
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set_max_transition 0.35 [get_ports out2]
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# Clock-specific slew limits (exercises writeClkSlewLimits)
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set_max_transition -clock_path 0.2 [get_clocks clk1]
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set_max_transition -data_path 0.4 [get_clocks clk1]
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# Per-rise/fall on clock data path
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set_max_transition -clock_path -rise 0.18 [get_clocks clk2]
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set_max_transition -clock_path -fall 0.22 [get_clocks clk2]
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set_max_transition -data_path -rise 0.38 [get_clocks clk2]
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set_max_transition -data_path -fall 0.42 [get_clocks clk2]
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# Max/min capacitance limits
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set_max_capacitance 0.2 [current_design]
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set_max_capacitance 0.1 [get_ports out1]
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set_max_capacitance 0.15 [get_ports out2]
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# Pin-level cap limits
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set_max_capacitance 0.08 [get_pins reg1/Q]
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# Min capacitance
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set_min_capacitance 0.001 [current_design]
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set_min_capacitance 0.0005 [get_ports out1]
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# Max/min fanout limits
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set_max_fanout 20 [current_design]
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set_max_fanout 10 [get_ports in1]
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set_max_fanout 15 [get_ports in2]
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# Max area
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set_max_area 500.0
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# Min pulse width on various targets
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# Global min pulse width
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set_min_pulse_width 0.5
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# Clock min pulse width with high/low
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set_min_pulse_width -high 0.6 [get_clocks clk1]
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set_min_pulse_width -low 0.4 [get_clocks clk1]
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# Same value for high and low (exercises equal path)
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set_min_pulse_width 0.7 [get_clocks clk2]
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# Pin min pulse width
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set_min_pulse_width 0.3 [get_pins reg1/CK]
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set_min_pulse_width -high 0.35 [get_pins reg2/CK]
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set_min_pulse_width -low 0.25 [get_pins reg2/CK]
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# Instance min pulse width
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set_min_pulse_width 0.45 [get_cells reg3]
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# Latch borrow limits
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set_max_time_borrow 2.0 [get_clocks clk1]
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set_max_time_borrow 1.5 [get_clocks clk2]
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set_max_time_borrow 1.0 [get_pins reg1/D]
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set_max_time_borrow 1.2 [get_cells reg2]
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# Port slew limits
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set_max_transition 0.25 [get_ports in1]
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set_max_transition 0.28 [get_ports in2]
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# Write SDC (exercises all design rule writing paths)
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set sdc1 [make_result_file sdc_design_rules1.sdc]
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write_sdc -no_timestamp $sdc1
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set sdc2 [make_result_file sdc_design_rules2.sdc]
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write_sdc -no_timestamp -compatible $sdc2
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set sdc3 [make_result_file sdc_design_rules3.sdc]
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write_sdc -no_timestamp -digits 8 $sdc3
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