49 lines
1.8 KiB
Tcl
49 lines
1.8 KiB
Tcl
# Test 6: Write assign/tristate design with removes
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source ../../test/helpers.tcl
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suppress_msg 1140
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proc assert_file_not_contains {path token} {
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set in [open $path r]
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set text [read $in]
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close $in
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if {[string first $token $text] >= 0} {
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error "did not expect '$token' in $path"
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}
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}
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#---------------------------------------------------------------
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# Test 6: Write assign/tristate design with removes
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#---------------------------------------------------------------
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puts "--- Test 6: supply/tristate with removes ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_supply_tristate.v
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link_design verilog_supply_tristate
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set out_st_rm [make_result_file verilog_remove_supply_buf.v]
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write_verilog -remove_cells {BUF_X1} $out_st_rm
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assert_file_nonempty $out_st_rm
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assert_file_contains $out_st_rm "module verilog_supply_tristate"
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assert_file_not_contains $out_st_rm "BUF_X1"
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set out_st_pwr [make_result_file verilog_remove_supply_pwr.v]
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write_verilog -include_pwr_gnd -remove_cells {INV_X1} $out_st_pwr
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assert_file_nonempty $out_st_pwr
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assert_file_contains $out_st_pwr "module verilog_supply_tristate"
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assert_file_not_contains $out_st_pwr "INV_X1"
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assert_file_contains $out_st_pwr "wire gnd_net;"
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diff_files verilog_remove_supply_buf.vok $out_st_rm
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diff_files verilog_remove_supply_pwr.vok $out_st_pwr
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog $out_st_rm
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link_design verilog_supply_tristate
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports {in1 in2 in3 en}]
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set_output_delay -clock clk 0 [get_ports {out1 out2 out3 outbus[*]}]
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set_input_transition 0.1 [all_inputs]
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with_output_to_variable st_rep { report_checks -path_delay max }
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if {![regexp {Path Type:\s+max} $st_rep]} {
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error "remove_cells supply roundtrip timing report missing max path"
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}
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