65 lines
2.0 KiB
Tcl
65 lines
2.0 KiB
Tcl
# Test 1: Write verilog for bus design (exercises bus wire declarations)
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# Test 2: Read back written bus verilog (roundtrip)
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source ../../test/helpers.tcl
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suppress_msg 1140
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#---------------------------------------------------------------
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# Test 1: Write verilog for bus design (exercises bus wire declarations)
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#---------------------------------------------------------------
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puts "--- Test 1: write bus design ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_bus_test.v
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link_design verilog_bus_test
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set cells [get_cells *]
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puts "cells: [llength $cells]"
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set nets [get_nets *]
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puts "nets: [llength $nets]"
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set ports [get_ports *]
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puts "ports: [llength $ports]"
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# Write basic
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set out1 [make_result_file verilog_escaped_bus.v]
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write_verilog $out1
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# Write with pwr_gnd
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set out2 [make_result_file verilog_escaped_bus_pwr.v]
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write_verilog -include_pwr_gnd $out2
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diff_files verilog_escaped_bus.vok $out1
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diff_files verilog_escaped_bus_pwr.vok $out2
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#---------------------------------------------------------------
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# Test 2: Read back written bus verilog (roundtrip)
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# Exercises: verilogToSta on bus names, bus port parsing
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#---------------------------------------------------------------
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puts "--- Test 2: roundtrip bus design ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog $out1
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link_design verilog_bus_test
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set rt_cells [get_cells *]
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puts "roundtrip cells: [llength $rt_cells]"
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set rt_nets [get_nets *]
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puts "roundtrip nets: [llength $rt_nets]"
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set rt_ports [get_ports *]
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puts "roundtrip ports: [llength $rt_ports]"
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# Verify bus ports after roundtrip
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set rt_din [get_ports {data_in[*]}]
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puts "roundtrip data_in[*]: [llength $rt_din]"
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set rt_dout [get_ports {data_out[*]}]
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puts "roundtrip data_out[*]: [llength $rt_dout]"
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# Timing after roundtrip
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports {data_in[*]}]
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set_output_delay -clock clk 0 [get_ports {data_out[*]}]
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set_input_transition 0.1 [all_inputs]
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report_checks
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