256 lines
13 KiB
Plaintext
256 lines
13 KiB
Plaintext
--- read_sdf ---
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--- report_annotated_delay (all) ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 3 2 1
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internal net arcs 1 0 1
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net arcs from primary inputs 2 0 2
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net arcs to primary outputs 1 0 1
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----------------------------------------------------------------
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7 2 5
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--- report_annotated_delay -cell ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 3 2 1
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----------------------------------------------------------------
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3 2 1
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--- report_annotated_delay -net ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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internal net arcs 1 0 1
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----------------------------------------------------------------
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1 0 1
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--- report_annotated_delay -from_in_ports ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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net arcs from primary inputs 2 0 2
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----------------------------------------------------------------
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2 0 2
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--- report_annotated_delay -to_out_ports ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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net arcs to primary outputs 1 0 1
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----------------------------------------------------------------
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1 0 1
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--- report_annotated_delay -cell -report_annotated ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 3 2 1
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----------------------------------------------------------------
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3 2 1
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Annotated Arcs
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delay buf1/A -> buf1/Z
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delay reg1/CK -> reg1/Q
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--- report_annotated_delay -cell -report_unannotated ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 3 2 1
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----------------------------------------------------------------
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3 2 1
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Unannotated Arcs
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delay reg1/CK -> reg1/QN
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--- report_annotated_delay -constant_arcs ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 3 2 1
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constant arcs 0 0
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internal net arcs 1 0 1
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constant arcs 0 0
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net arcs from primary inputs 2 0 2
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constant arcs 0 0
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net arcs to primary outputs 1 0 1
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constant arcs 0 0
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----------------------------------------------------------------
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7 2 5
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--- report_annotated_delay -max_lines 5 ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 3 2 1
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internal net arcs 1 0 1
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net arcs from primary inputs 2 0 2
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net arcs to primary outputs 1 0 1
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----------------------------------------------------------------
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7 2 5
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--- report_annotated_check (all) ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 0 1
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cell hold arcs 1 0 1
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cell width arcs 1 0 1
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----------------------------------------------------------------
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3 0 3
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--- report_annotated_check -setup ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 0 1
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----------------------------------------------------------------
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1 0 1
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--- report_annotated_check -hold ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell hold arcs 1 0 1
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----------------------------------------------------------------
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1 0 1
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--- report_annotated_check -recovery ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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--- report_annotated_check -removal ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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--- report_annotated_check -width ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell width arcs 1 0 1
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----------------------------------------------------------------
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1 0 1
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--- report_annotated_check -period ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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----------------------------------------------------------------
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0 0 0
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--- report_annotated_check -setup -report_annotated ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 0 1
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----------------------------------------------------------------
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1 0 1
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Annotated Arcs
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--- report_annotated_check -setup -report_unannotated ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 0 1
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----------------------------------------------------------------
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1 0 1
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Unannotated Arcs
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setup reg1/CK -> reg1/D
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--- report_annotated_check -constant_arcs ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 0 1
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constant arcs 0 0
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cell hold arcs 1 0 1
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constant arcs 0 0
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cell width arcs 1 0 1
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constant arcs 0 0
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----------------------------------------------------------------
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3 0 3
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--- report_annotated_check -max_lines 5 ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 0 1
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cell hold arcs 1 0 1
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cell width arcs 1 0 1
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----------------------------------------------------------------
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3 0 3
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--- report_checks (shows annotated delays) ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: q (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.40 0.40 ^ reg1/Q (DFF_X1)
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0.00 0.40 ^ q (out)
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0.40 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.40 data arrival time
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---------------------------------------------------------
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9.60 slack (MET)
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--- report_checks -format full_clock ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: q (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.40 0.40 ^ reg1/Q (DFF_X1)
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0.00 0.40 ^ q (out)
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0.40 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.40 data arrival time
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---------------------------------------------------------
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9.60 slack (MET)
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--- report_checks -path_delay min ---
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Startpoint: d (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ d (in)
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0.10 0.10 ^ buf1/Z (BUF_X1)
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0.00 0.10 ^ reg1/D (DFF_X1)
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0.10 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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0.10 slack (MET)
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