60 lines
1.0 KiB
Plaintext
60 lines
1.0 KiB
Plaintext
* Path from reg1/Q ^ to out1 ^
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.include "/workspace/sta/OpenSTA/spice/test/results/spice_out/mock_model.sp"
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.include "path_1.subckt"
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.tran 1e-13 3.1e-08
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.print tran v(clk) v(reg1/CK) v(reg1/Q) v(out1)
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**************
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* Input source
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**************
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v1 clk 0 pwl(
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+0.000e+00 0.000e+00
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+9.985e-10 0.000e+00
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+1.001e-09 1.100e+00
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+5.999e-09 1.100e+00
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+6.001e-09 0.000e+00
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+1.100e-08 0.000e+00
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+1.100e-08 1.100e+00
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+1.600e-08 1.100e+00
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+1.600e-08 0.000e+00
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+2.100e-08 0.000e+00
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+2.100e-08 1.100e+00
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+2.600e-08 1.100e+00
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+2.600e-08 0.000e+00
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+3.100e-08 0.000e+00
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+)
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*****************
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* Stage instances
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*****************
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xstage1 clk reg1/CK stage1
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xstage2 reg1/CK reg1/Q out1 stage2
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***************
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* Stage subckts
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***************
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.subckt stage1 clk reg1/CK
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* Net clk
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* Net has no parasitics.
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R1 clk reg1/CK 1.000e-04
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.ends
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.subckt stage2 reg1/CK reg1/Q out1
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* Gate reg1 CK -> Q
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xreg1 reg1/D reg1/CK reg1/Q reg1/VDD reg1/VSS DFF_X1
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v1 reg1/D 0 1.100
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v2 reg1/VDD 0 1.100
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v3 reg1/VSS 0 0.000
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* Load pins
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* Net out1
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* Net has no parasitics.
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R1 reg1/Q out1 1.000e-04
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.ends
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.end
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