1477 lines
31 KiB
Plaintext
1477 lines
31 KiB
Plaintext
--- report_checks -format json (multiple endpoints) ---
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{"checks": [
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{
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"type": "output_delay",
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"path_group": "clk",
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"path_type": "max",
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"startpoint": "reg1/Q",
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"endpoint": "out1",
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"source_clock": "clk",
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"source_clock_edge": "rise",
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"source_clock_path": [
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{
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"instance": "",
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"cell": "search_test1",
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"verilog_src": "",
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"pin": "clk",
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"arrival": 0.000e+00,
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"capacitance": 9.497e-16,
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"slew": 0.000e+00
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},
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{
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"instance": "reg1",
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"cell": "DFF_X1",
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"verilog_src": "",
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"pin": "reg1/CK",
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"net": "clk",
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"arrival": 0.000e+00,
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"slew": 0.000e+00
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}
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],
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"source_path": [
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{
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"instance": "reg1",
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"cell": "DFF_X1",
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"verilog_src": "",
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"pin": "reg1/Q",
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"net": "n3",
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"arrival": 8.371e-11,
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"capacitance": 9.747e-16,
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"slew": 7.314e-12
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},
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{
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"instance": "buf2",
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"cell": "BUF_X1",
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"verilog_src": "",
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"pin": "buf2/A",
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"net": "n3",
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"arrival": 8.371e-11,
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"slew": 7.314e-12
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},
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{
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"instance": "buf2",
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"cell": "BUF_X1",
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"verilog_src": "",
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"pin": "buf2/Z",
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"net": "out1",
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"arrival": 1.003e-10,
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"capacitance": 0.000e+00,
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"slew": 3.638e-12
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},
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{
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"instance": "",
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"cell": "search_test1",
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"verilog_src": "",
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"pin": "out1",
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"arrival": 1.003e-10,
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"slew": 3.638e-12
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}
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],
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"target_clock": "clk",
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"target_clock_edge": "rise",
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"data_arrival_time": 1.003e-10,
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"crpr": 0.000e+00,
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"margin": 2.000e-09,
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"required_time": 8.000e-09,
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"slack": 7.900e-09
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},
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{
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"type": "output_delay",
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"path_group": "clk",
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"path_type": "max",
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"startpoint": "reg1/Q",
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"endpoint": "out1",
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"source_clock": "clk",
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"source_clock_edge": "rise",
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"source_clock_path": [
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{
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"instance": "",
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"cell": "search_test1",
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"verilog_src": "",
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"pin": "clk",
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"arrival": 0.000e+00,
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"capacitance": 9.497e-16,
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"slew": 0.000e+00
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},
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{
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"instance": "reg1",
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"cell": "DFF_X1",
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"verilog_src": "",
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"pin": "reg1/CK",
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"net": "clk",
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"arrival": 0.000e+00,
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"slew": 0.000e+00
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}
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],
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"source_path": [
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{
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"instance": "reg1",
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"cell": "DFF_X1",
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"verilog_src": "",
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"pin": "reg1/Q",
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"net": "n3",
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"arrival": 7.722e-11,
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"capacitance": 8.752e-16,
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"slew": 5.624e-12
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},
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{
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"instance": "buf2",
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"cell": "BUF_X1",
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"verilog_src": "",
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"pin": "buf2/A",
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"net": "n3",
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"arrival": 7.722e-11,
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"slew": 5.624e-12
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},
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{
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"instance": "buf2",
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"cell": "BUF_X1",
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"verilog_src": "",
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"pin": "buf2/Z",
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"net": "out1",
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"arrival": 9.857e-11,
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"capacitance": 0.000e+00,
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"slew": 3.903e-12
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},
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{
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"instance": "",
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"cell": "search_test1",
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"verilog_src": "",
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"pin": "out1",
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"arrival": 9.857e-11,
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"slew": 3.903e-12
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}
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],
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"target_clock": "clk",
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"target_clock_edge": "rise",
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"data_arrival_time": 9.857e-11,
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"crpr": 0.000e+00,
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"margin": 2.000e-09,
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"required_time": 8.000e-09,
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"slack": 7.901e-09
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},
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{
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"type": "check",
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"path_group": "clk",
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"path_type": "max",
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"startpoint": "in2",
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"endpoint": "reg1/D",
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"source_clock": "clk",
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"source_clock_edge": "rise",
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"source_path": [
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{
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"instance": "",
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"cell": "search_test1",
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"verilog_src": "",
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"pin": "in2",
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"arrival": 1.000e-09,
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"capacitance": 8.941e-16,
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"slew": 0.000e+00
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},
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{
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"instance": "and1",
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"cell": "AND2_X1",
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"verilog_src": "",
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"pin": "and1/A2",
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"net": "in2",
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"arrival": 1.000e-09,
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"slew": 0.000e+00
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},
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{
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"instance": "and1",
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"cell": "AND2_X1",
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"verilog_src": "",
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"pin": "and1/ZN",
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"net": "n1",
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"arrival": 1.025e-09,
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"capacitance": 8.752e-16,
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"slew": 5.258e-12
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},
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{
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"instance": "buf1",
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"cell": "BUF_X1",
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"verilog_src": "",
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"pin": "buf1/A",
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"net": "n1",
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"arrival": 1.025e-09,
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"slew": 5.258e-12
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},
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{
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"instance": "buf1",
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"cell": "BUF_X1",
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"verilog_src": "",
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"pin": "buf1/Z",
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"net": "n2",
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"arrival": 1.048e-09,
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"capacitance": 1.062e-15,
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"slew": 5.011e-12
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},
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{
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"instance": "reg1",
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"cell": "DFF_X1",
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"verilog_src": "",
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"pin": "reg1/D",
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"net": "n2",
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"arrival": 1.048e-09,
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"slew": 5.011e-12
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}
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],
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"target_clock": "clk",
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"target_clock_edge": "rise",
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"target_clock_path": [
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{
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"instance": "",
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"cell": "search_test1",
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"verilog_src": "",
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"pin": "clk",
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"arrival": 0.000e+00,
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"capacitance": 9.497e-16,
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"slew": 0.000e+00
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},
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{
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"instance": "reg1",
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"cell": "DFF_X1",
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"verilog_src": "",
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"pin": "reg1/CK",
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"net": "clk",
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"arrival": 0.000e+00,
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"slew": 0.000e+00
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}
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],
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"data_arrival_time": 1.048e-09,
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"crpr": 0.000e+00,
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"margin": 3.878e-11,
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"required_time": 9.961e-09,
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"slack": 8.913e-09
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},
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{
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"type": "check",
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"path_group": "clk",
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"path_type": "max",
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"startpoint": "in1",
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"endpoint": "reg1/D",
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"source_clock": "clk",
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"source_clock_edge": "rise",
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"source_path": [
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{
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"instance": "",
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"cell": "search_test1",
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"verilog_src": "",
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"pin": "in1",
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"arrival": 1.000e-09,
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"capacitance": 8.748e-16,
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"slew": 0.000e+00
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},
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{
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"instance": "and1",
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"cell": "AND2_X1",
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"verilog_src": "",
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"pin": "and1/A1",
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"net": "in1",
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"arrival": 1.000e-09,
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"slew": 0.000e+00
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},
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{
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"instance": "and1",
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"cell": "AND2_X1",
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"verilog_src": "",
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"pin": "and1/ZN",
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"net": "n1",
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"arrival": 1.022e-09,
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"capacitance": 8.752e-16,
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"slew": 5.258e-12
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},
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{
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"instance": "buf1",
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"cell": "BUF_X1",
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"verilog_src": "",
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"pin": "buf1/A",
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"net": "n1",
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"arrival": 1.022e-09,
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"slew": 5.258e-12
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},
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{
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"instance": "buf1",
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"cell": "BUF_X1",
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"verilog_src": "",
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"pin": "buf1/Z",
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"net": "n2",
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"arrival": 1.046e-09,
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"capacitance": 1.062e-15,
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"slew": 5.011e-12
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},
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{
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"instance": "reg1",
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"cell": "DFF_X1",
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"verilog_src": "",
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"pin": "reg1/D",
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"net": "n2",
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"arrival": 1.046e-09,
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"slew": 5.011e-12
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}
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],
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"target_clock": "clk",
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"target_clock_edge": "rise",
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"target_clock_path": [
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{
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"instance": "",
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"cell": "search_test1",
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"verilog_src": "",
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"pin": "clk",
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"arrival": 0.000e+00,
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"capacitance": 9.497e-16,
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"slew": 0.000e+00
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},
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{
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"instance": "reg1",
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"cell": "DFF_X1",
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"verilog_src": "",
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"pin": "reg1/CK",
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"net": "clk",
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"arrival": 0.000e+00,
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"slew": 0.000e+00
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}
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],
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"data_arrival_time": 1.046e-09,
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"crpr": 0.000e+00,
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"margin": 3.878e-11,
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"required_time": 9.961e-09,
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"slack": 8.915e-09
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},
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{
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"type": "check",
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"path_group": "clk",
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"path_type": "max",
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"startpoint": "in2",
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"endpoint": "reg1/D",
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"source_clock": "clk",
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"source_clock_edge": "rise",
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"source_path": [
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{
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"instance": "",
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"cell": "search_test1",
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"verilog_src": "",
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"pin": "in2",
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"arrival": 1.000e-09,
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"capacitance": 9.746e-16,
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"slew": 0.000e+00
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},
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{
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"instance": "and1",
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"cell": "AND2_X1",
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"verilog_src": "",
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"pin": "and1/A2",
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"net": "in2",
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"arrival": 1.000e-09,
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"slew": 0.000e+00
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},
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{
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"instance": "and1",
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"cell": "AND2_X1",
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"verilog_src": "",
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"pin": "and1/ZN",
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"net": "n1",
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"arrival": 1.026e-09,
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"capacitance": 9.747e-16,
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"slew": 7.001e-12
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},
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{
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"instance": "buf1",
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"cell": "BUF_X1",
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"verilog_src": "",
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"pin": "buf1/A",
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"net": "n1",
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"arrival": 1.026e-09,
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"slew": 7.001e-12
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},
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{
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"instance": "buf1",
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"cell": "BUF_X1",
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"verilog_src": "",
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"pin": "buf1/Z",
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"net": "n2",
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"arrival": 1.045e-09,
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"capacitance": 1.140e-15,
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"slew": 5.947e-12
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},
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{
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"instance": "reg1",
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"cell": "DFF_X1",
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"verilog_src": "",
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"pin": "reg1/D",
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"net": "n2",
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"arrival": 1.045e-09,
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"slew": 5.947e-12
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}
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],
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"target_clock": "clk",
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"target_clock_edge": "rise",
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"target_clock_path": [
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{
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"instance": "",
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"cell": "search_test1",
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"verilog_src": "",
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"pin": "clk",
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"arrival": 0.000e+00,
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"capacitance": 9.497e-16,
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"slew": 0.000e+00
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},
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{
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"instance": "reg1",
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"cell": "DFF_X1",
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"verilog_src": "",
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"pin": "reg1/CK",
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"net": "clk",
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"arrival": 0.000e+00,
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"slew": 0.000e+00
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}
|
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],
|
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"data_arrival_time": 1.045e-09,
|
|
"crpr": 0.000e+00,
|
|
"margin": 3.073e-11,
|
|
"required_time": 9.969e-09,
|
|
"slack": 8.924e-09
|
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}
|
|
]
|
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}
|
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--- report_checks -format json min ---
|
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{"checks": [
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{
|
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"type": "check",
|
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"path_group": "clk",
|
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"path_type": "min",
|
|
"startpoint": "in1",
|
|
"endpoint": "reg1/D",
|
|
"source_clock": "clk",
|
|
"source_clock_edge": "rise",
|
|
"source_path": [
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "in1",
|
|
"arrival": 1.000e-09,
|
|
"capacitance": 9.181e-16,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "and1",
|
|
"cell": "AND2_X1",
|
|
"verilog_src": "",
|
|
"pin": "and1/A1",
|
|
"net": "in1",
|
|
"arrival": 1.000e-09,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "and1",
|
|
"cell": "AND2_X1",
|
|
"verilog_src": "",
|
|
"pin": "and1/ZN",
|
|
"net": "n1",
|
|
"arrival": 1.024e-09,
|
|
"capacitance": 9.747e-16,
|
|
"slew": 7.000e-12
|
|
},
|
|
{
|
|
"instance": "buf1",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf1/A",
|
|
"net": "n1",
|
|
"arrival": 1.024e-09,
|
|
"slew": 7.000e-12
|
|
},
|
|
{
|
|
"instance": "buf1",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf1/Z",
|
|
"net": "n2",
|
|
"arrival": 1.044e-09,
|
|
"capacitance": 1.140e-15,
|
|
"slew": 5.947e-12
|
|
},
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/D",
|
|
"net": "n2",
|
|
"arrival": 1.044e-09,
|
|
"slew": 5.947e-12
|
|
}
|
|
],
|
|
"target_clock": "clk",
|
|
"target_clock_edge": "rise",
|
|
"target_clock_path": [
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "clk",
|
|
"arrival": 0.000e+00,
|
|
"capacitance": 9.497e-16,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/CK",
|
|
"net": "clk",
|
|
"arrival": 0.000e+00,
|
|
"slew": 0.000e+00
|
|
}
|
|
],
|
|
"data_arrival_time": 1.044e-09,
|
|
"crpr": -0.000e+00,
|
|
"margin": 4.894e-12,
|
|
"required_time": 4.894e-12,
|
|
"slack": 1.039e-09
|
|
}
|
|
]
|
|
}
|
|
--- report_checks -format json min_max ---
|
|
{"checks": [
|
|
{
|
|
"type": "check",
|
|
"path_group": "clk",
|
|
"path_type": "min",
|
|
"startpoint": "in1",
|
|
"endpoint": "reg1/D",
|
|
"source_clock": "clk",
|
|
"source_clock_edge": "rise",
|
|
"source_path": [
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "in1",
|
|
"arrival": 1.000e-09,
|
|
"capacitance": 9.181e-16,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "and1",
|
|
"cell": "AND2_X1",
|
|
"verilog_src": "",
|
|
"pin": "and1/A1",
|
|
"net": "in1",
|
|
"arrival": 1.000e-09,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "and1",
|
|
"cell": "AND2_X1",
|
|
"verilog_src": "",
|
|
"pin": "and1/ZN",
|
|
"net": "n1",
|
|
"arrival": 1.024e-09,
|
|
"capacitance": 9.747e-16,
|
|
"slew": 7.000e-12
|
|
},
|
|
{
|
|
"instance": "buf1",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf1/A",
|
|
"net": "n1",
|
|
"arrival": 1.024e-09,
|
|
"slew": 7.000e-12
|
|
},
|
|
{
|
|
"instance": "buf1",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf1/Z",
|
|
"net": "n2",
|
|
"arrival": 1.044e-09,
|
|
"capacitance": 1.140e-15,
|
|
"slew": 5.947e-12
|
|
},
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/D",
|
|
"net": "n2",
|
|
"arrival": 1.044e-09,
|
|
"slew": 5.947e-12
|
|
}
|
|
],
|
|
"target_clock": "clk",
|
|
"target_clock_edge": "rise",
|
|
"target_clock_path": [
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "clk",
|
|
"arrival": 0.000e+00,
|
|
"capacitance": 9.497e-16,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/CK",
|
|
"net": "clk",
|
|
"arrival": 0.000e+00,
|
|
"slew": 0.000e+00
|
|
}
|
|
],
|
|
"data_arrival_time": 1.044e-09,
|
|
"crpr": -0.000e+00,
|
|
"margin": 4.894e-12,
|
|
"required_time": 4.894e-12,
|
|
"slack": 1.039e-09
|
|
},
|
|
{
|
|
"type": "output_delay",
|
|
"path_group": "clk",
|
|
"path_type": "max",
|
|
"startpoint": "reg1/Q",
|
|
"endpoint": "out1",
|
|
"source_clock": "clk",
|
|
"source_clock_edge": "rise",
|
|
"source_clock_path": [
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "clk",
|
|
"arrival": 0.000e+00,
|
|
"capacitance": 9.497e-16,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/CK",
|
|
"net": "clk",
|
|
"arrival": 0.000e+00,
|
|
"slew": 0.000e+00
|
|
}
|
|
],
|
|
"source_path": [
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/Q",
|
|
"net": "n3",
|
|
"arrival": 8.371e-11,
|
|
"capacitance": 9.747e-16,
|
|
"slew": 7.314e-12
|
|
},
|
|
{
|
|
"instance": "buf2",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf2/A",
|
|
"net": "n3",
|
|
"arrival": 8.371e-11,
|
|
"slew": 7.314e-12
|
|
},
|
|
{
|
|
"instance": "buf2",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf2/Z",
|
|
"net": "out1",
|
|
"arrival": 1.003e-10,
|
|
"capacitance": 0.000e+00,
|
|
"slew": 3.638e-12
|
|
},
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "out1",
|
|
"arrival": 1.003e-10,
|
|
"slew": 3.638e-12
|
|
}
|
|
],
|
|
"target_clock": "clk",
|
|
"target_clock_edge": "rise",
|
|
"data_arrival_time": 1.003e-10,
|
|
"crpr": 0.000e+00,
|
|
"margin": 2.000e-09,
|
|
"required_time": 8.000e-09,
|
|
"slack": 7.900e-09
|
|
}
|
|
]
|
|
}
|
|
--- report_checks -format json to specific pin ---
|
|
{"checks": [
|
|
{
|
|
"type": "check",
|
|
"path_group": "clk",
|
|
"path_type": "max",
|
|
"startpoint": "in2",
|
|
"endpoint": "reg1/D",
|
|
"source_clock": "clk",
|
|
"source_clock_edge": "rise",
|
|
"source_path": [
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "in2",
|
|
"arrival": 1.000e-09,
|
|
"capacitance": 8.941e-16,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "and1",
|
|
"cell": "AND2_X1",
|
|
"verilog_src": "",
|
|
"pin": "and1/A2",
|
|
"net": "in2",
|
|
"arrival": 1.000e-09,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "and1",
|
|
"cell": "AND2_X1",
|
|
"verilog_src": "",
|
|
"pin": "and1/ZN",
|
|
"net": "n1",
|
|
"arrival": 1.025e-09,
|
|
"capacitance": 8.752e-16,
|
|
"slew": 5.258e-12
|
|
},
|
|
{
|
|
"instance": "buf1",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf1/A",
|
|
"net": "n1",
|
|
"arrival": 1.025e-09,
|
|
"slew": 5.258e-12
|
|
},
|
|
{
|
|
"instance": "buf1",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf1/Z",
|
|
"net": "n2",
|
|
"arrival": 1.048e-09,
|
|
"capacitance": 1.062e-15,
|
|
"slew": 5.011e-12
|
|
},
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/D",
|
|
"net": "n2",
|
|
"arrival": 1.048e-09,
|
|
"slew": 5.011e-12
|
|
}
|
|
],
|
|
"target_clock": "clk",
|
|
"target_clock_edge": "rise",
|
|
"target_clock_path": [
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "clk",
|
|
"arrival": 0.000e+00,
|
|
"capacitance": 9.497e-16,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/CK",
|
|
"net": "clk",
|
|
"arrival": 0.000e+00,
|
|
"slew": 0.000e+00
|
|
}
|
|
],
|
|
"data_arrival_time": 1.048e-09,
|
|
"crpr": 0.000e+00,
|
|
"margin": 3.878e-11,
|
|
"required_time": 9.961e-09,
|
|
"slack": 8.913e-09
|
|
}
|
|
]
|
|
}
|
|
--- report_checks -format json from specific port ---
|
|
{"checks": [
|
|
{
|
|
"type": "check",
|
|
"path_group": "clk",
|
|
"path_type": "max",
|
|
"startpoint": "in1",
|
|
"endpoint": "reg1/D",
|
|
"source_clock": "clk",
|
|
"source_clock_edge": "rise",
|
|
"source_path": [
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "in1",
|
|
"arrival": 1.000e-09,
|
|
"capacitance": 8.748e-16,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "and1",
|
|
"cell": "AND2_X1",
|
|
"verilog_src": "",
|
|
"pin": "and1/A1",
|
|
"net": "in1",
|
|
"arrival": 1.000e-09,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "and1",
|
|
"cell": "AND2_X1",
|
|
"verilog_src": "",
|
|
"pin": "and1/ZN",
|
|
"net": "n1",
|
|
"arrival": 1.022e-09,
|
|
"capacitance": 8.752e-16,
|
|
"slew": 5.258e-12
|
|
},
|
|
{
|
|
"instance": "buf1",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf1/A",
|
|
"net": "n1",
|
|
"arrival": 1.022e-09,
|
|
"slew": 5.258e-12
|
|
},
|
|
{
|
|
"instance": "buf1",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf1/Z",
|
|
"net": "n2",
|
|
"arrival": 1.046e-09,
|
|
"capacitance": 1.062e-15,
|
|
"slew": 5.011e-12
|
|
},
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/D",
|
|
"net": "n2",
|
|
"arrival": 1.046e-09,
|
|
"slew": 5.011e-12
|
|
}
|
|
],
|
|
"target_clock": "clk",
|
|
"target_clock_edge": "rise",
|
|
"target_clock_path": [
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "clk",
|
|
"arrival": 0.000e+00,
|
|
"capacitance": 9.497e-16,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/CK",
|
|
"net": "clk",
|
|
"arrival": 0.000e+00,
|
|
"slew": 0.000e+00
|
|
}
|
|
],
|
|
"data_arrival_time": 1.046e-09,
|
|
"crpr": 0.000e+00,
|
|
"margin": 3.878e-11,
|
|
"required_time": 9.961e-09,
|
|
"slack": 8.915e-09
|
|
}
|
|
]
|
|
}
|
|
--- report_checks -format json through pin ---
|
|
{"checks": [
|
|
{
|
|
"type": "check",
|
|
"path_group": "clk",
|
|
"path_type": "max",
|
|
"startpoint": "in2",
|
|
"endpoint": "reg1/D",
|
|
"source_clock": "clk",
|
|
"source_clock_edge": "rise",
|
|
"source_path": [
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "in2",
|
|
"arrival": 1.000e-09,
|
|
"capacitance": 8.941e-16,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "and1",
|
|
"cell": "AND2_X1",
|
|
"verilog_src": "",
|
|
"pin": "and1/A2",
|
|
"net": "in2",
|
|
"arrival": 1.000e-09,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "and1",
|
|
"cell": "AND2_X1",
|
|
"verilog_src": "",
|
|
"pin": "and1/ZN",
|
|
"net": "n1",
|
|
"arrival": 1.025e-09,
|
|
"capacitance": 8.752e-16,
|
|
"slew": 5.258e-12
|
|
},
|
|
{
|
|
"instance": "buf1",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf1/A",
|
|
"net": "n1",
|
|
"arrival": 1.025e-09,
|
|
"slew": 5.258e-12
|
|
},
|
|
{
|
|
"instance": "buf1",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf1/Z",
|
|
"net": "n2",
|
|
"arrival": 1.048e-09,
|
|
"capacitance": 1.062e-15,
|
|
"slew": 5.011e-12
|
|
},
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/D",
|
|
"net": "n2",
|
|
"arrival": 1.048e-09,
|
|
"slew": 5.011e-12
|
|
}
|
|
],
|
|
"target_clock": "clk",
|
|
"target_clock_edge": "rise",
|
|
"target_clock_path": [
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "clk",
|
|
"arrival": 0.000e+00,
|
|
"capacitance": 9.497e-16,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/CK",
|
|
"net": "clk",
|
|
"arrival": 0.000e+00,
|
|
"slew": 0.000e+00
|
|
}
|
|
],
|
|
"data_arrival_time": 1.048e-09,
|
|
"crpr": 0.000e+00,
|
|
"margin": 3.878e-11,
|
|
"required_time": 9.961e-09,
|
|
"slack": 8.913e-09
|
|
}
|
|
]
|
|
}
|
|
--- report_checks -unconstrained format full ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.02 0.10 ^ buf2/Z (BUF_X1)
|
|
0.00 0.10 ^ out1 (out)
|
|
0.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-2.00 8.00 output external delay
|
|
8.00 data required time
|
|
---------------------------------------------------------
|
|
8.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
7.90 slack (MET)
|
|
|
|
|
|
--- report_checks -unconstrained format short ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
|
|
--- report_checks -unconstrained format end ---
|
|
max_delay/setup group clk
|
|
|
|
Required Actual
|
|
Endpoint Delay Delay Slack
|
|
------------------------------------------------------------
|
|
out1 (output) 8.00 0.10 7.90 (MET)
|
|
|
|
--- report_checks -unconstrained format slack_only ---
|
|
Group Slack
|
|
--------------------------------------------
|
|
clk 7.90
|
|
|
|
--- report_path on individual path (json format) ---
|
|
{
|
|
"path": [
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/Q",
|
|
"net": "n3",
|
|
"arrival": 8.371e-11,
|
|
"capacitance": 9.747e-16,
|
|
"slew": 7.314e-12
|
|
},
|
|
{
|
|
"instance": "buf2",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf2/A",
|
|
"net": "n3",
|
|
"arrival": 8.371e-11,
|
|
"slew": 7.314e-12
|
|
},
|
|
{
|
|
"instance": "buf2",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf2/Z",
|
|
"net": "out1",
|
|
"arrival": 1.003e-10,
|
|
"capacitance": 0.000e+00,
|
|
"slew": 3.638e-12
|
|
},
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "out1",
|
|
"arrival": 1.003e-10,
|
|
"slew": 3.638e-12
|
|
}
|
|
]
|
|
}
|
|
|
|
{
|
|
"path": [
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/Q",
|
|
"net": "n3",
|
|
"arrival": 7.722e-11,
|
|
"capacitance": 8.752e-16,
|
|
"slew": 5.624e-12
|
|
},
|
|
{
|
|
"instance": "buf2",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf2/A",
|
|
"net": "n3",
|
|
"arrival": 7.722e-11,
|
|
"slew": 5.624e-12
|
|
},
|
|
{
|
|
"instance": "buf2",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf2/Z",
|
|
"net": "out1",
|
|
"arrival": 9.857e-11,
|
|
"capacitance": 0.000e+00,
|
|
"slew": 3.903e-12
|
|
},
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "out1",
|
|
"arrival": 9.857e-11,
|
|
"slew": 3.903e-12
|
|
}
|
|
]
|
|
}
|
|
|
|
{
|
|
"path": [
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "in2",
|
|
"arrival": 1.000e-09,
|
|
"capacitance": 8.941e-16,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "and1",
|
|
"cell": "AND2_X1",
|
|
"verilog_src": "",
|
|
"pin": "and1/A2",
|
|
"net": "in2",
|
|
"arrival": 1.000e-09,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "and1",
|
|
"cell": "AND2_X1",
|
|
"verilog_src": "",
|
|
"pin": "and1/ZN",
|
|
"net": "n1",
|
|
"arrival": 1.025e-09,
|
|
"capacitance": 8.752e-16,
|
|
"slew": 5.258e-12
|
|
},
|
|
{
|
|
"instance": "buf1",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf1/A",
|
|
"net": "n1",
|
|
"arrival": 1.025e-09,
|
|
"slew": 5.258e-12
|
|
},
|
|
{
|
|
"instance": "buf1",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf1/Z",
|
|
"net": "n2",
|
|
"arrival": 1.048e-09,
|
|
"capacitance": 1.062e-15,
|
|
"slew": 5.011e-12
|
|
},
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/D",
|
|
"net": "n2",
|
|
"arrival": 1.048e-09,
|
|
"slew": 5.011e-12
|
|
}
|
|
]
|
|
}
|
|
|
|
--- reportPathFull on a single path ---
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.02 0.10 ^ buf2/Z (BUF_X1)
|
|
0.00 0.10 ^ out1 (out)
|
|
--- json report with full_clock format (for source clock paths) ---
|
|
{"checks": [
|
|
{
|
|
"type": "output_delay",
|
|
"path_group": "clk",
|
|
"path_type": "max",
|
|
"startpoint": "reg1/Q",
|
|
"endpoint": "out1",
|
|
"source_clock": "clk",
|
|
"source_clock_edge": "rise",
|
|
"source_clock_path": [
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "clk",
|
|
"arrival": 0.000e+00,
|
|
"capacitance": 9.497e-16,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/CK",
|
|
"net": "clk",
|
|
"arrival": 0.000e+00,
|
|
"slew": 0.000e+00
|
|
}
|
|
],
|
|
"source_path": [
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/Q",
|
|
"net": "n3",
|
|
"arrival": 8.371e-11,
|
|
"capacitance": 9.747e-16,
|
|
"slew": 7.314e-12
|
|
},
|
|
{
|
|
"instance": "buf2",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf2/A",
|
|
"net": "n3",
|
|
"arrival": 8.371e-11,
|
|
"slew": 7.314e-12
|
|
},
|
|
{
|
|
"instance": "buf2",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf2/Z",
|
|
"net": "out1",
|
|
"arrival": 1.003e-10,
|
|
"capacitance": 0.000e+00,
|
|
"slew": 3.638e-12
|
|
},
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "out1",
|
|
"arrival": 1.003e-10,
|
|
"slew": 3.638e-12
|
|
}
|
|
],
|
|
"target_clock": "clk",
|
|
"target_clock_edge": "rise",
|
|
"data_arrival_time": 1.003e-10,
|
|
"crpr": 0.000e+00,
|
|
"margin": 2.000e-09,
|
|
"required_time": 8.000e-09,
|
|
"slack": 7.900e-09
|
|
}
|
|
]
|
|
}
|
|
--- report_checks -format json -sort_by_slack ---
|
|
{"checks": [
|
|
{
|
|
"type": "output_delay",
|
|
"path_group": "clk",
|
|
"path_type": "max",
|
|
"startpoint": "reg1/Q",
|
|
"endpoint": "out1",
|
|
"source_clock": "clk",
|
|
"source_clock_edge": "rise",
|
|
"source_clock_path": [
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "clk",
|
|
"arrival": 0.000e+00,
|
|
"capacitance": 9.497e-16,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/CK",
|
|
"net": "clk",
|
|
"arrival": 0.000e+00,
|
|
"slew": 0.000e+00
|
|
}
|
|
],
|
|
"source_path": [
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/Q",
|
|
"net": "n3",
|
|
"arrival": 8.371e-11,
|
|
"capacitance": 9.747e-16,
|
|
"slew": 7.314e-12
|
|
},
|
|
{
|
|
"instance": "buf2",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf2/A",
|
|
"net": "n3",
|
|
"arrival": 8.371e-11,
|
|
"slew": 7.314e-12
|
|
},
|
|
{
|
|
"instance": "buf2",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf2/Z",
|
|
"net": "out1",
|
|
"arrival": 1.003e-10,
|
|
"capacitance": 0.000e+00,
|
|
"slew": 3.638e-12
|
|
},
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "out1",
|
|
"arrival": 1.003e-10,
|
|
"slew": 3.638e-12
|
|
}
|
|
],
|
|
"target_clock": "clk",
|
|
"target_clock_edge": "rise",
|
|
"data_arrival_time": 1.003e-10,
|
|
"crpr": 0.000e+00,
|
|
"margin": 2.000e-09,
|
|
"required_time": 8.000e-09,
|
|
"slack": 7.900e-09
|
|
}
|
|
]
|
|
}
|
|
--- report_checks min with fields ---
|
|
Startpoint: in1 (input port clocked by clk)
|
|
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: min
|
|
|
|
Fanout Cap Slew Delay Time Description
|
|
-----------------------------------------------------------------------------
|
|
0.00 0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 ^ input external delay
|
|
1 0.92 0.00 0.00 1.00 ^ in1 (in)
|
|
in1 (net)
|
|
0.00 0.00 1.00 ^ and1/A1 (AND2_X1)
|
|
1 0.97 0.01 0.02 1.02 ^ and1/ZN (AND2_X1)
|
|
n1 (net)
|
|
0.01 0.00 1.02 ^ buf1/A (BUF_X1)
|
|
1 1.14 0.01 0.02 1.04 ^ buf1/Z (BUF_X1)
|
|
n2 (net)
|
|
0.01 0.00 1.04 ^ reg1/D (DFF_X1)
|
|
1.04 data arrival time
|
|
|
|
0.00 0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 clock reconvergence pessimism
|
|
0.00 ^ reg1/CK (DFF_X1)
|
|
0.00 0.00 library hold time
|
|
0.00 data required time
|
|
-----------------------------------------------------------------------------
|
|
0.00 data required time
|
|
-1.04 data arrival time
|
|
-----------------------------------------------------------------------------
|
|
1.04 slack (MET)
|
|
|
|
|
|
--- report_checks with -digits ---
|
|
{"checks": [
|
|
{
|
|
"type": "output_delay",
|
|
"path_group": "clk",
|
|
"path_type": "max",
|
|
"startpoint": "reg1/Q",
|
|
"endpoint": "out1",
|
|
"source_clock": "clk",
|
|
"source_clock_edge": "rise",
|
|
"source_clock_path": [
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "clk",
|
|
"arrival": 0.000e+00,
|
|
"capacitance": 9.497e-16,
|
|
"slew": 0.000e+00
|
|
},
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/CK",
|
|
"net": "clk",
|
|
"arrival": 0.000e+00,
|
|
"slew": 0.000e+00
|
|
}
|
|
],
|
|
"source_path": [
|
|
{
|
|
"instance": "reg1",
|
|
"cell": "DFF_X1",
|
|
"verilog_src": "",
|
|
"pin": "reg1/Q",
|
|
"net": "n3",
|
|
"arrival": 8.371e-11,
|
|
"capacitance": 9.747e-16,
|
|
"slew": 7.314e-12
|
|
},
|
|
{
|
|
"instance": "buf2",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf2/A",
|
|
"net": "n3",
|
|
"arrival": 8.371e-11,
|
|
"slew": 7.314e-12
|
|
},
|
|
{
|
|
"instance": "buf2",
|
|
"cell": "BUF_X1",
|
|
"verilog_src": "",
|
|
"pin": "buf2/Z",
|
|
"net": "out1",
|
|
"arrival": 1.003e-10,
|
|
"capacitance": 0.000e+00,
|
|
"slew": 3.638e-12
|
|
},
|
|
{
|
|
"instance": "",
|
|
"cell": "search_test1",
|
|
"verilog_src": "",
|
|
"pin": "out1",
|
|
"arrival": 1.003e-10,
|
|
"slew": 3.638e-12
|
|
}
|
|
],
|
|
"target_clock": "clk",
|
|
"target_clock_edge": "rise",
|
|
"data_arrival_time": 1.003e-10,
|
|
"crpr": 0.000e+00,
|
|
"margin": 2.000e-09,
|
|
"required_time": 8.000e-09,
|
|
"slack": 7.900e-09
|
|
}
|
|
]
|
|
}
|