323 lines
9.6 KiB
Plaintext
323 lines
9.6 KiB
Plaintext
--- report_tns max ---
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tns max 0.00
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--- report_tns min ---
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tns min 0.00
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--- report_wns max ---
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wns max 0.00
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--- report_wns min ---
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wns min 0.00
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--- report_worst_slack max ---
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worst slack max 7.90
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--- report_worst_slack min ---
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worst slack min 1.04
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--- check_setup verbose ---
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--- check_setup specific flags ---
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--- check_setup no_clock ---
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--- check_setup unconstrained ---
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--- check_setup loops ---
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--- check_setup generated_clocks ---
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--- report_check_types verbose ---
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ in1 (in)
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0.02 1.02 ^ and1/ZN (AND2_X1)
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0.02 1.04 ^ buf1/Z (BUF_X1)
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0.00 1.04 ^ reg1/D (DFF_X1)
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1.04 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.04 data arrival time
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---------------------------------------------------------
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1.04 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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max slew
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Pin reg1/QN v
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max slew 0.20
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slew 0.01
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----------------
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Slack 0.19 (MET)
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max capacitance
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Pin buf1/Z ^
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max capacitance 60.65
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capacitance 1.14
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-----------------------
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Slack 59.51 (MET)
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Pin: reg1/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 reg1/CK
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0.00 open edge arrival time
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5.00 5.00 clock clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 reg1/CK
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0.00 5.00 clock reconvergence pessimism
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5.00 close edge arrival time
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---------------------------------------------------------
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0.05 required pulse width (high)
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5.00 actual pulse width
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---------------------------------------------------------
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4.95 slack (MET)
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--- report_check_types max_delay ---
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Group Slack
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--------------------------------------------
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clk 7.90
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--- report_check_types min_delay ---
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Group Slack
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--------------------------------------------
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clk 1.04
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--- report_check_types max_slew ---
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max slew
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Pin Limit Slew Slack
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------------------------------------------------------------
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reg1/QN 0.20 0.01 0.19 (MET)
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--- report_check_types max_fanout ---
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--- report_check_types max_capacitance ---
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max capacitance
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Pin Limit Cap Slack
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------------------------------------------------------------
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buf1/Z 60.65 1.14 59.51 (MET)
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--- report_check_types min_pulse_width ---
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Required Actual
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Pin Width Width Slack
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------------------------------------------------------------
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reg1/CK (high) 0.05 5.00 4.95 (MET)
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--- report_check_types min_period ---
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--- report_check_types max_skew ---
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--- report_check_types violators ---
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Group Slack
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--------------------------------------------
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No paths found.
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--- report_clock_skew setup ---
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Clock clk
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No launch/capture paths found.
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--- report_clock_skew hold ---
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Clock clk
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No launch/capture paths found.
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--- report_clock_skew -include_internal_latency ---
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Clock clk
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No launch/capture paths found.
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--- report_clock_latency ---
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Clock clk
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rise -> rise
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min max
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0.00 0.00 source latency
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0.00 network latency reg1/CK
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0.00 network latency reg1/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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fall -> fall
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min max
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0.00 0.00 source latency
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0.00 network latency reg1/CK
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0.00 network latency reg1/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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--- report_clock_latency -include_internal_latency ---
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Clock clk
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rise -> rise
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min max
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0.00 0.00 source latency
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0.00 network latency reg1/CK
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0.00 network latency reg1/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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fall -> fall
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min max
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0.00 0.00 source latency
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0.00 network latency reg1/CK
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0.00 network latency reg1/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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--- report_clock_min_period ---
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clk period_min = 0.00 fmax = inf
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--- report_clock_min_period -include_port_paths ---
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clk period_min = 2.10 fmax = 476.13
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--- report_clock_properties ---
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Clock Period Waveform
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----------------------------------------------------
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clk 10.00 0.00 5.00
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--- report_clock_properties clk ---
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Clock Period Waveform
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----------------------------------------------------
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clk 10.00 0.00 5.00
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--- report_pulse_width_checks ---
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Required Actual
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Pin Width Width Slack
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------------------------------------------------------------
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reg1/CK (high) 0.05 5.00 4.95 (MET)
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reg1/CK (low) 0.05 5.00 4.95 (MET)
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--- report_pulse_width_checks verbose ---
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Pin: reg1/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 reg1/CK
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0.00 open edge arrival time
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5.00 5.00 clock clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 reg1/CK
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0.00 5.00 clock reconvergence pessimism
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5.00 close edge arrival time
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---------------------------------------------------------
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0.05 required pulse width (high)
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5.00 actual pulse width
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---------------------------------------------------------
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4.95 slack (MET)
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Pin: reg1/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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5.00 5.00 clock clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 reg1/CK
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5.00 open edge arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 reg1/CK
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0.00 10.00 clock reconvergence pessimism
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10.00 close edge arrival time
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---------------------------------------------------------
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0.05 required pulse width (low)
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5.00 actual pulse width
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---------------------------------------------------------
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4.95 slack (MET)
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--- report_pulse_width_checks on pin ---
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Required Actual
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Pin Width Width Slack
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------------------------------------------------------------
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reg1/CK (high) 0.05 5.00 4.95 (MET)
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reg1/CK (low) 0.05 5.00 4.95 (MET)
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--- report_disabled_edges ---
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--- report_constant on instance ---
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VDD X
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VSS X
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A1 X
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A2 X
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ZN X
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--- report_constant on pin ---
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A1 X
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--- find_timing_paths max ---
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Found 1 max paths
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--- find_timing_paths min ---
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Found 1 min paths
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--- find_timing_paths min_max ---
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Found 2 min_max paths
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--- find_timing_paths with constraints ---
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Found 1 paths from in1
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--- find_timing_paths -endpoint_path_count ---
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Found 3 paths with endpoint_path_count 3
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--- find_timing_paths -group_path_count ---
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Found 5 paths with group_path_count 5
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--- find_timing_paths -sort_by_slack ---
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Found 3 sorted paths
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--- find_timing_paths -unique_paths_to_endpoint ---
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Found 3 unique paths
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--- find_timing_paths -slack_max ---
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Found 1 paths with slack_max 100
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--- report_tns with digits ---
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tns max 0.000000
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--- report_wns with digits ---
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wns max 0.000000
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--- report_worst_slack with digits ---
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worst slack max 7.899714
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--- report_arrival ---
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(clk ^) r 0.08:0.08 f 0.08:0.08
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--- report_required ---
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(clk ^) r 0.00:9.97 f 0.00:9.96
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--- report_slack ---
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(clk ^) r 1.04:8.92 f 1.04:8.91
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--- worst_slack hidden cmd ---
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Worst slack (max): 7.899713995438537
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--- worst_slack min ---
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Worst slack (min): 1.0391781063125174
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--- total_negative_slack hidden cmd ---
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TNS (max): 0.0
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--- worst_negative_slack hidden cmd ---
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WNS (max): 0.0
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