252 lines
12 KiB
Plaintext
252 lines
12 KiB
Plaintext
--- first read_sdf ---
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Startpoint: d (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ d (in)
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0.15 0.15 ^ buf1/Z (BUF_X1)
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0.12 0.27 ^ buf2/Z (BUF_X2)
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0.15 0.42 ^ and1/ZN (AND2_X1)
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0.03 0.45 ^ reg1/D (DFF_X1)
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0.45 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.10 9.90 library setup time
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9.90 data required time
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---------------------------------------------------------
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9.90 data required time
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-0.45 data arrival time
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---------------------------------------------------------
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9.45 slack (MET)
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--- report_annotated before re-read ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 6 0
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----------------------------------------------------------------
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6 6 0
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Annotated Arcs
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delay and1/A1 -> and1/ZN
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delay and1/A2 -> and1/ZN
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delay buf1/A -> buf1/Z
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delay buf2/A -> buf2/Z
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delay reg1/CK -> reg1/QN
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delay reg1/CK -> reg1/Q
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 1 0
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----------------------------------------------------------------
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1 1 0
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Annotated Arcs
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setup reg1/CK -> reg1/D
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 6 0
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internal net arcs 3 3 0
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net arcs from primary inputs 3 0 3
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net arcs to primary outputs 1 0 1
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----------------------------------------------------------------
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13 9 4
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Unannotated Arcs
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primary input net clk -> reg1/CK
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primary input net d -> buf1/A
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primary input net en -> and1/A2
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primary output net reg1/Q -> q
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 1 0
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cell hold arcs 1 1 0
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cell width arcs 1 1 0
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----------------------------------------------------------------
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3 3 0
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Unannotated Arcs
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--- write_sdf before re-read ---
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--- re-read_sdf ---
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Startpoint: d (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ d (in)
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0.15 0.15 ^ buf1/Z (BUF_X1)
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0.12 0.27 ^ buf2/Z (BUF_X2)
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0.15 0.42 ^ and1/ZN (AND2_X1)
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0.03 0.45 ^ reg1/D (DFF_X1)
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0.45 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.10 9.90 library setup time
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9.90 data required time
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---------------------------------------------------------
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9.90 data required time
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-0.45 data arrival time
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---------------------------------------------------------
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9.45 slack (MET)
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 6 0
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internal net arcs 3 3 0
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net arcs from primary inputs 3 0 3
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net arcs to primary outputs 1 0 1
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----------------------------------------------------------------
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13 9 4
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 1 0
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cell hold arcs 1 1 0
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cell width arcs 1 1 0
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----------------------------------------------------------------
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3 3 0
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--- write-read roundtrip ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: q (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.35 0.35 ^ reg1/Q (DFF_X1)
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0.00 0.35 ^ q (out)
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0.35 data arrival time
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5.00 5.00 clock clk (rise edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 clock reconvergence pessimism
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-2.00 3.00 output external delay
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3.00 data required time
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---------------------------------------------------------
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3.00 data required time
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-0.35 data arrival time
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---------------------------------------------------------
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2.65 slack (MET)
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 6 0
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----------------------------------------------------------------
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6 6 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 1 0
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cell hold arcs 1 1 0
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----------------------------------------------------------------
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2 2 0
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--- write with dot divider ---
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--- report_annotated_delay max_lines variations ---
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 6 0
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internal net arcs 3 3 0
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net arcs from primary inputs 3 3 0
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net arcs to primary outputs 1 1 0
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----------------------------------------------------------------
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13 13 0
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 6 0
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internal net arcs 3 3 0
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net arcs from primary inputs 3 3 0
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net arcs to primary outputs 1 1 0
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----------------------------------------------------------------
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13 13 0
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 6 0
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internal net arcs 3 3 0
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net arcs from primary inputs 3 3 0
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net arcs to primary outputs 1 1 0
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----------------------------------------------------------------
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13 13 0
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 6 6 0
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internal net arcs 3 3 0
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net arcs from primary inputs 3 3 0
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net arcs to primary outputs 1 1 0
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----------------------------------------------------------------
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13 13 0
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--- report_annotated_check max_lines variations ---
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 1 0
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cell hold arcs 1 1 0
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cell width arcs 1 1 0
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----------------------------------------------------------------
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3 3 0
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 1 1 0
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cell hold arcs 1 1 0
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cell width arcs 1 1 0
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----------------------------------------------------------------
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3 3 0
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--- gzip write-read roundtrip ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: q (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.35 0.35 ^ reg1/Q (DFF_X1)
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0.00 0.35 ^ q (out)
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0.35 data arrival time
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5.00 5.00 clock clk (rise edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 clock reconvergence pessimism
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-2.00 3.00 output external delay
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3.00 data required time
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---------------------------------------------------------
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3.00 data required time
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-0.35 data arrival time
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---------------------------------------------------------
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2.65 slack (MET)
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